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Searched refs:FIELD_PREP (Results 1 – 25 of 791) sorted by relevance

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/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
[all …]
/linux/drivers/iio/adc/
H A Dstm32-dfsdm.h52 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
54 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
56 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
58 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
60 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
62 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
64 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
66 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
68 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
70 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
[all …]
/linux/drivers/tty/serial/
H A Datmel_serial.h44 #define ATMEL_US_USMODE_NORMAL FIELD_PREP(ATMEL_US_USMODE, 0)
45 #define ATMEL_US_USMODE_RS485 FIELD_PREP(ATMEL_US_USMODE, 1)
46 #define ATMEL_US_USMODE_HWHS FIELD_PREP(ATMEL_US_USMODE, 2)
47 #define ATMEL_US_USMODE_MODEM FIELD_PREP(ATMEL_US_USMODE, 3)
48 #define ATMEL_US_USMODE_ISO7816_T0 FIELD_PREP(ATMEL_US_USMODE, 4)
49 #define ATMEL_US_USMODE_ISO7816_T1 FIELD_PREP(ATMEL_US_USMODE, 6)
50 #define ATMEL_US_USMODE_IRDA FIELD_PREP(ATMEL_US_USMODE, 8)
52 #define ATMEL_US_USCLKS_MCK FIELD_PREP(ATMEL_US_USCLKS, 0)
53 #define ATMEL_US_USCLKS_MCK_DIV8 FIELD_PREP(ATMEL_US_USCLKS, 1)
54 #define ATMEL_US_USCLKS_GCLK FIELD_PREP(ATMEL_US_USCLKS, 2)
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
63 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
75 FIELD_PREP(ANA_ANAINTR_INTR, x)
81 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
90 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
99 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x)
108 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x)
117 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x)
[all …]
/linux/drivers/infiniband/hw/irdma/
H A Duda.c31 qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | in irdma_sc_access_ah()
32 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | in irdma_sc_access_ah()
33 FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); in irdma_sc_access_ah()
35 qw2 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ARPINDEX, info->dst_arpindex) | in irdma_sc_access_ah()
36 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_FLOWLABEL, info->flow_label) | in irdma_sc_access_ah()
37 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | in irdma_sc_access_ah()
38 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXHI, info->pd_idx >> 16); in irdma_sc_access_ah()
42 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) | in irdma_sc_access_ah()
43 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1])); in irdma_sc_access_ah()
45 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) | in irdma_sc_access_ah()
[all …]
H A Dctrl.c204 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_add_arp_cache_entry()
205 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) | in irdma_sc_add_arp_cache_entry()
206 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) | in irdma_sc_add_arp_cache_entry()
207 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_add_arp_cache_entry()
238 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_del_arp_cache_entry()
239 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_del_arp_cache_entry()
273 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | in irdma_sc_manage_apbvt_entry()
274 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | in irdma_sc_manage_apbvt_entry()
275 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_manage_apbvt_entry()
324 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | in irdma_sc_manage_qhash_table_entry()
[all …]
H A Duk.c20 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment()
22 FIELD_PREP(IRDMAQPSQ_VALID, valid) | in irdma_set_fragment()
23 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | in irdma_set_fragment()
24 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); in irdma_set_fragment()
28 FIELD_PREP(IRDMAQPSQ_VALID, valid)); in irdma_set_fragment()
44 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment_gen_1()
46 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->length) | in irdma_set_fragment_gen_1()
47 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->lkey)); in irdma_set_fragment_gen_1()
77 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | in irdma_nop_1()
78 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, signaled) | in irdma_nop_1()
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Dhal_tx.c43 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); in ath11k_hal_tx_cmd_desc_setup()
45 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, in ath11k_hal_tx_cmd_desc_setup()
48 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, ti->rbm_id) | in ath11k_hal_tx_cmd_desc_setup()
49 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); in ath11k_hal_tx_cmd_desc_setup()
52 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | in ath11k_hal_tx_cmd_desc_setup()
53 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | in ath11k_hal_tx_cmd_desc_setup()
54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, in ath11k_hal_tx_cmd_desc_setup()
56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, in ath11k_hal_tx_cmd_desc_setup()
58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, in ath11k_hal_tx_cmd_desc_setup()
60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, in ath11k_hal_tx_cmd_desc_setup()
[all …]
/linux/drivers/phy/amlogic/
H A Dphy-meson-g12a-usb2.c193 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
194 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | in phy_meson_g12a_usb2_init()
196 FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | in phy_meson_g12a_usb2_init()
202 FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) | in phy_meson_g12a_usb2_init()
203 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) | in phy_meson_g12a_usb2_init()
204 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) | in phy_meson_g12a_usb2_init()
205 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | in phy_meson_g12a_usb2_init()
206 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); in phy_meson_g12a_usb2_init()
208 value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | in phy_meson_g12a_usb2_init()
209 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | in phy_meson_g12a_usb2_init()
[all …]
/linux/drivers/crypto/ccree/
H A Dcc_hw_queue_defs.h224 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); in set_queue_last_ind_bit()
242 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr)); in set_din_type()
244 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | in set_din_type()
245 FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_type()
246 FIELD_PREP(WORD1_NS_BIT, axi_sec); in set_din_type()
260 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); in set_din_no_dma()
273 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE); in set_cpp_crypto_key()
274 pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); in set_cpp_crypto_key()
276 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot); in set_cpp_crypto_key()
291 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_sram()
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c78 #define STF_DPHY_LSHIFT_16(x) (FIELD_PREP(GENMASK(23, 16), (x)))
79 #define STF_DPHY_LSHIFT_8(x) (FIELD_PREP(GENMASK(15, 8), (x)))
217 writel(FIELD_PREP(STF_DPHY_RESETB, assert), in stf_dphy_hw_reset()
248 tmp |= FIELD_PREP(STF_DPHY_REFCLK_IN_SEL, STF_DPHY_REFCLK_12M); in stf_dphy_configure()
251 writel(FIELD_PREP(STF_DPHY_RG_CDTX_L0N_HSTX_RES, 0x10) | in stf_dphy_configure()
252 FIELD_PREP(STF_DPHY_RG_CDTX_L0P_HSTX_RES, 0x10), in stf_dphy_configure()
255 writel(FIELD_PREP(STF_DPHY_RG_CDTX_L0N_HSTX_RES, 0x10) | in stf_dphy_configure()
256 FIELD_PREP(STF_DPHY_RG_CDTX_L2N_HSTX_RES, 0x10) | in stf_dphy_configure()
257 FIELD_PREP(STF_DPHY_RG_CDTX_L3N_HSTX_RES, 0x10) | in stf_dphy_configure()
258 FIELD_PREP(STF_DPHY_RG_CDTX_L1P_HSTX_RES, 0x10) | in stf_dphy_configure()
[all …]
H A Dphy-jh7110-dphy-rx.c78 writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) | in stf_dphy_configure()
79 FIELD_PREP(STF_DPHY_ENABLE_CLK1, 1) | in stf_dphy_configure()
80 FIELD_PREP(STF_DPHY_ENABLE_LAN0, 1) | in stf_dphy_configure()
81 FIELD_PREP(STF_DPHY_ENABLE_LAN1, 1) | in stf_dphy_configure()
82 FIELD_PREP(STF_DPHY_ENABLE_LAN2, 1) | in stf_dphy_configure()
83 FIELD_PREP(STF_DPHY_ENABLE_LAN3, 1) | in stf_dphy_configure()
84 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | in stf_dphy_configure()
85 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | in stf_dphy_configure()
86 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | in stf_dphy_configure()
87 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), in stf_dphy_configure()
[all …]
/linux/drivers/phy/microchip/
H A Dlan966x_serdes_regs.h22 FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
28 FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
34 FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
40 FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
46 FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
52 FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
58 FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
64 FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
70 FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
76 FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-hdptx.c1014 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); in rk_hdptx_ropll_tmds_cmn_config()
1019 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); in rk_hdptx_ropll_tmds_cmn_config()
1025 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); in rk_hdptx_ropll_tmds_cmn_config()
1031 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); in rk_hdptx_ropll_tmds_cmn_config()
1034 FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1)); in rk_hdptx_ropll_tmds_cmn_config()
1037 FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); in rk_hdptx_ropll_tmds_cmn_config()
1082 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | in rk_hdptx_dp_reset()
1083 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); in rk_hdptx_dp_reset()
1086 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | in rk_hdptx_dp_reset()
1087 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); in rk_hdptx_dp_reset()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_guc_hxg_helpers.h73 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | in guc_hxg_msg_encode_success()
74 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_SUCCESS) | in guc_hxg_msg_encode_success()
75 FIELD_PREP(GUC_HXG_RESPONSE_MSG_0_DATA0, data0); in guc_hxg_msg_encode_success()
82 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | in guc_hxg_msg_encode_failure()
83 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_FAILURE) | in guc_hxg_msg_encode_failure()
84 FIELD_PREP(GUC_HXG_FAILURE_MSG_0_HINT, hint) | in guc_hxg_msg_encode_failure()
85 FIELD_PREP(GUC_HXG_FAILURE_MSG_0_ERROR, error); in guc_hxg_msg_encode_failure()
92 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | in guc_hxg_msg_encode_busy()
93 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_NO_RESPONSE_BUSY) | in guc_hxg_msg_encode_busy()
94 FIELD_PREP(GUC_HXG_BUSY_MSG_0_COUNTER, counter); in guc_hxg_msg_encode_busy()
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-qcom-common.c34 reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, in qcom_pcie_common_set_equalization()
43 reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | in qcom_pcie_common_set_equalization()
44 FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | in qcom_pcie_common_set_equalization()
45 FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) | in qcom_pcie_common_set_equalization()
46 FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5); in qcom_pcie_common_set_equalization()
68 reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | in qcom_pcie_common_set_16gt_lane_margining()
69 FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | in qcom_pcie_common_set_16gt_lane_margining()
70 FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | in qcom_pcie_common_set_16gt_lane_margining()
71 FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); in qcom_pcie_common_set_16gt_lane_margining()
83 reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) | in qcom_pcie_common_set_16gt_lane_margining()
[all …]
/linux/drivers/bus/mhi/
H A Dcommon.h121 #define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))
126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
127 FIELD_PREP(GENMASK(23, 16), \
133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
134 FIELD_PREP(GENMASK(23, 16), \
140 #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
141 FIELD_PREP(GENMASK(23, 16), \
150 #define MHI_TRE_EV_DWORD0(code, len) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \
151 FIELD_PREP(GENMASK(15, 0), len))
152 #define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
[all …]
/linux/drivers/media/platform/allegro-dvt/
H A Dallegro-mail.c98 dst[i++] = FIELD_PREP(GENMASK(31, 16), param->height) | in allegro_encode_config_blob()
99 FIELD_PREP(GENMASK(15, 0), param->width); in allegro_encode_config_blob()
108 dst[i++] = FIELD_PREP(GENMASK(31, 24), codec) | in allegro_encode_config_blob()
109 FIELD_PREP(GENMASK(23, 8), param->constraint_set_flags) | in allegro_encode_config_blob()
110 FIELD_PREP(GENMASK(7, 0), param->profile); in allegro_encode_config_blob()
111 dst[i++] = FIELD_PREP(GENMASK(31, 16), param->tier) | in allegro_encode_config_blob()
112 FIELD_PREP(GENMASK(15, 0), param->level); in allegro_encode_config_blob()
116 val |= FIELD_PREP(GENMASK(7, 4), param->log2_max_frame_num); in allegro_encode_config_blob()
118 val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc - 1); in allegro_encode_config_blob()
120 val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc); in allegro_encode_config_blob()
[all …]
/linux/sound/soc/fsl/
H A Dlpc3xxx-i2s.h43 #define LPC3XXX_I2S_WW8 FIELD_PREP(0x3, 0) /* Word width is 8bit */
44 #define LPC3XXX_I2S_WW16 FIELD_PREP(0x3, 1) /* Word width is 16bit */
45 #define LPC3XXX_I2S_WW32 FIELD_PREP(0x3, 3) /* Word width is 32bit */
50 #define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */
65 #define LPC3XXX_I2S_DMA0_RX_DEPTH(s) FIELD_PREP(0xF00, s) /* Set the DMA1 RX Request level */
66 #define LPC3XXX_I2S_DMA0_TX_DEPTH(s) FIELD_PREP(0xF0000, s) /* Set the DMA1 TX Request level */
71 #define LPC3XXX_I2S_DMA1_RX_DEPTH(s) FIELD_PREP(0x700, s) /* Set the DMA1 RX Request level */
72 #define LPC3XXX_I2S_DMA1_TX_DEPTH(s) FIELD_PREP(0x70000, s) /* Set the DMA1 TX Request level */
77 #define LPC3XXX_I2S_IRQ_RX_DEPTH(s) FIELD_PREP(0xFF00, s) /* valid values ar 0 to 7 */
78 #define LPC3XXX_I2S_IRQ_TX_DEPTH(s) FIELD_PREP(0xFF0000, s) /* valid values ar 0 to 7 */
/linux/drivers/fpga/
H A Ddfl-n3000-nios.c104 (FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \
106 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \
108 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK, \
110 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK, \
112 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK, \
114 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK, \
116 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK, \
118 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK, \
122 (FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \
124 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \
[all …]
/linux/drivers/net/phy/qcom/
H A Dqcom.h111 #define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
112 #define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
113 #define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
114 #define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
115 #define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
116 #define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
117 #define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
118 #define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
120 #define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
121 #define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
[all …]
/linux/drivers/irqchip/
H A Dirq-gic-v5-irs.c102 cfgr = FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, in gicv5_irs_init_ist_linear()
104 FIELD_PREP(GICV5_IRS_IST_CFGR_ISTSZ, istsz) | in gicv5_irs_init_ist_linear()
105 FIELD_PREP(GICV5_IRS_IST_CFGR_L2SZ, in gicv5_irs_init_ist_linear()
107 FIELD_PREP(GICV5_IRS_IST_CFGR_LPI_ID_BITS, lpi_id_bits); in gicv5_irs_init_ist_linear()
113 FIELD_PREP(GICV5_IRS_IST_BASER_VALID, 0x1); in gicv5_irs_init_ist_linear()
152 cfgr = FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, in gicv5_irs_init_ist_two_level()
154 FIELD_PREP(GICV5_IRS_IST_CFGR_ISTSZ, istsz) | in gicv5_irs_init_ist_two_level()
155 FIELD_PREP(GICV5_IRS_IST_CFGR_L2SZ, l2sz) | in gicv5_irs_init_ist_two_level()
156 FIELD_PREP(GICV5_IRS_IST_CFGR_LPI_ID_BITS, lpi_id_bits); in gicv5_irs_init_ist_two_level()
170 FIELD_PREP(GICV5_IRS_IST_BASER_VALID, 0x1); in gicv5_irs_init_ist_two_level()
[all …]
/linux/include/linux/mfd/
H A Dti_am335x_tscadc.h55 #define STEPCONFIG_MODE(val) FIELD_PREP(GENMASK(1, 0), (val))
58 #define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val))
66 #define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val))
68 #define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
70 #define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
74 #define STEPCONFIG_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))
78 #define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
81 #define STEPDELAY_SAMPLE(val) FIELD_PREP(GENMASK(31, 24), (val))
86 #define STEPCHARGE_RFP(val) FIELD_PREP(GENMASK(14, 12), (val))
88 #define STEPCHARGE_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8173.c164 FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) | in mtk_hdmi_pll_set_rate()
165 FIELD_PREP(RG_HDMITX_PLL_IR, 0x1)); in mtk_hdmi_pll_set_rate()
169 FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) | in mtk_hdmi_pll_set_rate()
170 FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19)); in mtk_hdmi_pll_set_rate()
175 FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) | in mtk_hdmi_pll_set_rate()
176 FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) | in mtk_hdmi_pll_set_rate()
177 FIELD_PREP(RG_HDMITX_PLL_BR, 0x1)); in mtk_hdmi_pll_set_rate()
192 FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) | in mtk_hdmi_pll_set_rate()
193 FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) | in mtk_hdmi_pll_set_rate()
194 FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) | in mtk_hdmi_pll_set_rate()
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi_ddc_v2.c51 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL)); in mtk_ddc_check_and_rise_low_bus()
87 FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT)); in mtk_ddcm_write_hdmi()
96 FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) | in mtk_ddcm_write_hdmi()
97 FIELD_PREP(SI2C_WDATA, wr_data[i]) | in mtk_ddcm_write_hdmi()
102 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) | in mtk_ddcm_write_hdmi()
103 FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data == NULL ? 0 : data_cnt) | in mtk_ddcm_write_hdmi()
104 FIELD_PREP(DDC_CTRL_OFFSET, offset_id) | in mtk_ddcm_write_hdmi()
105 FIELD_PREP(DDC_CTRL_ADDR, addr_id)); in mtk_ddcm_write_hdmi()
115 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER)); in mtk_ddcm_write_hdmi()
141 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO)); in mtk_ddcm_read_hdmi()
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