1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (c) 2021 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5
6 #include "clk-fhctl.h"
7 #include "clk-gate.h"
8 #include "clk-mtk.h"
9 #include "clk-pll.h"
10 #include "clk-pllfh.h"
11
12 #include <dt-bindings/clock/mt8195-clk.h>
13 #include <linux/platform_device.h>
14
15 static const struct mtk_gate_regs apmixed_cg_regs = {
16 .set_ofs = 0x8,
17 .clr_ofs = 0x8,
18 .sta_ofs = 0x8,
19 };
20
21 #define GATE_APMIXED(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
23
24 static const struct mtk_gate apmixed_clks[] = {
25 GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
26 };
27
28 #define MT8195_PLL_FMAX (3800UL * MHZ)
29 #define MT8195_PLL_FMIN (1500UL * MHZ)
30 #define MT8195_INTEGER_BITS 8
31
32 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
33 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
34 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
35 _pcw_reg, _pcw_shift, _pcw_chg_reg, \
36 _en_reg, _pll_en_bit) { \
37 .id = _id, \
38 .name = _name, \
39 .reg = _reg, \
40 .pwr_reg = _pwr_reg, \
41 .en_mask = _en_mask, \
42 .flags = _flags, \
43 .rst_bar_mask = _rst_bar_mask, \
44 .fmax = MT8195_PLL_FMAX, \
45 .fmin = MT8195_PLL_FMIN, \
46 .pcwbits = _pcwbits, \
47 .pcwibits = MT8195_INTEGER_BITS, \
48 .pd_reg = _pd_reg, \
49 .pd_shift = _pd_shift, \
50 .tuner_reg = _tuner_reg, \
51 .tuner_en_reg = _tuner_en_reg, \
52 .tuner_en_bit = _tuner_en_bit, \
53 .pcw_reg = _pcw_reg, \
54 .pcw_shift = _pcw_shift, \
55 .pcw_chg_reg = _pcw_chg_reg, \
56 .en_reg = _en_reg, \
57 .pll_en_bit = _pll_en_bit, \
58 }
59
60 static const struct mtk_pll_data plls[] = {
61 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
62 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
63 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
64 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
65 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
66 0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
67 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
68 0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
69 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
70 0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
71 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
72 0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
73 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
74 HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
75 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
76 HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
77 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
78 0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
79 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
80 0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
81 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
82 HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
83 PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
84 0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
85 PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
86 0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
87 PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
88 0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
89 PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
90 0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
91 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
92 0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
93 PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
94 0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
95 PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
96 0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
97 PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
98 0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
99 PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
100 0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
101 PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
102 0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
103 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
104 0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
105 PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
106 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
107 };
108
109 enum fh_pll_id {
110 FH_ARMPLL_LL,
111 FH_ARMPLL_BL,
112 FH_MEMPLL,
113 FH_ADSPPLL,
114 FH_NNAPLL,
115 FH_CCIPLL,
116 FH_MFGPLL,
117 FH_TVDPLL2,
118 FH_MPLL,
119 FH_MMPLL,
120 FH_MAINPLL,
121 FH_MSDCPLL,
122 FH_IMGPLL,
123 FH_VDECPLL,
124 FH_TVDPLL1,
125 FH_NR_FH,
126 };
127
128 #define FH(_pllid, _fhid, _offset) { \
129 .data = { \
130 .pll_id = _pllid, \
131 .fh_id = _fhid, \
132 .fh_ver = FHCTL_PLLFH_V2, \
133 .fhx_offset = _offset, \
134 .dds_mask = GENMASK(21, 0), \
135 .slope0_value = 0x6003c97, \
136 .slope1_value = 0x6003c97, \
137 .sfstrx_en = BIT(2), \
138 .frddsx_en = BIT(1), \
139 .fhctlx_en = BIT(0), \
140 .tgl_org = BIT(31), \
141 .dvfs_tri = BIT(31), \
142 .pcwchg = BIT(31), \
143 .dt_val = 0x0, \
144 .df_val = 0x9, \
145 .updnlmt_shft = 16, \
146 .msk_frddsx_dys = GENMASK(23, 20), \
147 .msk_frddsx_dts = GENMASK(19, 16), \
148 }, \
149 }
150
151 static struct mtk_pllfh_data pllfhs[] = {
152 FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
153 FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
154 FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
155 FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
156 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
157 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
158 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
159 FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
160 FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
161 FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
162 };
163
164 static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
165 { .compatible = "mediatek,mt8195-apmixedsys", },
166 {}
167 };
168 MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed);
169
clk_mt8195_apmixed_probe(struct platform_device * pdev)170 static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
171 {
172 struct clk_hw_onecell_data *clk_data;
173 struct device_node *node = pdev->dev.of_node;
174 const u8 *fhctl_node = "mediatek,mt8195-fhctl";
175 int r;
176
177 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
178 if (!clk_data)
179 return -ENOMEM;
180
181 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
182
183 r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
184 pllfhs, ARRAY_SIZE(pllfhs), clk_data);
185 if (r)
186 goto free_apmixed_data;
187
188 r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
189 ARRAY_SIZE(apmixed_clks), clk_data);
190 if (r)
191 goto unregister_plls;
192
193 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
194 if (r)
195 goto unregister_gates;
196
197 platform_set_drvdata(pdev, clk_data);
198
199 return r;
200
201 unregister_gates:
202 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
203 unregister_plls:
204 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
205 ARRAY_SIZE(pllfhs), clk_data);
206 free_apmixed_data:
207 mtk_free_clk_data(clk_data);
208 return r;
209 }
210
clk_mt8195_apmixed_remove(struct platform_device * pdev)211 static void clk_mt8195_apmixed_remove(struct platform_device *pdev)
212 {
213 struct device_node *node = pdev->dev.of_node;
214 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
215
216 of_clk_del_provider(node);
217 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
218 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
219 ARRAY_SIZE(pllfhs), clk_data);
220 mtk_free_clk_data(clk_data);
221 }
222
223 static struct platform_driver clk_mt8195_apmixed_drv = {
224 .probe = clk_mt8195_apmixed_probe,
225 .remove = clk_mt8195_apmixed_remove,
226 .driver = {
227 .name = "clk-mt8195-apmixed",
228 .of_match_table = of_match_clk_mt8195_apmixed,
229 },
230 };
231 module_platform_driver(clk_mt8195_apmixed_drv);
232
233 MODULE_DESCRIPTION("MediaTek MT8195 apmixedsys clocks driver");
234 MODULE_LICENSE("GPL");
235