xref: /linux/drivers/gpu/drm/amd/include/vangogh_ip_offset.h (revision b7e1e969c887c897947fdc3754fe9b0c24acb155)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __VANGOGH_IP_OFFSET_H__
25 #define __VANGOGH_IP_OFFSET_H__
26 
27 #define MAX_INSTANCE                                        8
28 #define MAX_SEGMENT                                         6
29 
30 
31 struct IP_BASE_INSTANCE {
32     unsigned int segment[MAX_SEGMENT];
33 };
34 
35 struct IP_BASE {
36     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
37 } __maybe_unused;
38 
39 
40 static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
41                                         { { 0, 0, 0, 0, 0, 0 } },
42                                         { { 0, 0, 0, 0, 0, 0 } },
43                                         { { 0, 0, 0, 0, 0, 0 } },
44                                         { { 0, 0, 0, 0, 0, 0 } },
45                                         { { 0, 0, 0, 0, 0, 0 } },
46                                         { { 0, 0, 0, 0, 0, 0 } },
47                                         { { 0, 0, 0, 0, 0, 0 } } } };
48 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
49                                         { { 0, 0, 0, 0, 0, 0 } },
50                                         { { 0, 0, 0, 0, 0, 0 } },
51                                         { { 0, 0, 0, 0, 0, 0 } },
52                                         { { 0, 0, 0, 0, 0, 0 } },
53                                         { { 0, 0, 0, 0, 0, 0 } },
54                                         { { 0, 0, 0, 0, 0, 0 } },
55                                         { { 0, 0, 0, 0, 0, 0 } } } };
56 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
57                                         { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
58                                         { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
59                                         { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
60                                         { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
61                                         { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
62                                         { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
63                                         { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
64 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
65                                         { { 0, 0, 0, 0, 0, 0 } },
66                                         { { 0, 0, 0, 0, 0, 0 } },
67                                         { { 0, 0, 0, 0, 0, 0 } },
68                                         { { 0, 0, 0, 0, 0, 0 } },
69                                         { { 0, 0, 0, 0, 0, 0 } },
70                                         { { 0, 0, 0, 0, 0, 0 } },
71                                         { { 0, 0, 0, 0, 0, 0 } } } };
72 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
73                                         { { 0, 0, 0, 0, 0, 0 } },
74                                         { { 0, 0, 0, 0, 0, 0 } },
75                                         { { 0, 0, 0, 0, 0, 0 } },
76                                         { { 0, 0, 0, 0, 0, 0 } },
77                                         { { 0, 0, 0, 0, 0, 0 } },
78                                         { { 0, 0, 0, 0, 0, 0 } },
79                                         { { 0, 0, 0, 0, 0, 0 } } } };
80 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
81                                         { { 0, 0, 0, 0, 0, 0 } },
82                                         { { 0, 0, 0, 0, 0, 0 } },
83                                         { { 0, 0, 0, 0, 0, 0 } },
84                                         { { 0, 0, 0, 0, 0, 0 } },
85                                         { { 0, 0, 0, 0, 0, 0 } },
86                                         { { 0, 0, 0, 0, 0, 0 } },
87                                         { { 0, 0, 0, 0, 0, 0 } } } };
88 static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
89                                         { { 0, 0, 0, 0, 0, 0 } },
90                                         { { 0, 0, 0, 0, 0, 0 } },
91                                         { { 0, 0, 0, 0, 0, 0 } },
92                                         { { 0, 0, 0, 0, 0, 0 } },
93                                         { { 0, 0, 0, 0, 0, 0 } },
94                                         { { 0, 0, 0, 0, 0, 0 } },
95                                         { { 0, 0, 0, 0, 0, 0 } } } };
96 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
97                                         { { 0, 0, 0, 0, 0, 0 } },
98                                         { { 0, 0, 0, 0, 0, 0 } },
99                                         { { 0, 0, 0, 0, 0, 0 } },
100                                         { { 0, 0, 0, 0, 0, 0 } },
101                                         { { 0, 0, 0, 0, 0, 0 } },
102                                         { { 0, 0, 0, 0, 0, 0 } },
103                                         { { 0, 0, 0, 0, 0, 0 } } } };
104 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
105                                         { { 0, 0, 0, 0, 0, 0 } },
106                                         { { 0, 0, 0, 0, 0, 0 } },
107                                         { { 0, 0, 0, 0, 0, 0 } },
108                                         { { 0, 0, 0, 0, 0, 0 } },
109                                         { { 0, 0, 0, 0, 0, 0 } },
110                                         { { 0, 0, 0, 0, 0, 0 } },
111                                         { { 0, 0, 0, 0, 0, 0 } } } };
112 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
113                                         { { 0, 0, 0, 0, 0, 0 } },
114                                         { { 0, 0, 0, 0, 0, 0 } },
115                                         { { 0, 0, 0, 0, 0, 0 } },
116                                         { { 0, 0, 0, 0, 0, 0 } },
117                                         { { 0, 0, 0, 0, 0, 0 } },
118                                         { { 0, 0, 0, 0, 0, 0 } },
119                                         { { 0, 0, 0, 0, 0, 0 } } } };
120 static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
121                                         { { 0, 0, 0, 0, 0, 0 } },
122                                         { { 0, 0, 0, 0, 0, 0 } },
123                                         { { 0, 0, 0, 0, 0, 0 } },
124                                         { { 0, 0, 0, 0, 0, 0 } },
125                                         { { 0, 0, 0, 0, 0, 0 } },
126                                         { { 0, 0, 0, 0, 0, 0 } },
127                                         { { 0, 0, 0, 0, 0, 0 } } } };
128 static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
129                                         { { 0, 0, 0, 0, 0, 0 } },
130                                         { { 0, 0, 0, 0, 0, 0 } },
131                                         { { 0, 0, 0, 0, 0, 0 } },
132                                         { { 0, 0, 0, 0, 0, 0 } },
133                                         { { 0, 0, 0, 0, 0, 0 } },
134                                         { { 0, 0, 0, 0, 0, 0 } },
135                                         { { 0, 0, 0, 0, 0, 0 } } } };
136 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
137                                         { { 0, 0, 0, 0, 0, 0 } },
138                                         { { 0, 0, 0, 0, 0, 0 } },
139                                         { { 0, 0, 0, 0, 0, 0 } },
140                                         { { 0, 0, 0, 0, 0, 0 } },
141                                         { { 0, 0, 0, 0, 0, 0 } },
142                                         { { 0, 0, 0, 0, 0, 0 } },
143                                         { { 0, 0, 0, 0, 0, 0 } } } };
144 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
145                                         { { 0, 0, 0, 0, 0, 0 } },
146                                         { { 0, 0, 0, 0, 0, 0 } },
147                                         { { 0, 0, 0, 0, 0, 0 } },
148                                         { { 0, 0, 0, 0, 0, 0 } },
149                                         { { 0, 0, 0, 0, 0, 0 } },
150                                         { { 0, 0, 0, 0, 0, 0 } },
151                                         { { 0, 0, 0, 0, 0, 0 } } } };
152 static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
153                                         { { 0, 0, 0, 0, 0, 0 } },
154                                         { { 0, 0, 0, 0, 0, 0 } },
155                                         { { 0, 0, 0, 0, 0, 0 } },
156                                         { { 0, 0, 0, 0, 0, 0 } },
157                                         { { 0, 0, 0, 0, 0, 0 } },
158                                         { { 0, 0, 0, 0, 0, 0 } },
159                                         { { 0, 0, 0, 0, 0, 0 } } } };
160 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
161                                         { { 0, 0, 0, 0, 0, 0 } },
162                                         { { 0, 0, 0, 0, 0, 0 } },
163                                         { { 0, 0, 0, 0, 0, 0 } },
164                                         { { 0, 0, 0, 0, 0, 0 } },
165                                         { { 0, 0, 0, 0, 0, 0 } },
166                                         { { 0, 0, 0, 0, 0, 0 } },
167                                         { { 0, 0, 0, 0, 0, 0 } } } };
168 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
169                                         { { 0, 0, 0, 0, 0, 0 } },
170                                         { { 0, 0, 0, 0, 0, 0 } },
171                                         { { 0, 0, 0, 0, 0, 0 } },
172                                         { { 0, 0, 0, 0, 0, 0 } },
173                                         { { 0, 0, 0, 0, 0, 0 } },
174                                         { { 0, 0, 0, 0, 0, 0 } },
175                                         { { 0, 0, 0, 0, 0, 0 } } } };
176 static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
177                                         { { 0, 0, 0, 0, 0, 0 } },
178                                         { { 0, 0, 0, 0, 0, 0 } },
179                                         { { 0, 0, 0, 0, 0, 0 } },
180                                         { { 0, 0, 0, 0, 0, 0 } },
181                                         { { 0, 0, 0, 0, 0, 0 } },
182                                         { { 0, 0, 0, 0, 0, 0 } },
183                                         { { 0, 0, 0, 0, 0, 0 } } } };
184 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
185                                         { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
186                                         { { 0, 0, 0, 0, 0, 0 } },
187                                         { { 0, 0, 0, 0, 0, 0 } },
188                                         { { 0, 0, 0, 0, 0, 0 } },
189                                         { { 0, 0, 0, 0, 0, 0 } },
190                                         { { 0, 0, 0, 0, 0, 0 } },
191                                         { { 0, 0, 0, 0, 0, 0 } } } };
192 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
193                                         { { 0, 0, 0, 0, 0, 0 } },
194                                         { { 0, 0, 0, 0, 0, 0 } },
195                                         { { 0, 0, 0, 0, 0, 0 } },
196                                         { { 0, 0, 0, 0, 0, 0 } },
197                                         { { 0, 0, 0, 0, 0, 0 } },
198                                         { { 0, 0, 0, 0, 0, 0 } },
199                                         { { 0, 0, 0, 0, 0, 0 } } } };
200 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
201                                         { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
202                                         { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
203                                         { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
204                                         { { 0, 0, 0, 0, 0, 0 } },
205                                         { { 0, 0, 0, 0, 0, 0 } },
206                                         { { 0, 0, 0, 0, 0, 0 } },
207                                         { { 0, 0, 0, 0, 0, 0 } } } };
208 static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
209                                         { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
210                                         { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
211                                         { { 0, 0, 0, 0, 0, 0 } },
212                                         { { 0, 0, 0, 0, 0, 0 } },
213                                         { { 0, 0, 0, 0, 0, 0 } },
214                                         { { 0, 0, 0, 0, 0, 0 } },
215                                         { { 0, 0, 0, 0, 0, 0 } } } };
216 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
217                                         { { 0, 0, 0, 0, 0, 0 } },
218                                         { { 0, 0, 0, 0, 0, 0 } },
219                                         { { 0, 0, 0, 0, 0, 0 } },
220                                         { { 0, 0, 0, 0, 0, 0 } },
221                                         { { 0, 0, 0, 0, 0, 0 } },
222                                         { { 0, 0, 0, 0, 0, 0 } },
223                                         { { 0, 0, 0, 0, 0, 0 } } } };
224 
225 
226 #define ACP_BASE__INST0_SEG0                       0x02403800
227 #define ACP_BASE__INST0_SEG1                       0x00480000
228 #define ACP_BASE__INST0_SEG2                       0
229 #define ACP_BASE__INST0_SEG3                       0
230 #define ACP_BASE__INST0_SEG4                       0
231 #define ACP_BASE__INST0_SEG5                       0
232 
233 #define ACP_BASE__INST1_SEG0                       0
234 #define ACP_BASE__INST1_SEG1                       0
235 #define ACP_BASE__INST1_SEG2                       0
236 #define ACP_BASE__INST1_SEG3                       0
237 #define ACP_BASE__INST1_SEG4                       0
238 #define ACP_BASE__INST1_SEG5                       0
239 
240 #define ACP_BASE__INST2_SEG0                       0
241 #define ACP_BASE__INST2_SEG1                       0
242 #define ACP_BASE__INST2_SEG2                       0
243 #define ACP_BASE__INST2_SEG3                       0
244 #define ACP_BASE__INST2_SEG4                       0
245 #define ACP_BASE__INST2_SEG5                       0
246 
247 #define ACP_BASE__INST3_SEG0                       0
248 #define ACP_BASE__INST3_SEG1                       0
249 #define ACP_BASE__INST3_SEG2                       0
250 #define ACP_BASE__INST3_SEG3                       0
251 #define ACP_BASE__INST3_SEG4                       0
252 #define ACP_BASE__INST3_SEG5                       0
253 
254 #define ACP_BASE__INST4_SEG0                       0
255 #define ACP_BASE__INST4_SEG1                       0
256 #define ACP_BASE__INST4_SEG2                       0
257 #define ACP_BASE__INST4_SEG3                       0
258 #define ACP_BASE__INST4_SEG4                       0
259 #define ACP_BASE__INST4_SEG5                       0
260 
261 #define ACP_BASE__INST5_SEG0                       0
262 #define ACP_BASE__INST5_SEG1                       0
263 #define ACP_BASE__INST5_SEG2                       0
264 #define ACP_BASE__INST5_SEG3                       0
265 #define ACP_BASE__INST5_SEG4                       0
266 #define ACP_BASE__INST5_SEG5                       0
267 
268 #define ACP_BASE__INST6_SEG0                       0
269 #define ACP_BASE__INST6_SEG1                       0
270 #define ACP_BASE__INST6_SEG2                       0
271 #define ACP_BASE__INST6_SEG3                       0
272 #define ACP_BASE__INST6_SEG4                       0
273 #define ACP_BASE__INST6_SEG5                       0
274 
275 #define ACP_BASE__INST7_SEG0                       0
276 #define ACP_BASE__INST7_SEG1                       0
277 #define ACP_BASE__INST7_SEG2                       0
278 #define ACP_BASE__INST7_SEG3                       0
279 #define ACP_BASE__INST7_SEG4                       0
280 #define ACP_BASE__INST7_SEG5                       0
281 
282 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
283 #define ATHUB_BASE__INST0_SEG1                     0x00013300
284 #define ATHUB_BASE__INST0_SEG2                     0x02408C00
285 #define ATHUB_BASE__INST0_SEG3                     0
286 #define ATHUB_BASE__INST0_SEG4                     0
287 #define ATHUB_BASE__INST0_SEG5                     0
288 
289 #define ATHUB_BASE__INST1_SEG0                     0
290 #define ATHUB_BASE__INST1_SEG1                     0
291 #define ATHUB_BASE__INST1_SEG2                     0
292 #define ATHUB_BASE__INST1_SEG3                     0
293 #define ATHUB_BASE__INST1_SEG4                     0
294 #define ATHUB_BASE__INST1_SEG5                     0
295 
296 #define ATHUB_BASE__INST2_SEG0                     0
297 #define ATHUB_BASE__INST2_SEG1                     0
298 #define ATHUB_BASE__INST2_SEG2                     0
299 #define ATHUB_BASE__INST2_SEG3                     0
300 #define ATHUB_BASE__INST2_SEG4                     0
301 #define ATHUB_BASE__INST2_SEG5                     0
302 
303 #define ATHUB_BASE__INST3_SEG0                     0
304 #define ATHUB_BASE__INST3_SEG1                     0
305 #define ATHUB_BASE__INST3_SEG2                     0
306 #define ATHUB_BASE__INST3_SEG3                     0
307 #define ATHUB_BASE__INST3_SEG4                     0
308 #define ATHUB_BASE__INST3_SEG5                     0
309 
310 #define ATHUB_BASE__INST4_SEG0                     0
311 #define ATHUB_BASE__INST4_SEG1                     0
312 #define ATHUB_BASE__INST4_SEG2                     0
313 #define ATHUB_BASE__INST4_SEG3                     0
314 #define ATHUB_BASE__INST4_SEG4                     0
315 #define ATHUB_BASE__INST4_SEG5                     0
316 
317 #define ATHUB_BASE__INST5_SEG0                     0
318 #define ATHUB_BASE__INST5_SEG1                     0
319 #define ATHUB_BASE__INST5_SEG2                     0
320 #define ATHUB_BASE__INST5_SEG3                     0
321 #define ATHUB_BASE__INST5_SEG4                     0
322 #define ATHUB_BASE__INST5_SEG5                     0
323 
324 #define ATHUB_BASE__INST6_SEG0                     0
325 #define ATHUB_BASE__INST6_SEG1                     0
326 #define ATHUB_BASE__INST6_SEG2                     0
327 #define ATHUB_BASE__INST6_SEG3                     0
328 #define ATHUB_BASE__INST6_SEG4                     0
329 #define ATHUB_BASE__INST6_SEG5                     0
330 
331 #define ATHUB_BASE__INST7_SEG0                     0
332 #define ATHUB_BASE__INST7_SEG1                     0
333 #define ATHUB_BASE__INST7_SEG2                     0
334 #define ATHUB_BASE__INST7_SEG3                     0
335 #define ATHUB_BASE__INST7_SEG4                     0
336 #define ATHUB_BASE__INST7_SEG5                     0
337 
338 #define CLK_BASE__INST0_SEG0                       0x00016C00
339 #define CLK_BASE__INST0_SEG1                       0x02401800
340 #define CLK_BASE__INST0_SEG2                       0
341 #define CLK_BASE__INST0_SEG3                       0
342 #define CLK_BASE__INST0_SEG4                       0
343 #define CLK_BASE__INST0_SEG5                       0
344 
345 #define CLK_BASE__INST1_SEG0                       0x00016E00
346 #define CLK_BASE__INST1_SEG1                       0x02401C00
347 #define CLK_BASE__INST1_SEG2                       0
348 #define CLK_BASE__INST1_SEG3                       0
349 #define CLK_BASE__INST1_SEG4                       0
350 #define CLK_BASE__INST1_SEG5                       0
351 
352 #define CLK_BASE__INST2_SEG0                       0x00017000
353 #define CLK_BASE__INST2_SEG1                       0x02402000
354 #define CLK_BASE__INST2_SEG2                       0
355 #define CLK_BASE__INST2_SEG3                       0
356 #define CLK_BASE__INST2_SEG4                       0
357 #define CLK_BASE__INST2_SEG5                       0
358 
359 #define CLK_BASE__INST3_SEG0                       0x00017200
360 #define CLK_BASE__INST3_SEG1                       0x02402400
361 #define CLK_BASE__INST3_SEG2                       0
362 #define CLK_BASE__INST3_SEG3                       0
363 #define CLK_BASE__INST3_SEG4                       0
364 #define CLK_BASE__INST3_SEG5                       0
365 
366 #define CLK_BASE__INST4_SEG0                       0x0001B000
367 #define CLK_BASE__INST4_SEG1                       0x0242D800
368 #define CLK_BASE__INST4_SEG2                       0
369 #define CLK_BASE__INST4_SEG3                       0
370 #define CLK_BASE__INST4_SEG4                       0
371 #define CLK_BASE__INST4_SEG5                       0
372 
373 #define CLK_BASE__INST5_SEG0                       0x0001B200
374 #define CLK_BASE__INST5_SEG1                       0x0242DC00
375 #define CLK_BASE__INST5_SEG2                       0
376 #define CLK_BASE__INST5_SEG3                       0
377 #define CLK_BASE__INST5_SEG4                       0
378 #define CLK_BASE__INST5_SEG5                       0
379 
380 #define CLK_BASE__INST6_SEG0                       0x0001B400
381 #define CLK_BASE__INST6_SEG1                       0x0242E000
382 #define CLK_BASE__INST6_SEG2                       0
383 #define CLK_BASE__INST6_SEG3                       0
384 #define CLK_BASE__INST6_SEG4                       0
385 #define CLK_BASE__INST6_SEG5                       0
386 
387 #define CLK_BASE__INST7_SEG0                       0x00017E00
388 #define CLK_BASE__INST7_SEG1                       0x0240BC00
389 #define CLK_BASE__INST7_SEG2                       0
390 #define CLK_BASE__INST7_SEG3                       0
391 #define CLK_BASE__INST7_SEG4                       0
392 #define CLK_BASE__INST7_SEG5                       0
393 
394 #define DF_BASE__INST0_SEG0                        0x00007000
395 #define DF_BASE__INST0_SEG1                        0x0240B800
396 #define DF_BASE__INST0_SEG2                        0
397 #define DF_BASE__INST0_SEG3                        0
398 #define DF_BASE__INST0_SEG4                        0
399 #define DF_BASE__INST0_SEG5                        0
400 
401 #define DF_BASE__INST1_SEG0                        0
402 #define DF_BASE__INST1_SEG1                        0
403 #define DF_BASE__INST1_SEG2                        0
404 #define DF_BASE__INST1_SEG3                        0
405 #define DF_BASE__INST1_SEG4                        0
406 #define DF_BASE__INST1_SEG5                        0
407 
408 #define DF_BASE__INST2_SEG0                        0
409 #define DF_BASE__INST2_SEG1                        0
410 #define DF_BASE__INST2_SEG2                        0
411 #define DF_BASE__INST2_SEG3                        0
412 #define DF_BASE__INST2_SEG4                        0
413 #define DF_BASE__INST2_SEG5                        0
414 
415 #define DF_BASE__INST3_SEG0                        0
416 #define DF_BASE__INST3_SEG1                        0
417 #define DF_BASE__INST3_SEG2                        0
418 #define DF_BASE__INST3_SEG3                        0
419 #define DF_BASE__INST3_SEG4                        0
420 #define DF_BASE__INST3_SEG5                        0
421 
422 #define DF_BASE__INST4_SEG0                        0
423 #define DF_BASE__INST4_SEG1                        0
424 #define DF_BASE__INST4_SEG2                        0
425 #define DF_BASE__INST4_SEG3                        0
426 #define DF_BASE__INST4_SEG4                        0
427 #define DF_BASE__INST4_SEG5                        0
428 
429 #define DF_BASE__INST5_SEG0                        0
430 #define DF_BASE__INST5_SEG1                        0
431 #define DF_BASE__INST5_SEG2                        0
432 #define DF_BASE__INST5_SEG3                        0
433 #define DF_BASE__INST5_SEG4                        0
434 #define DF_BASE__INST5_SEG5                        0
435 
436 #define DF_BASE__INST6_SEG0                        0
437 #define DF_BASE__INST6_SEG1                        0
438 #define DF_BASE__INST6_SEG2                        0
439 #define DF_BASE__INST6_SEG3                        0
440 #define DF_BASE__INST6_SEG4                        0
441 #define DF_BASE__INST6_SEG5                        0
442 
443 #define DF_BASE__INST7_SEG0                        0
444 #define DF_BASE__INST7_SEG1                        0
445 #define DF_BASE__INST7_SEG2                        0
446 #define DF_BASE__INST7_SEG3                        0
447 #define DF_BASE__INST7_SEG4                        0
448 #define DF_BASE__INST7_SEG5                        0
449 
450 #define DCN_BASE__INST0_SEG0                       0x00000012
451 #define DCN_BASE__INST0_SEG1                       0x000000C0
452 #define DCN_BASE__INST0_SEG2                       0x000034C0
453 #define DCN_BASE__INST0_SEG3                       0x00009000
454 #define DCN_BASE__INST0_SEG4                       0x02403C00
455 #define DCN_BASE__INST0_SEG5                       0
456 
457 #define DCN_BASE__INST1_SEG0                       0
458 #define DCN_BASE__INST1_SEG1                       0
459 #define DCN_BASE__INST1_SEG2                       0
460 #define DCN_BASE__INST1_SEG3                       0
461 #define DCN_BASE__INST1_SEG4                       0
462 #define DCN_BASE__INST1_SEG5                       0
463 
464 #define DCN_BASE__INST2_SEG0                       0
465 #define DCN_BASE__INST2_SEG1                       0
466 #define DCN_BASE__INST2_SEG2                       0
467 #define DCN_BASE__INST2_SEG3                       0
468 #define DCN_BASE__INST2_SEG4                       0
469 #define DCN_BASE__INST2_SEG5                       0
470 
471 #define DCN_BASE__INST3_SEG0                       0
472 #define DCN_BASE__INST3_SEG1                       0
473 #define DCN_BASE__INST3_SEG2                       0
474 #define DCN_BASE__INST3_SEG3                       0
475 #define DCN_BASE__INST3_SEG4                       0
476 #define DCN_BASE__INST3_SEG5                       0
477 
478 #define DCN_BASE__INST4_SEG0                       0
479 #define DCN_BASE__INST4_SEG1                       0
480 #define DCN_BASE__INST4_SEG2                       0
481 #define DCN_BASE__INST4_SEG3                       0
482 #define DCN_BASE__INST4_SEG4                       0
483 #define DCN_BASE__INST4_SEG5                       0
484 
485 #define DCN_BASE__INST5_SEG0                       0
486 #define DCN_BASE__INST5_SEG1                       0
487 #define DCN_BASE__INST5_SEG2                       0
488 #define DCN_BASE__INST5_SEG3                       0
489 #define DCN_BASE__INST5_SEG4                       0
490 #define DCN_BASE__INST5_SEG5                       0
491 
492 #define DCN_BASE__INST6_SEG0                       0
493 #define DCN_BASE__INST6_SEG1                       0
494 #define DCN_BASE__INST6_SEG2                       0
495 #define DCN_BASE__INST6_SEG3                       0
496 #define DCN_BASE__INST6_SEG4                       0
497 #define DCN_BASE__INST6_SEG5                       0
498 
499 #define DCN_BASE__INST7_SEG0                       0
500 #define DCN_BASE__INST7_SEG1                       0
501 #define DCN_BASE__INST7_SEG2                       0
502 #define DCN_BASE__INST7_SEG3                       0
503 #define DCN_BASE__INST7_SEG4                       0
504 #define DCN_BASE__INST7_SEG5                       0
505 
506 #define DPCS_BASE__INST0_SEG0                      0x00000012
507 #define DPCS_BASE__INST0_SEG1                      0x000000C0
508 #define DPCS_BASE__INST0_SEG2                      0x000034C0
509 #define DPCS_BASE__INST0_SEG3                      0x00009000
510 #define DPCS_BASE__INST0_SEG4                      0x02403C00
511 #define DPCS_BASE__INST0_SEG5                      0
512 
513 #define DPCS_BASE__INST1_SEG0                      0
514 #define DPCS_BASE__INST1_SEG1                      0
515 #define DPCS_BASE__INST1_SEG2                      0
516 #define DPCS_BASE__INST1_SEG3                      0
517 #define DPCS_BASE__INST1_SEG4                      0
518 #define DPCS_BASE__INST1_SEG5                      0
519 
520 #define DPCS_BASE__INST2_SEG0                      0
521 #define DPCS_BASE__INST2_SEG1                      0
522 #define DPCS_BASE__INST2_SEG2                      0
523 #define DPCS_BASE__INST2_SEG3                      0
524 #define DPCS_BASE__INST2_SEG4                      0
525 #define DPCS_BASE__INST2_SEG5                      0
526 
527 #define DPCS_BASE__INST3_SEG0                      0
528 #define DPCS_BASE__INST3_SEG1                      0
529 #define DPCS_BASE__INST3_SEG2                      0
530 #define DPCS_BASE__INST3_SEG3                      0
531 #define DPCS_BASE__INST3_SEG4                      0
532 #define DPCS_BASE__INST3_SEG5                      0
533 
534 #define DPCS_BASE__INST4_SEG0                      0
535 #define DPCS_BASE__INST4_SEG1                      0
536 #define DPCS_BASE__INST4_SEG2                      0
537 #define DPCS_BASE__INST4_SEG3                      0
538 #define DPCS_BASE__INST4_SEG4                      0
539 #define DPCS_BASE__INST4_SEG5                      0
540 
541 #define DPCS_BASE__INST5_SEG0                      0
542 #define DPCS_BASE__INST5_SEG1                      0
543 #define DPCS_BASE__INST5_SEG2                      0
544 #define DPCS_BASE__INST5_SEG3                      0
545 #define DPCS_BASE__INST5_SEG4                      0
546 #define DPCS_BASE__INST5_SEG5                      0
547 
548 #define DPCS_BASE__INST6_SEG0                      0
549 #define DPCS_BASE__INST6_SEG1                      0
550 #define DPCS_BASE__INST6_SEG2                      0
551 #define DPCS_BASE__INST6_SEG3                      0
552 #define DPCS_BASE__INST6_SEG4                      0
553 #define DPCS_BASE__INST6_SEG5                      0
554 
555 #define DPCS_BASE__INST7_SEG0                      0
556 #define DPCS_BASE__INST7_SEG1                      0
557 #define DPCS_BASE__INST7_SEG2                      0
558 #define DPCS_BASE__INST7_SEG3                      0
559 #define DPCS_BASE__INST7_SEG4                      0
560 #define DPCS_BASE__INST7_SEG5                      0
561 
562 #define FCH_BASE__INST0_SEG0                       0x0240C000
563 #define FCH_BASE__INST0_SEG1                       0x00B40000
564 #define FCH_BASE__INST0_SEG2                       0x11000000
565 #define FCH_BASE__INST0_SEG3                       0
566 #define FCH_BASE__INST0_SEG4                       0
567 #define FCH_BASE__INST0_SEG5                       0
568 
569 #define FCH_BASE__INST1_SEG0                       0
570 #define FCH_BASE__INST1_SEG1                       0
571 #define FCH_BASE__INST1_SEG2                       0
572 #define FCH_BASE__INST1_SEG3                       0
573 #define FCH_BASE__INST1_SEG4                       0
574 #define FCH_BASE__INST1_SEG5                       0
575 
576 #define FCH_BASE__INST2_SEG0                       0
577 #define FCH_BASE__INST2_SEG1                       0
578 #define FCH_BASE__INST2_SEG2                       0
579 #define FCH_BASE__INST2_SEG3                       0
580 #define FCH_BASE__INST2_SEG4                       0
581 #define FCH_BASE__INST2_SEG5                       0
582 
583 #define FCH_BASE__INST3_SEG0                       0
584 #define FCH_BASE__INST3_SEG1                       0
585 #define FCH_BASE__INST3_SEG2                       0
586 #define FCH_BASE__INST3_SEG3                       0
587 #define FCH_BASE__INST3_SEG4                       0
588 #define FCH_BASE__INST3_SEG5                       0
589 
590 #define FCH_BASE__INST4_SEG0                       0
591 #define FCH_BASE__INST4_SEG1                       0
592 #define FCH_BASE__INST4_SEG2                       0
593 #define FCH_BASE__INST4_SEG3                       0
594 #define FCH_BASE__INST4_SEG4                       0
595 #define FCH_BASE__INST4_SEG5                       0
596 
597 #define FCH_BASE__INST5_SEG0                       0
598 #define FCH_BASE__INST5_SEG1                       0
599 #define FCH_BASE__INST5_SEG2                       0
600 #define FCH_BASE__INST5_SEG3                       0
601 #define FCH_BASE__INST5_SEG4                       0
602 #define FCH_BASE__INST5_SEG5                       0
603 
604 #define FCH_BASE__INST6_SEG0                       0
605 #define FCH_BASE__INST6_SEG1                       0
606 #define FCH_BASE__INST6_SEG2                       0
607 #define FCH_BASE__INST6_SEG3                       0
608 #define FCH_BASE__INST6_SEG4                       0
609 #define FCH_BASE__INST6_SEG5                       0
610 
611 #define FCH_BASE__INST7_SEG0                       0
612 #define FCH_BASE__INST7_SEG1                       0
613 #define FCH_BASE__INST7_SEG2                       0
614 #define FCH_BASE__INST7_SEG3                       0
615 #define FCH_BASE__INST7_SEG4                       0
616 #define FCH_BASE__INST7_SEG5                       0
617 
618 #define FUSE_BASE__INST0_SEG0                      0x00017400
619 #define FUSE_BASE__INST0_SEG1                      0x02401400
620 #define FUSE_BASE__INST0_SEG2                      0
621 #define FUSE_BASE__INST0_SEG3                      0
622 #define FUSE_BASE__INST0_SEG4                      0
623 #define FUSE_BASE__INST0_SEG5                      0
624 
625 #define FUSE_BASE__INST1_SEG0                      0
626 #define FUSE_BASE__INST1_SEG1                      0
627 #define FUSE_BASE__INST1_SEG2                      0
628 #define FUSE_BASE__INST1_SEG3                      0
629 #define FUSE_BASE__INST1_SEG4                      0
630 #define FUSE_BASE__INST1_SEG5                      0
631 
632 #define FUSE_BASE__INST2_SEG0                      0
633 #define FUSE_BASE__INST2_SEG1                      0
634 #define FUSE_BASE__INST2_SEG2                      0
635 #define FUSE_BASE__INST2_SEG3                      0
636 #define FUSE_BASE__INST2_SEG4                      0
637 #define FUSE_BASE__INST2_SEG5                      0
638 
639 #define FUSE_BASE__INST3_SEG0                      0
640 #define FUSE_BASE__INST3_SEG1                      0
641 #define FUSE_BASE__INST3_SEG2                      0
642 #define FUSE_BASE__INST3_SEG3                      0
643 #define FUSE_BASE__INST3_SEG4                      0
644 #define FUSE_BASE__INST3_SEG5                      0
645 
646 #define FUSE_BASE__INST4_SEG0                      0
647 #define FUSE_BASE__INST4_SEG1                      0
648 #define FUSE_BASE__INST4_SEG2                      0
649 #define FUSE_BASE__INST4_SEG3                      0
650 #define FUSE_BASE__INST4_SEG4                      0
651 #define FUSE_BASE__INST4_SEG5                      0
652 
653 #define FUSE_BASE__INST5_SEG0                      0
654 #define FUSE_BASE__INST5_SEG1                      0
655 #define FUSE_BASE__INST5_SEG2                      0
656 #define FUSE_BASE__INST5_SEG3                      0
657 #define FUSE_BASE__INST5_SEG4                      0
658 #define FUSE_BASE__INST5_SEG5                      0
659 
660 #define FUSE_BASE__INST6_SEG0                      0
661 #define FUSE_BASE__INST6_SEG1                      0
662 #define FUSE_BASE__INST6_SEG2                      0
663 #define FUSE_BASE__INST6_SEG3                      0
664 #define FUSE_BASE__INST6_SEG4                      0
665 #define FUSE_BASE__INST6_SEG5                      0
666 
667 #define FUSE_BASE__INST7_SEG0                      0
668 #define FUSE_BASE__INST7_SEG1                      0
669 #define FUSE_BASE__INST7_SEG2                      0
670 #define FUSE_BASE__INST7_SEG3                      0
671 #define FUSE_BASE__INST7_SEG4                      0
672 #define FUSE_BASE__INST7_SEG5                      0
673 
674 #define GC_BASE__INST0_SEG0                        0x00001260
675 #define GC_BASE__INST0_SEG1                        0x0000A000
676 #define GC_BASE__INST0_SEG2                        0x02402C00
677 #define GC_BASE__INST0_SEG3                        0
678 #define GC_BASE__INST0_SEG4                        0
679 #define GC_BASE__INST0_SEG5                        0
680 
681 #define GC_BASE__INST1_SEG0                        0
682 #define GC_BASE__INST1_SEG1                        0
683 #define GC_BASE__INST1_SEG2                        0
684 #define GC_BASE__INST1_SEG3                        0
685 #define GC_BASE__INST1_SEG4                        0
686 #define GC_BASE__INST1_SEG5                        0
687 
688 #define GC_BASE__INST2_SEG0                        0
689 #define GC_BASE__INST2_SEG1                        0
690 #define GC_BASE__INST2_SEG2                        0
691 #define GC_BASE__INST2_SEG3                        0
692 #define GC_BASE__INST2_SEG4                        0
693 #define GC_BASE__INST2_SEG5                        0
694 
695 #define GC_BASE__INST3_SEG0                        0
696 #define GC_BASE__INST3_SEG1                        0
697 #define GC_BASE__INST3_SEG2                        0
698 #define GC_BASE__INST3_SEG3                        0
699 #define GC_BASE__INST3_SEG4                        0
700 #define GC_BASE__INST3_SEG5                        0
701 
702 #define GC_BASE__INST4_SEG0                        0
703 #define GC_BASE__INST4_SEG1                        0
704 #define GC_BASE__INST4_SEG2                        0
705 #define GC_BASE__INST4_SEG3                        0
706 #define GC_BASE__INST4_SEG4                        0
707 #define GC_BASE__INST4_SEG5                        0
708 
709 #define GC_BASE__INST5_SEG0                        0
710 #define GC_BASE__INST5_SEG1                        0
711 #define GC_BASE__INST5_SEG2                        0
712 #define GC_BASE__INST5_SEG3                        0
713 #define GC_BASE__INST5_SEG4                        0
714 #define GC_BASE__INST5_SEG5                        0
715 
716 #define GC_BASE__INST6_SEG0                        0
717 #define GC_BASE__INST6_SEG1                        0
718 #define GC_BASE__INST6_SEG2                        0
719 #define GC_BASE__INST6_SEG3                        0
720 #define GC_BASE__INST6_SEG4                        0
721 #define GC_BASE__INST6_SEG5                        0
722 
723 #define GC_BASE__INST7_SEG0                        0
724 #define GC_BASE__INST7_SEG1                        0
725 #define GC_BASE__INST7_SEG2                        0
726 #define GC_BASE__INST7_SEG3                        0
727 #define GC_BASE__INST7_SEG4                        0
728 #define GC_BASE__INST7_SEG5                        0
729 
730 #define HDP_BASE__INST0_SEG0                       0x00000F20
731 #define HDP_BASE__INST0_SEG1                       0x0240A400
732 #define HDP_BASE__INST0_SEG2                       0
733 #define HDP_BASE__INST0_SEG3                       0
734 #define HDP_BASE__INST0_SEG4                       0
735 #define HDP_BASE__INST0_SEG5                       0
736 
737 #define HDP_BASE__INST1_SEG0                       0
738 #define HDP_BASE__INST1_SEG1                       0
739 #define HDP_BASE__INST1_SEG2                       0
740 #define HDP_BASE__INST1_SEG3                       0
741 #define HDP_BASE__INST1_SEG4                       0
742 #define HDP_BASE__INST1_SEG5                       0
743 
744 #define HDP_BASE__INST2_SEG0                       0
745 #define HDP_BASE__INST2_SEG1                       0
746 #define HDP_BASE__INST2_SEG2                       0
747 #define HDP_BASE__INST2_SEG3                       0
748 #define HDP_BASE__INST2_SEG4                       0
749 #define HDP_BASE__INST2_SEG5                       0
750 
751 #define HDP_BASE__INST3_SEG0                       0
752 #define HDP_BASE__INST3_SEG1                       0
753 #define HDP_BASE__INST3_SEG2                       0
754 #define HDP_BASE__INST3_SEG3                       0
755 #define HDP_BASE__INST3_SEG4                       0
756 #define HDP_BASE__INST3_SEG5                       0
757 
758 #define HDP_BASE__INST4_SEG0                       0
759 #define HDP_BASE__INST4_SEG1                       0
760 #define HDP_BASE__INST4_SEG2                       0
761 #define HDP_BASE__INST4_SEG3                       0
762 #define HDP_BASE__INST4_SEG4                       0
763 #define HDP_BASE__INST4_SEG5                       0
764 
765 #define HDP_BASE__INST5_SEG0                       0
766 #define HDP_BASE__INST5_SEG1                       0
767 #define HDP_BASE__INST5_SEG2                       0
768 #define HDP_BASE__INST5_SEG3                       0
769 #define HDP_BASE__INST5_SEG4                       0
770 #define HDP_BASE__INST5_SEG5                       0
771 
772 #define HDP_BASE__INST6_SEG0                       0
773 #define HDP_BASE__INST6_SEG1                       0
774 #define HDP_BASE__INST6_SEG2                       0
775 #define HDP_BASE__INST6_SEG3                       0
776 #define HDP_BASE__INST6_SEG4                       0
777 #define HDP_BASE__INST6_SEG5                       0
778 
779 #define HDP_BASE__INST7_SEG0                       0
780 #define HDP_BASE__INST7_SEG1                       0
781 #define HDP_BASE__INST7_SEG2                       0
782 #define HDP_BASE__INST7_SEG3                       0
783 #define HDP_BASE__INST7_SEG4                       0
784 #define HDP_BASE__INST7_SEG5                       0
785 
786 #define ISP_BASE__INST0_SEG0                       0x00018000
787 #define ISP_BASE__INST0_SEG1                       0x0240B000
788 #define ISP_BASE__INST0_SEG2                       0
789 #define ISP_BASE__INST0_SEG3                       0
790 #define ISP_BASE__INST0_SEG4                       0
791 #define ISP_BASE__INST0_SEG5                       0
792 
793 #define ISP_BASE__INST1_SEG0                       0
794 #define ISP_BASE__INST1_SEG1                       0
795 #define ISP_BASE__INST1_SEG2                       0
796 #define ISP_BASE__INST1_SEG3                       0
797 #define ISP_BASE__INST1_SEG4                       0
798 #define ISP_BASE__INST1_SEG5                       0
799 
800 #define ISP_BASE__INST2_SEG0                       0
801 #define ISP_BASE__INST2_SEG1                       0
802 #define ISP_BASE__INST2_SEG2                       0
803 #define ISP_BASE__INST2_SEG3                       0
804 #define ISP_BASE__INST2_SEG4                       0
805 #define ISP_BASE__INST2_SEG5                       0
806 
807 #define ISP_BASE__INST3_SEG0                       0
808 #define ISP_BASE__INST3_SEG1                       0
809 #define ISP_BASE__INST3_SEG2                       0
810 #define ISP_BASE__INST3_SEG3                       0
811 #define ISP_BASE__INST3_SEG4                       0
812 #define ISP_BASE__INST3_SEG5                       0
813 
814 #define ISP_BASE__INST4_SEG0                       0
815 #define ISP_BASE__INST4_SEG1                       0
816 #define ISP_BASE__INST4_SEG2                       0
817 #define ISP_BASE__INST4_SEG3                       0
818 #define ISP_BASE__INST4_SEG4                       0
819 #define ISP_BASE__INST4_SEG5                       0
820 
821 #define ISP_BASE__INST5_SEG0                       0
822 #define ISP_BASE__INST5_SEG1                       0
823 #define ISP_BASE__INST5_SEG2                       0
824 #define ISP_BASE__INST5_SEG3                       0
825 #define ISP_BASE__INST5_SEG4                       0
826 #define ISP_BASE__INST5_SEG5                       0
827 
828 #define ISP_BASE__INST6_SEG0                       0
829 #define ISP_BASE__INST6_SEG1                       0
830 #define ISP_BASE__INST6_SEG2                       0
831 #define ISP_BASE__INST6_SEG3                       0
832 #define ISP_BASE__INST6_SEG4                       0
833 #define ISP_BASE__INST6_SEG5                       0
834 
835 #define ISP_BASE__INST7_SEG0                       0
836 #define ISP_BASE__INST7_SEG1                       0
837 #define ISP_BASE__INST7_SEG2                       0
838 #define ISP_BASE__INST7_SEG3                       0
839 #define ISP_BASE__INST7_SEG4                       0
840 #define ISP_BASE__INST7_SEG5                       0
841 
842 #define MMHUB_BASE__INST0_SEG0                     0x00013200
843 #define MMHUB_BASE__INST0_SEG1                     0x0001A000
844 #define MMHUB_BASE__INST0_SEG2                     0x02408800
845 #define MMHUB_BASE__INST0_SEG3                     0
846 #define MMHUB_BASE__INST0_SEG4                     0
847 #define MMHUB_BASE__INST0_SEG5                     0
848 
849 #define MMHUB_BASE__INST1_SEG0                     0
850 #define MMHUB_BASE__INST1_SEG1                     0
851 #define MMHUB_BASE__INST1_SEG2                     0
852 #define MMHUB_BASE__INST1_SEG3                     0
853 #define MMHUB_BASE__INST1_SEG4                     0
854 #define MMHUB_BASE__INST1_SEG5                     0
855 
856 #define MMHUB_BASE__INST2_SEG0                     0
857 #define MMHUB_BASE__INST2_SEG1                     0
858 #define MMHUB_BASE__INST2_SEG2                     0
859 #define MMHUB_BASE__INST2_SEG3                     0
860 #define MMHUB_BASE__INST2_SEG4                     0
861 #define MMHUB_BASE__INST2_SEG5                     0
862 
863 #define MMHUB_BASE__INST3_SEG0                     0
864 #define MMHUB_BASE__INST3_SEG1                     0
865 #define MMHUB_BASE__INST3_SEG2                     0
866 #define MMHUB_BASE__INST3_SEG3                     0
867 #define MMHUB_BASE__INST3_SEG4                     0
868 #define MMHUB_BASE__INST3_SEG5                     0
869 
870 #define MMHUB_BASE__INST4_SEG0                     0
871 #define MMHUB_BASE__INST4_SEG1                     0
872 #define MMHUB_BASE__INST4_SEG2                     0
873 #define MMHUB_BASE__INST4_SEG3                     0
874 #define MMHUB_BASE__INST4_SEG4                     0
875 #define MMHUB_BASE__INST4_SEG5                     0
876 
877 #define MMHUB_BASE__INST5_SEG0                     0
878 #define MMHUB_BASE__INST5_SEG1                     0
879 #define MMHUB_BASE__INST5_SEG2                     0
880 #define MMHUB_BASE__INST5_SEG3                     0
881 #define MMHUB_BASE__INST5_SEG4                     0
882 #define MMHUB_BASE__INST5_SEG5                     0
883 
884 #define MMHUB_BASE__INST6_SEG0                     0
885 #define MMHUB_BASE__INST6_SEG1                     0
886 #define MMHUB_BASE__INST6_SEG2                     0
887 #define MMHUB_BASE__INST6_SEG3                     0
888 #define MMHUB_BASE__INST6_SEG4                     0
889 #define MMHUB_BASE__INST6_SEG5                     0
890 
891 #define MMHUB_BASE__INST7_SEG0                     0
892 #define MMHUB_BASE__INST7_SEG1                     0
893 #define MMHUB_BASE__INST7_SEG2                     0
894 #define MMHUB_BASE__INST7_SEG3                     0
895 #define MMHUB_BASE__INST7_SEG4                     0
896 #define MMHUB_BASE__INST7_SEG5                     0
897 
898 #define MP0_BASE__INST0_SEG0                       0x00016000
899 #define MP0_BASE__INST0_SEG1                       0x0243FC00
900 #define MP0_BASE__INST0_SEG2                       0x00DC0000
901 #define MP0_BASE__INST0_SEG3                       0x00E00000
902 #define MP0_BASE__INST0_SEG4                       0x00E40000
903 #define MP0_BASE__INST0_SEG5                       0
904 
905 #define MP0_BASE__INST1_SEG0                       0
906 #define MP0_BASE__INST1_SEG1                       0
907 #define MP0_BASE__INST1_SEG2                       0
908 #define MP0_BASE__INST1_SEG3                       0
909 #define MP0_BASE__INST1_SEG4                       0
910 #define MP0_BASE__INST1_SEG5                       0
911 
912 #define MP0_BASE__INST2_SEG0                       0
913 #define MP0_BASE__INST2_SEG1                       0
914 #define MP0_BASE__INST2_SEG2                       0
915 #define MP0_BASE__INST2_SEG3                       0
916 #define MP0_BASE__INST2_SEG4                       0
917 #define MP0_BASE__INST2_SEG5                       0
918 
919 #define MP0_BASE__INST3_SEG0                       0
920 #define MP0_BASE__INST3_SEG1                       0
921 #define MP0_BASE__INST3_SEG2                       0
922 #define MP0_BASE__INST3_SEG3                       0
923 #define MP0_BASE__INST3_SEG4                       0
924 #define MP0_BASE__INST3_SEG5                       0
925 
926 #define MP0_BASE__INST4_SEG0                       0
927 #define MP0_BASE__INST4_SEG1                       0
928 #define MP0_BASE__INST4_SEG2                       0
929 #define MP0_BASE__INST4_SEG3                       0
930 #define MP0_BASE__INST4_SEG4                       0
931 #define MP0_BASE__INST4_SEG5                       0
932 
933 #define MP0_BASE__INST5_SEG0                       0
934 #define MP0_BASE__INST5_SEG1                       0
935 #define MP0_BASE__INST5_SEG2                       0
936 #define MP0_BASE__INST5_SEG3                       0
937 #define MP0_BASE__INST5_SEG4                       0
938 #define MP0_BASE__INST5_SEG5                       0
939 
940 #define MP0_BASE__INST6_SEG0                       0
941 #define MP0_BASE__INST6_SEG1                       0
942 #define MP0_BASE__INST6_SEG2                       0
943 #define MP0_BASE__INST6_SEG3                       0
944 #define MP0_BASE__INST6_SEG4                       0
945 #define MP0_BASE__INST6_SEG5                       0
946 
947 #define MP0_BASE__INST7_SEG0                       0
948 #define MP0_BASE__INST7_SEG1                       0
949 #define MP0_BASE__INST7_SEG2                       0
950 #define MP0_BASE__INST7_SEG3                       0
951 #define MP0_BASE__INST7_SEG4                       0
952 #define MP0_BASE__INST7_SEG5                       0
953 
954 #define MP1_BASE__INST0_SEG0                       0x00016000
955 #define MP1_BASE__INST0_SEG1                       0x0243FC00
956 #define MP1_BASE__INST0_SEG2                       0x00DC0000
957 #define MP1_BASE__INST0_SEG3                       0x00E00000
958 #define MP1_BASE__INST0_SEG4                       0x00E40000
959 #define MP1_BASE__INST0_SEG5                       0
960 
961 #define MP1_BASE__INST1_SEG0                       0
962 #define MP1_BASE__INST1_SEG1                       0
963 #define MP1_BASE__INST1_SEG2                       0
964 #define MP1_BASE__INST1_SEG3                       0
965 #define MP1_BASE__INST1_SEG4                       0
966 #define MP1_BASE__INST1_SEG5                       0
967 
968 #define MP1_BASE__INST2_SEG0                       0
969 #define MP1_BASE__INST2_SEG1                       0
970 #define MP1_BASE__INST2_SEG2                       0
971 #define MP1_BASE__INST2_SEG3                       0
972 #define MP1_BASE__INST2_SEG4                       0
973 #define MP1_BASE__INST2_SEG5                       0
974 
975 #define MP1_BASE__INST3_SEG0                       0
976 #define MP1_BASE__INST3_SEG1                       0
977 #define MP1_BASE__INST3_SEG2                       0
978 #define MP1_BASE__INST3_SEG3                       0
979 #define MP1_BASE__INST3_SEG4                       0
980 #define MP1_BASE__INST3_SEG5                       0
981 
982 #define MP1_BASE__INST4_SEG0                       0
983 #define MP1_BASE__INST4_SEG1                       0
984 #define MP1_BASE__INST4_SEG2                       0
985 #define MP1_BASE__INST4_SEG3                       0
986 #define MP1_BASE__INST4_SEG4                       0
987 #define MP1_BASE__INST4_SEG5                       0
988 
989 #define MP1_BASE__INST5_SEG0                       0
990 #define MP1_BASE__INST5_SEG1                       0
991 #define MP1_BASE__INST5_SEG2                       0
992 #define MP1_BASE__INST5_SEG3                       0
993 #define MP1_BASE__INST5_SEG4                       0
994 #define MP1_BASE__INST5_SEG5                       0
995 
996 #define MP1_BASE__INST6_SEG0                       0
997 #define MP1_BASE__INST6_SEG1                       0
998 #define MP1_BASE__INST6_SEG2                       0
999 #define MP1_BASE__INST6_SEG3                       0
1000 #define MP1_BASE__INST6_SEG4                       0
1001 #define MP1_BASE__INST6_SEG5                       0
1002 
1003 #define MP1_BASE__INST7_SEG0                       0
1004 #define MP1_BASE__INST7_SEG1                       0
1005 #define MP1_BASE__INST7_SEG2                       0
1006 #define MP1_BASE__INST7_SEG3                       0
1007 #define MP1_BASE__INST7_SEG4                       0
1008 #define MP1_BASE__INST7_SEG5                       0
1009 
1010 #define MP2_BASE__INST0_SEG0                       0x00016400
1011 #define MP2_BASE__INST0_SEG1                       0x02400800
1012 #define MP2_BASE__INST0_SEG2                       0x00F40000
1013 #define MP2_BASE__INST0_SEG3                       0x00F80000
1014 #define MP2_BASE__INST0_SEG4                       0x00FC0000
1015 #define MP2_BASE__INST0_SEG5                       0
1016 
1017 #define MP2_BASE__INST1_SEG0                       0
1018 #define MP2_BASE__INST1_SEG1                       0
1019 #define MP2_BASE__INST1_SEG2                       0
1020 #define MP2_BASE__INST1_SEG3                       0
1021 #define MP2_BASE__INST1_SEG4                       0
1022 #define MP2_BASE__INST1_SEG5                       0
1023 
1024 #define MP2_BASE__INST2_SEG0                       0
1025 #define MP2_BASE__INST2_SEG1                       0
1026 #define MP2_BASE__INST2_SEG2                       0
1027 #define MP2_BASE__INST2_SEG3                       0
1028 #define MP2_BASE__INST2_SEG4                       0
1029 #define MP2_BASE__INST2_SEG5                       0
1030 
1031 #define MP2_BASE__INST3_SEG0                       0
1032 #define MP2_BASE__INST3_SEG1                       0
1033 #define MP2_BASE__INST3_SEG2                       0
1034 #define MP2_BASE__INST3_SEG3                       0
1035 #define MP2_BASE__INST3_SEG4                       0
1036 #define MP2_BASE__INST3_SEG5                       0
1037 
1038 #define MP2_BASE__INST4_SEG0                       0
1039 #define MP2_BASE__INST4_SEG1                       0
1040 #define MP2_BASE__INST4_SEG2                       0
1041 #define MP2_BASE__INST4_SEG3                       0
1042 #define MP2_BASE__INST4_SEG4                       0
1043 #define MP2_BASE__INST4_SEG5                       0
1044 
1045 #define MP2_BASE__INST5_SEG0                       0
1046 #define MP2_BASE__INST5_SEG1                       0
1047 #define MP2_BASE__INST5_SEG2                       0
1048 #define MP2_BASE__INST5_SEG3                       0
1049 #define MP2_BASE__INST5_SEG4                       0
1050 #define MP2_BASE__INST5_SEG5                       0
1051 
1052 #define MP2_BASE__INST6_SEG0                       0
1053 #define MP2_BASE__INST6_SEG1                       0
1054 #define MP2_BASE__INST6_SEG2                       0
1055 #define MP2_BASE__INST6_SEG3                       0
1056 #define MP2_BASE__INST6_SEG4                       0
1057 #define MP2_BASE__INST6_SEG5                       0
1058 
1059 #define MP2_BASE__INST7_SEG0                       0
1060 #define MP2_BASE__INST7_SEG1                       0
1061 #define MP2_BASE__INST7_SEG2                       0
1062 #define MP2_BASE__INST7_SEG3                       0
1063 #define MP2_BASE__INST7_SEG4                       0
1064 #define MP2_BASE__INST7_SEG5                       0
1065 
1066 #define NBIO_BASE__INST0_SEG0                      0x00000000
1067 #define NBIO_BASE__INST0_SEG1                      0x00000014
1068 #define NBIO_BASE__INST0_SEG2                      0x00000D20
1069 #define NBIO_BASE__INST0_SEG3                      0x00010400
1070 #define NBIO_BASE__INST0_SEG4                      0x0241B000
1071 #define NBIO_BASE__INST0_SEG5                      0x04040000
1072 
1073 #define NBIO_BASE__INST1_SEG0                      0
1074 #define NBIO_BASE__INST1_SEG1                      0
1075 #define NBIO_BASE__INST1_SEG2                      0
1076 #define NBIO_BASE__INST1_SEG3                      0
1077 #define NBIO_BASE__INST1_SEG4                      0
1078 #define NBIO_BASE__INST1_SEG5                      0
1079 
1080 #define NBIO_BASE__INST2_SEG0                      0
1081 #define NBIO_BASE__INST2_SEG1                      0
1082 #define NBIO_BASE__INST2_SEG2                      0
1083 #define NBIO_BASE__INST2_SEG3                      0
1084 #define NBIO_BASE__INST2_SEG4                      0
1085 #define NBIO_BASE__INST2_SEG5                      0
1086 
1087 #define NBIO_BASE__INST3_SEG0                      0
1088 #define NBIO_BASE__INST3_SEG1                      0
1089 #define NBIO_BASE__INST3_SEG2                      0
1090 #define NBIO_BASE__INST3_SEG3                      0
1091 #define NBIO_BASE__INST3_SEG4                      0
1092 #define NBIO_BASE__INST3_SEG5                      0
1093 
1094 #define NBIO_BASE__INST4_SEG0                      0
1095 #define NBIO_BASE__INST4_SEG1                      0
1096 #define NBIO_BASE__INST4_SEG2                      0
1097 #define NBIO_BASE__INST4_SEG3                      0
1098 #define NBIO_BASE__INST4_SEG4                      0
1099 #define NBIO_BASE__INST4_SEG5                      0
1100 
1101 #define NBIO_BASE__INST5_SEG0                      0
1102 #define NBIO_BASE__INST5_SEG1                      0
1103 #define NBIO_BASE__INST5_SEG2                      0
1104 #define NBIO_BASE__INST5_SEG3                      0
1105 #define NBIO_BASE__INST5_SEG4                      0
1106 #define NBIO_BASE__INST5_SEG5                      0
1107 
1108 #define NBIO_BASE__INST6_SEG0                      0
1109 #define NBIO_BASE__INST6_SEG1                      0
1110 #define NBIO_BASE__INST6_SEG2                      0
1111 #define NBIO_BASE__INST6_SEG3                      0
1112 #define NBIO_BASE__INST6_SEG4                      0
1113 #define NBIO_BASE__INST6_SEG5                      0
1114 
1115 #define NBIO_BASE__INST7_SEG0                      0
1116 #define NBIO_BASE__INST7_SEG1                      0
1117 #define NBIO_BASE__INST7_SEG2                      0
1118 #define NBIO_BASE__INST7_SEG3                      0
1119 #define NBIO_BASE__INST7_SEG4                      0
1120 #define NBIO_BASE__INST7_SEG5                      0
1121 
1122 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
1123 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
1124 #define OSSSYS_BASE__INST0_SEG2                    0
1125 #define OSSSYS_BASE__INST0_SEG3                    0
1126 #define OSSSYS_BASE__INST0_SEG4                    0
1127 #define OSSSYS_BASE__INST0_SEG5                    0
1128 
1129 #define OSSSYS_BASE__INST1_SEG0                    0
1130 #define OSSSYS_BASE__INST1_SEG1                    0
1131 #define OSSSYS_BASE__INST1_SEG2                    0
1132 #define OSSSYS_BASE__INST1_SEG3                    0
1133 #define OSSSYS_BASE__INST1_SEG4                    0
1134 #define OSSSYS_BASE__INST1_SEG5                    0
1135 
1136 #define OSSSYS_BASE__INST2_SEG0                    0
1137 #define OSSSYS_BASE__INST2_SEG1                    0
1138 #define OSSSYS_BASE__INST2_SEG2                    0
1139 #define OSSSYS_BASE__INST2_SEG3                    0
1140 #define OSSSYS_BASE__INST2_SEG4                    0
1141 #define OSSSYS_BASE__INST2_SEG5                    0
1142 
1143 #define OSSSYS_BASE__INST3_SEG0                    0
1144 #define OSSSYS_BASE__INST3_SEG1                    0
1145 #define OSSSYS_BASE__INST3_SEG2                    0
1146 #define OSSSYS_BASE__INST3_SEG3                    0
1147 #define OSSSYS_BASE__INST3_SEG4                    0
1148 #define OSSSYS_BASE__INST3_SEG5                    0
1149 
1150 #define OSSSYS_BASE__INST4_SEG0                    0
1151 #define OSSSYS_BASE__INST4_SEG1                    0
1152 #define OSSSYS_BASE__INST4_SEG2                    0
1153 #define OSSSYS_BASE__INST4_SEG3                    0
1154 #define OSSSYS_BASE__INST4_SEG4                    0
1155 #define OSSSYS_BASE__INST4_SEG5                    0
1156 
1157 #define OSSSYS_BASE__INST5_SEG0                    0
1158 #define OSSSYS_BASE__INST5_SEG1                    0
1159 #define OSSSYS_BASE__INST5_SEG2                    0
1160 #define OSSSYS_BASE__INST5_SEG3                    0
1161 #define OSSSYS_BASE__INST5_SEG4                    0
1162 #define OSSSYS_BASE__INST5_SEG5                    0
1163 
1164 #define OSSSYS_BASE__INST6_SEG0                    0
1165 #define OSSSYS_BASE__INST6_SEG1                    0
1166 #define OSSSYS_BASE__INST6_SEG2                    0
1167 #define OSSSYS_BASE__INST6_SEG3                    0
1168 #define OSSSYS_BASE__INST6_SEG4                    0
1169 #define OSSSYS_BASE__INST6_SEG5                    0
1170 
1171 #define OSSSYS_BASE__INST7_SEG0                    0
1172 #define OSSSYS_BASE__INST7_SEG1                    0
1173 #define OSSSYS_BASE__INST7_SEG2                    0
1174 #define OSSSYS_BASE__INST7_SEG3                    0
1175 #define OSSSYS_BASE__INST7_SEG4                    0
1176 #define OSSSYS_BASE__INST7_SEG5                    0
1177 
1178 #define PCIE0_BASE__INST0_SEG0                     0x00000000
1179 #define PCIE0_BASE__INST0_SEG1                     0x00000014
1180 #define PCIE0_BASE__INST0_SEG2                     0x00000D20
1181 #define PCIE0_BASE__INST0_SEG3                     0x00010400
1182 #define PCIE0_BASE__INST0_SEG4                     0x0241B000
1183 #define PCIE0_BASE__INST0_SEG5                     0x04040000
1184 
1185 #define PCIE0_BASE__INST1_SEG0                     0
1186 #define PCIE0_BASE__INST1_SEG1                     0
1187 #define PCIE0_BASE__INST1_SEG2                     0
1188 #define PCIE0_BASE__INST1_SEG3                     0
1189 #define PCIE0_BASE__INST1_SEG4                     0
1190 #define PCIE0_BASE__INST1_SEG5                     0
1191 
1192 #define PCIE0_BASE__INST2_SEG0                     0
1193 #define PCIE0_BASE__INST2_SEG1                     0
1194 #define PCIE0_BASE__INST2_SEG2                     0
1195 #define PCIE0_BASE__INST2_SEG3                     0
1196 #define PCIE0_BASE__INST2_SEG4                     0
1197 #define PCIE0_BASE__INST2_SEG5                     0
1198 
1199 #define PCIE0_BASE__INST3_SEG0                     0
1200 #define PCIE0_BASE__INST3_SEG1                     0
1201 #define PCIE0_BASE__INST3_SEG2                     0
1202 #define PCIE0_BASE__INST3_SEG3                     0
1203 #define PCIE0_BASE__INST3_SEG4                     0
1204 #define PCIE0_BASE__INST3_SEG5                     0
1205 
1206 #define PCIE0_BASE__INST4_SEG0                     0
1207 #define PCIE0_BASE__INST4_SEG1                     0
1208 #define PCIE0_BASE__INST4_SEG2                     0
1209 #define PCIE0_BASE__INST4_SEG3                     0
1210 #define PCIE0_BASE__INST4_SEG4                     0
1211 #define PCIE0_BASE__INST4_SEG5                     0
1212 
1213 #define PCIE0_BASE__INST5_SEG0                     0
1214 #define PCIE0_BASE__INST5_SEG1                     0
1215 #define PCIE0_BASE__INST5_SEG2                     0
1216 #define PCIE0_BASE__INST5_SEG3                     0
1217 #define PCIE0_BASE__INST5_SEG4                     0
1218 #define PCIE0_BASE__INST5_SEG5                     0
1219 
1220 #define PCIE0_BASE__INST6_SEG0                     0
1221 #define PCIE0_BASE__INST6_SEG1                     0
1222 #define PCIE0_BASE__INST6_SEG2                     0
1223 #define PCIE0_BASE__INST6_SEG3                     0
1224 #define PCIE0_BASE__INST6_SEG4                     0
1225 #define PCIE0_BASE__INST6_SEG5                     0
1226 
1227 #define PCIE0_BASE__INST7_SEG0                     0
1228 #define PCIE0_BASE__INST7_SEG1                     0
1229 #define PCIE0_BASE__INST7_SEG2                     0
1230 #define PCIE0_BASE__INST7_SEG3                     0
1231 #define PCIE0_BASE__INST7_SEG4                     0
1232 #define PCIE0_BASE__INST7_SEG5                     0
1233 
1234 #define SMUIO_BASE__INST0_SEG0                      0x00016800
1235 #define SMUIO_BASE__INST0_SEG1                      0x00016A00
1236 #define SMUIO_BASE__INST0_SEG2                      0x02401000
1237 #define SMUIO_BASE__INST0_SEG3                      0x00440000
1238 #define SMUIO_BASE__INST0_SEG4                      0
1239 #define SMUIO_BASE__INST0_SEG5                      0
1240 
1241 #define SMUIO_BASE__INST1_SEG0                      0x0001BC00
1242 #define SMUIO_BASE__INST1_SEG1                      0x0242D400
1243 #define SMUIO_BASE__INST1_SEG2                      0
1244 #define SMUIO_BASE__INST1_SEG3                      0
1245 #define SMUIO_BASE__INST1_SEG4                      0
1246 #define SMUIO_BASE__INST1_SEG5                      0
1247 
1248 #define SMUIO_BASE__INST2_SEG0                      0
1249 #define SMUIO_BASE__INST2_SEG1                      0
1250 #define SMUIO_BASE__INST2_SEG2                      0
1251 #define SMUIO_BASE__INST2_SEG3                      0
1252 #define SMUIO_BASE__INST2_SEG4                      0
1253 #define SMUIO_BASE__INST2_SEG5                      0
1254 
1255 #define SMUIO_BASE__INST3_SEG0                      0
1256 #define SMUIO_BASE__INST3_SEG1                      0
1257 #define SMUIO_BASE__INST3_SEG2                      0
1258 #define SMUIO_BASE__INST3_SEG3                      0
1259 #define SMUIO_BASE__INST3_SEG4                      0
1260 #define SMUIO_BASE__INST3_SEG5                      0
1261 
1262 #define SMUIO_BASE__INST4_SEG0                      0
1263 #define SMUIO_BASE__INST4_SEG1                      0
1264 #define SMUIO_BASE__INST4_SEG2                      0
1265 #define SMUIO_BASE__INST4_SEG3                      0
1266 #define SMUIO_BASE__INST4_SEG4                      0
1267 #define SMUIO_BASE__INST4_SEG5                      0
1268 
1269 #define SMUIO_BASE__INST5_SEG0                      0
1270 #define SMUIO_BASE__INST5_SEG1                      0
1271 #define SMUIO_BASE__INST5_SEG2                      0
1272 #define SMUIO_BASE__INST5_SEG3                      0
1273 #define SMUIO_BASE__INST5_SEG4                      0
1274 #define SMUIO_BASE__INST5_SEG5                      0
1275 
1276 #define SMUIO_BASE__INST6_SEG0                      0
1277 #define SMUIO_BASE__INST6_SEG1                      0
1278 #define SMUIO_BASE__INST6_SEG2                      0
1279 #define SMUIO_BASE__INST6_SEG3                      0
1280 #define SMUIO_BASE__INST6_SEG4                      0
1281 #define SMUIO_BASE__INST6_SEG5                      0
1282 
1283 #define SMUIO_BASE__INST7_SEG0                      0
1284 #define SMUIO_BASE__INST7_SEG1                      0
1285 #define SMUIO_BASE__INST7_SEG2                      0
1286 #define SMUIO_BASE__INST7_SEG3                      0
1287 #define SMUIO_BASE__INST7_SEG4                      0
1288 #define SMUIO_BASE__INST7_SEG5                      0
1289 
1290 #define THM_BASE__INST0_SEG0                       0x00016600
1291 #define THM_BASE__INST0_SEG1                       0x02400C00
1292 #define THM_BASE__INST0_SEG2                       0
1293 #define THM_BASE__INST0_SEG3                       0
1294 #define THM_BASE__INST0_SEG4                       0
1295 #define THM_BASE__INST0_SEG5                       0
1296 
1297 #define THM_BASE__INST1_SEG0                       0
1298 #define THM_BASE__INST1_SEG1                       0
1299 #define THM_BASE__INST1_SEG2                       0
1300 #define THM_BASE__INST1_SEG3                       0
1301 #define THM_BASE__INST1_SEG4                       0
1302 #define THM_BASE__INST1_SEG5                       0
1303 
1304 #define THM_BASE__INST2_SEG0                       0
1305 #define THM_BASE__INST2_SEG1                       0
1306 #define THM_BASE__INST2_SEG2                       0
1307 #define THM_BASE__INST2_SEG3                       0
1308 #define THM_BASE__INST2_SEG4                       0
1309 #define THM_BASE__INST2_SEG5                       0
1310 
1311 #define THM_BASE__INST3_SEG0                       0
1312 #define THM_BASE__INST3_SEG1                       0
1313 #define THM_BASE__INST3_SEG2                       0
1314 #define THM_BASE__INST3_SEG3                       0
1315 #define THM_BASE__INST3_SEG4                       0
1316 #define THM_BASE__INST3_SEG5                       0
1317 
1318 #define THM_BASE__INST4_SEG0                       0
1319 #define THM_BASE__INST4_SEG1                       0
1320 #define THM_BASE__INST4_SEG2                       0
1321 #define THM_BASE__INST4_SEG3                       0
1322 #define THM_BASE__INST4_SEG4                       0
1323 #define THM_BASE__INST4_SEG5                       0
1324 
1325 #define THM_BASE__INST5_SEG0                       0
1326 #define THM_BASE__INST5_SEG1                       0
1327 #define THM_BASE__INST5_SEG2                       0
1328 #define THM_BASE__INST5_SEG3                       0
1329 #define THM_BASE__INST5_SEG4                       0
1330 #define THM_BASE__INST5_SEG5                       0
1331 
1332 #define THM_BASE__INST6_SEG0                       0
1333 #define THM_BASE__INST6_SEG1                       0
1334 #define THM_BASE__INST6_SEG2                       0
1335 #define THM_BASE__INST6_SEG3                       0
1336 #define THM_BASE__INST6_SEG4                       0
1337 #define THM_BASE__INST6_SEG5                       0
1338 
1339 #define THM_BASE__INST7_SEG0                       0
1340 #define THM_BASE__INST7_SEG1                       0
1341 #define THM_BASE__INST7_SEG2                       0
1342 #define THM_BASE__INST7_SEG3                       0
1343 #define THM_BASE__INST7_SEG4                       0
1344 #define THM_BASE__INST7_SEG5                       0
1345 
1346 #define UMC_BASE__INST0_SEG0                       0x00014000
1347 #define UMC_BASE__INST0_SEG1                       0x02425800
1348 #define UMC_BASE__INST0_SEG2                       0
1349 #define UMC_BASE__INST0_SEG3                       0
1350 #define UMC_BASE__INST0_SEG4                       0
1351 #define UMC_BASE__INST0_SEG5                       0
1352 
1353 #define UMC_BASE__INST1_SEG0                       0x00054000
1354 #define UMC_BASE__INST1_SEG1                       0x02425C00
1355 #define UMC_BASE__INST1_SEG2                       0
1356 #define UMC_BASE__INST1_SEG3                       0
1357 #define UMC_BASE__INST1_SEG4                       0
1358 #define UMC_BASE__INST1_SEG5                       0
1359 
1360 #define UMC_BASE__INST2_SEG0                       0x00094000
1361 #define UMC_BASE__INST2_SEG1                       0x02426000
1362 #define UMC_BASE__INST2_SEG2                       0
1363 #define UMC_BASE__INST2_SEG3                       0
1364 #define UMC_BASE__INST2_SEG4                       0
1365 #define UMC_BASE__INST2_SEG5                       0
1366 
1367 #define UMC_BASE__INST3_SEG0                       0x000D4000
1368 #define UMC_BASE__INST3_SEG1                       0x02426400
1369 #define UMC_BASE__INST3_SEG2                       0
1370 #define UMC_BASE__INST3_SEG3                       0
1371 #define UMC_BASE__INST3_SEG4                       0
1372 #define UMC_BASE__INST3_SEG5                       0
1373 
1374 #define UMC_BASE__INST4_SEG0                       0
1375 #define UMC_BASE__INST4_SEG1                       0
1376 #define UMC_BASE__INST4_SEG2                       0
1377 #define UMC_BASE__INST4_SEG3                       0
1378 #define UMC_BASE__INST4_SEG4                       0
1379 #define UMC_BASE__INST4_SEG5                       0
1380 
1381 #define UMC_BASE__INST5_SEG0                       0
1382 #define UMC_BASE__INST5_SEG1                       0
1383 #define UMC_BASE__INST5_SEG2                       0
1384 #define UMC_BASE__INST5_SEG3                       0
1385 #define UMC_BASE__INST5_SEG4                       0
1386 #define UMC_BASE__INST5_SEG5                       0
1387 
1388 #define UMC_BASE__INST6_SEG0                       0
1389 #define UMC_BASE__INST6_SEG1                       0
1390 #define UMC_BASE__INST6_SEG2                       0
1391 #define UMC_BASE__INST6_SEG3                       0
1392 #define UMC_BASE__INST6_SEG4                       0
1393 #define UMC_BASE__INST6_SEG5                       0
1394 
1395 #define UMC_BASE__INST7_SEG0                       0
1396 #define UMC_BASE__INST7_SEG1                       0
1397 #define UMC_BASE__INST7_SEG2                       0
1398 #define UMC_BASE__INST7_SEG3                       0
1399 #define UMC_BASE__INST7_SEG4                       0
1400 #define UMC_BASE__INST7_SEG5                       0
1401 
1402 #define USB_BASE__INST0_SEG0                       0x0242A800
1403 #define USB_BASE__INST0_SEG1                       0x05B00000
1404 #define USB_BASE__INST0_SEG2                       0
1405 #define USB_BASE__INST0_SEG3                       0
1406 #define USB_BASE__INST0_SEG4                       0
1407 #define USB_BASE__INST0_SEG5                       0
1408 
1409 #define USB_BASE__INST1_SEG0                       0x0242AC00
1410 #define USB_BASE__INST1_SEG1                       0x05B80000
1411 #define USB_BASE__INST1_SEG2                       0
1412 #define USB_BASE__INST1_SEG3                       0
1413 #define USB_BASE__INST1_SEG4                       0
1414 #define USB_BASE__INST1_SEG5                       0
1415 
1416 #define USB_BASE__INST2_SEG0                       0x0242B000
1417 #define USB_BASE__INST2_SEG1                       0x05C00000
1418 #define USB_BASE__INST2_SEG2                       0
1419 #define USB_BASE__INST2_SEG3                       0
1420 #define USB_BASE__INST2_SEG4                       0
1421 #define USB_BASE__INST2_SEG5                       0
1422 
1423 #define USB_BASE__INST3_SEG0                       0
1424 #define USB_BASE__INST3_SEG1                       0
1425 #define USB_BASE__INST3_SEG2                       0
1426 #define USB_BASE__INST3_SEG3                       0
1427 #define USB_BASE__INST3_SEG4                       0
1428 #define USB_BASE__INST3_SEG5                       0
1429 
1430 #define USB_BASE__INST4_SEG0                       0
1431 #define USB_BASE__INST4_SEG1                       0
1432 #define USB_BASE__INST4_SEG2                       0
1433 #define USB_BASE__INST4_SEG3                       0
1434 #define USB_BASE__INST4_SEG4                       0
1435 #define USB_BASE__INST4_SEG5                       0
1436 
1437 #define USB_BASE__INST5_SEG0                       0
1438 #define USB_BASE__INST5_SEG1                       0
1439 #define USB_BASE__INST5_SEG2                       0
1440 #define USB_BASE__INST5_SEG3                       0
1441 #define USB_BASE__INST5_SEG4                       0
1442 #define USB_BASE__INST5_SEG5                       0
1443 
1444 #define USB_BASE__INST6_SEG0                       0
1445 #define USB_BASE__INST6_SEG1                       0
1446 #define USB_BASE__INST6_SEG2                       0
1447 #define USB_BASE__INST6_SEG3                       0
1448 #define USB_BASE__INST6_SEG4                       0
1449 #define USB_BASE__INST6_SEG5                       0
1450 
1451 #define USB_BASE__INST7_SEG0                       0
1452 #define USB_BASE__INST7_SEG1                       0
1453 #define USB_BASE__INST7_SEG2                       0
1454 #define USB_BASE__INST7_SEG3                       0
1455 #define USB_BASE__INST7_SEG4                       0
1456 #define USB_BASE__INST7_SEG5                       0
1457 
1458 #define VCN_BASE__INST0_SEG0                      0x00007800
1459 #define VCN_BASE__INST0_SEG1                      0x00007E00
1460 #define VCN_BASE__INST0_SEG2                      0x02403000
1461 #define VCN_BASE__INST0_SEG3                      0
1462 #define VCN_BASE__INST0_SEG4                      0
1463 #define VCN_BASE__INST0_SEG5                      0
1464 
1465 #define VCN_BASE__INST1_SEG0                      0
1466 #define VCN_BASE__INST1_SEG1                      0
1467 #define VCN_BASE__INST1_SEG2                      0
1468 #define VCN_BASE__INST1_SEG3                      0
1469 #define VCN_BASE__INST1_SEG4                      0
1470 #define VCN_BASE__INST1_SEG5                      0
1471 
1472 #define VCN_BASE__INST2_SEG0                      0
1473 #define VCN_BASE__INST2_SEG1                      0
1474 #define VCN_BASE__INST2_SEG2                      0
1475 #define VCN_BASE__INST2_SEG3                      0
1476 #define VCN_BASE__INST2_SEG4                      0
1477 #define VCN_BASE__INST2_SEG5                      0
1478 
1479 #define VCN_BASE__INST3_SEG0                      0
1480 #define VCN_BASE__INST3_SEG1                      0
1481 #define VCN_BASE__INST3_SEG2                      0
1482 #define VCN_BASE__INST3_SEG3                      0
1483 #define VCN_BASE__INST3_SEG4                      0
1484 #define VCN_BASE__INST3_SEG5                      0
1485 
1486 #define VCN_BASE__INST4_SEG0                      0
1487 #define VCN_BASE__INST4_SEG1                      0
1488 #define VCN_BASE__INST4_SEG2                      0
1489 #define VCN_BASE__INST4_SEG3                      0
1490 #define VCN_BASE__INST4_SEG4                      0
1491 #define VCN_BASE__INST4_SEG5                      0
1492 
1493 #define VCN_BASE__INST5_SEG0                      0
1494 #define VCN_BASE__INST5_SEG1                      0
1495 #define VCN_BASE__INST5_SEG2                      0
1496 #define VCN_BASE__INST5_SEG3                      0
1497 #define VCN_BASE__INST5_SEG4                      0
1498 #define VCN_BASE__INST5_SEG5                      0
1499 
1500 #define VCN_BASE__INST6_SEG0                      0
1501 #define VCN_BASE__INST6_SEG1                      0
1502 #define VCN_BASE__INST6_SEG2                      0
1503 #define VCN_BASE__INST6_SEG3                      0
1504 #define VCN_BASE__INST6_SEG4                      0
1505 #define VCN_BASE__INST6_SEG5                      0
1506 
1507 #define VCN_BASE__INST7_SEG0                      0
1508 #define VCN_BASE__INST7_SEG1                      0
1509 #define VCN_BASE__INST7_SEG2                      0
1510 #define VCN_BASE__INST7_SEG3                      0
1511 #define VCN_BASE__INST7_SEG4                      0
1512 #define VCN_BASE__INST7_SEG5                      0
1513 
1514 #endif
1515