1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) Meta Platforms, Inc. and affiliates. */ 3 4 #ifndef _FBNIC_CSR_H_ 5 #define _FBNIC_CSR_H_ 6 7 #include <linux/bitops.h> 8 9 struct fbnic_dev; 10 11 #define CSR_BIT(nr) (1u << (nr)) 12 #define CSR_GENMASK(h, l) GENMASK(h, l) 13 14 #define DESC_BIT(nr) BIT_ULL(nr) 15 #define DESC_GENMASK(h, l) GENMASK_ULL(h, l) 16 17 #define FW_VER_CODE(_major, _minor, _patch, _build) ( \ 18 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_MAJOR, _major) | \ 19 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_MINOR, _minor) | \ 20 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_PATCH, _patch) | \ 21 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_BUILD, _build)) 22 23 /* Defines the minimum firmware version required by the driver */ 24 #define MIN_FW_VER_CODE FW_VER_CODE(0, 10, 6, 0) 25 26 /* Defines the minimum firmware version required for firmware logs */ 27 #define MIN_FW_VER_CODE_LOG FW_VER_CODE(0, 12, 9, 0) 28 29 /* Driver can request that firmware sends all cached logs in bulk. This 30 * feature was enabled on older firmware however firmware has a bug 31 * which attempted to send 30 messages per mbx message which caused an 32 * overflow flooding the mailbox. This results in a kernel warning 33 * related to corrupt mailbox messages. 34 * 35 * If firmware is new enough only request sending historical logs when 36 * the log buffer is empty to prevent duplicate logs. 37 */ 38 #define MIN_FW_VER_CODE_HIST FW_VER_CODE(25, 5, 7, 0) 39 40 #define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013 41 42 #define FBNIC_CLOCK_FREQ (600 * (1000 * 1000)) 43 44 /* Transmit Work Descriptor Format */ 45 /* Length, Type, Offset Masks and Shifts */ 46 #define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0) 47 48 #define FBNIC_TWD_L3_TYPE_MASK DESC_GENMASK(7, 6) 49 enum { 50 FBNIC_TWD_L3_TYPE_OTHER = 0, 51 FBNIC_TWD_L3_TYPE_IPV4 = 1, 52 FBNIC_TWD_L3_TYPE_IPV6 = 2, 53 FBNIC_TWD_L3_TYPE_V6V6 = 3, 54 }; 55 56 #define FBNIC_TWD_L3_OHLEN_MASK DESC_GENMASK(15, 8) 57 #define FBNIC_TWD_L3_IHLEN_MASK DESC_GENMASK(23, 16) 58 59 enum { 60 FBNIC_TWD_L4_TYPE_OTHER = 0, 61 FBNIC_TWD_L4_TYPE_TCP = 1, 62 FBNIC_TWD_L4_TYPE_UDP = 2, 63 }; 64 65 #define FBNIC_TWD_CSUM_OFFSET_MASK DESC_GENMASK(27, 24) 66 #define FBNIC_TWD_L4_HLEN_MASK DESC_GENMASK(31, 28) 67 68 /* Flags and Type */ 69 #define FBNIC_TWD_L4_TYPE_MASK DESC_GENMASK(33, 32) 70 #define FBNIC_TWD_FLAG_REQ_TS DESC_BIT(34) 71 #define FBNIC_TWD_FLAG_REQ_LSO DESC_BIT(35) 72 #define FBNIC_TWD_FLAG_REQ_CSO DESC_BIT(36) 73 #define FBNIC_TWD_FLAG_REQ_COMPLETION DESC_BIT(37) 74 #define FBNIC_TWD_FLAG_DEST_MAC DESC_BIT(43) 75 #define FBNIC_TWD_FLAG_DEST_BMC DESC_BIT(44) 76 #define FBNIC_TWD_FLAG_DEST_FW DESC_BIT(45) 77 #define FBNIC_TWD_TYPE_MASK DESC_GENMASK(47, 46) 78 enum { 79 FBNIC_TWD_TYPE_META = 0, 80 FBNIC_TWD_TYPE_OPT_META = 1, 81 FBNIC_TWD_TYPE_AL = 2, 82 FBNIC_TWD_TYPE_LAST_AL = 3, 83 }; 84 85 /* MSS and Completion Req */ 86 #define FBNIC_TWD_MSS_MASK DESC_GENMASK(61, 48) 87 88 #define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0) 89 #define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0) 90 #define FBNIC_TWD_LEN_MASK DESC_GENMASK(63, 48) 91 92 /* Tx Completion Descriptor Format */ 93 #define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0) 94 #define FBNIC_TCD_TYPE0_HEAD1_MASK DESC_GENMASK(31, 16) 95 96 #define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0) 97 98 #define FBNIC_TCD_STATUS_MASK DESC_GENMASK(59, 48) 99 #define FBNIC_TCD_STATUS_TS_INVALID DESC_BIT(48) 100 #define FBNIC_TCD_STATUS_ILLEGAL_TS_REQ DESC_BIT(49) 101 #define FBNIC_TCD_TWQ1 DESC_BIT(60) 102 #define FBNIC_TCD_TYPE_MASK DESC_GENMASK(62, 61) 103 enum { 104 FBNIC_TCD_TYPE_0 = 0, 105 FBNIC_TCD_TYPE_1 = 1, 106 }; 107 108 #define FBNIC_TCD_DONE DESC_BIT(63) 109 110 /* Rx Buffer Descriptor Format 111 * 112 * The layout of this can vary depending on the page size of the system. 113 * 114 * If the page size is 4K then the layout will simply consist of ID for 115 * the 16 most significant bits, and the lower 46 are essentially the page 116 * address with the lowest 12 bits being reserved 0 due to the fact that 117 * a page will be aligned. 118 * 119 * If the page size is larger than 4K then the lower n bits of the ID and 120 * page address will be reserved for the fragment ID. This fragment will 121 * be 4K in size and will be used to index both the DMA address and the ID 122 * by the same amount. 123 */ 124 #define FBNIC_BD_DESC_ADDR_MASK DESC_GENMASK(45, 12) 125 #define FBNIC_BD_DESC_ID_MASK DESC_GENMASK(63, 48) 126 #define FBNIC_BD_FRAG_SIZE \ 127 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1)) 128 #define FBNIC_BD_FRAG_COUNT \ 129 (PAGE_SIZE / FBNIC_BD_FRAG_SIZE) 130 #define FBNIC_BD_FRAG_ADDR_MASK \ 131 (FBNIC_BD_DESC_ADDR_MASK & \ 132 ~(FBNIC_BD_DESC_ADDR_MASK * FBNIC_BD_FRAG_COUNT)) 133 #define FBNIC_BD_FRAG_ID_MASK \ 134 (FBNIC_BD_DESC_ID_MASK & \ 135 ~(FBNIC_BD_DESC_ID_MASK * FBNIC_BD_FRAG_COUNT)) 136 #define FBNIC_BD_PAGE_ADDR_MASK \ 137 (FBNIC_BD_DESC_ADDR_MASK & ~FBNIC_BD_FRAG_ADDR_MASK) 138 #define FBNIC_BD_PAGE_ID_MASK \ 139 (FBNIC_BD_DESC_ID_MASK & ~FBNIC_BD_FRAG_ID_MASK) 140 141 /* Rx Completion Queue Descriptors */ 142 #define FBNIC_RCD_TYPE_MASK DESC_GENMASK(62, 61) 143 enum { 144 FBNIC_RCD_TYPE_HDR_AL = 0, 145 FBNIC_RCD_TYPE_PAY_AL = 1, 146 FBNIC_RCD_TYPE_OPT_META = 2, 147 FBNIC_RCD_TYPE_META = 3, 148 }; 149 150 #define FBNIC_RCD_DONE DESC_BIT(63) 151 152 /* Address/Length Completion Descriptors */ 153 #define FBNIC_RCD_AL_BUFF_ID_MASK DESC_GENMASK(15, 0) 154 #define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1) 155 #define FBNIC_RCD_AL_BUFF_PAGE_MASK \ 156 (FBNIC_RCD_AL_BUFF_ID_MASK & ~FBNIC_RCD_AL_BUFF_FRAG_MASK) 157 #define FBNIC_RCD_AL_BUFF_LEN_MASK DESC_GENMASK(28, 16) 158 #define FBNIC_RCD_AL_BUFF_OFF_MASK DESC_GENMASK(43, 32) 159 #define FBNIC_RCD_AL_PAGE_FIN DESC_BIT(60) 160 161 /* Header AL specific values */ 162 #define FBNIC_RCD_HDR_AL_OVERFLOW DESC_BIT(53) 163 #define FBNIC_RCD_HDR_AL_DMA_HINT_MASK DESC_GENMASK(59, 54) 164 enum { 165 FBNIC_RCD_HDR_AL_DMA_HINT_NONE = 0, 166 FBNIC_RCD_HDR_AL_DMA_HINT_L2 = 1, 167 FBNIC_RCD_HDR_AL_DMA_HINT_L3 = 2, 168 FBNIC_RCD_HDR_AL_DMA_HINT_L4 = 4, 169 }; 170 171 /* Optional Metadata Completion Descriptors */ 172 #define FBNIC_RCD_OPT_META_TS_MASK DESC_GENMASK(39, 0) 173 #define FBNIC_RCD_OPT_META_ACTION_MASK DESC_GENMASK(45, 40) 174 #define FBNIC_RCD_OPT_META_ACTION DESC_BIT(57) 175 #define FBNIC_RCD_OPT_META_TS DESC_BIT(58) 176 #define FBNIC_RCD_OPT_META_TYPE_MASK DESC_GENMASK(60, 59) 177 178 /* Metadata Completion Descriptors */ 179 #define FBNIC_RCD_META_RSS_HASH_MASK DESC_GENMASK(31, 0) 180 #define FBNIC_RCD_META_L2_CSUM_MASK DESC_GENMASK(47, 32) 181 #define FBNIC_RCD_META_L3_TYPE_MASK DESC_GENMASK(49, 48) 182 enum { 183 FBNIC_RCD_META_L3_TYPE_OTHER = 0, 184 FBNIC_RCD_META_L3_TYPE_IPV4 = 1, 185 FBNIC_RCD_META_L3_TYPE_IPV6 = 2, 186 FBNIC_RCD_META_L3_TYPE_V6V6 = 3, 187 }; 188 189 #define FBNIC_RCD_META_L4_TYPE_MASK DESC_GENMASK(51, 50) 190 enum { 191 FBNIC_RCD_META_L4_TYPE_OTHER = 0, 192 FBNIC_RCD_META_L4_TYPE_TCP = 1, 193 FBNIC_RCD_META_L4_TYPE_UDP = 2, 194 }; 195 196 #define FBNIC_RCD_META_L4_CSUM_UNNECESSARY DESC_BIT(52) 197 #define FBNIC_RCD_META_ERR_MAC_EOP DESC_BIT(53) 198 #define FBNIC_RCD_META_ERR_TRUNCATED_FRAME DESC_BIT(54) 199 #define FBNIC_RCD_META_ERR_PARSER DESC_BIT(55) 200 #define FBNIC_RCD_META_UNCORRECTABLE_ERR_MASK \ 201 (FBNIC_RCD_META_ERR_MAC_EOP | FBNIC_RCD_META_ERR_TRUNCATED_FRAME) 202 #define FBNIC_RCD_META_ECN DESC_BIT(60) 203 204 /* Register Definitions 205 * 206 * The registers are laid as indexes into an le32 array. As such the actual 207 * address is 4 times the index value. Below each register is defined as 3 208 * fields, name, index, and Address. 209 * 210 * Name Index Address 211 *************************************************************************/ 212 /* Interrupt Registers */ 213 #define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */ 214 #define FBNIC_INTR_STATUS(n) (0x00000 + (n)) /* 0x00000 + 4*n */ 215 #define FBNIC_INTR_STATUS_CNT 8 216 #define FBNIC_INTR_MASK(n) (0x00008 + (n)) /* 0x00020 + 4*n */ 217 #define FBNIC_INTR_MASK_CNT 8 218 #define FBNIC_INTR_SET(n) (0x00010 + (n)) /* 0x00040 + 4*n */ 219 #define FBNIC_INTR_SET_CNT 8 220 #define FBNIC_INTR_CLEAR(n) (0x00018 + (n)) /* 0x00060 + 4*n */ 221 #define FBNIC_INTR_CLEAR_CNT 8 222 #define FBNIC_INTR_SW_STATUS(n) (0x00020 + (n)) /* 0x00080 + 4*n */ 223 #define FBNIC_INTR_SW_STATUS_CNT 8 224 #define FBNIC_INTR_SW_AC_MODE(n) (0x00028 + (n)) /* 0x000a0 + 4*n */ 225 #define FBNIC_INTR_SW_AC_MODE_CNT 8 226 #define FBNIC_INTR_MASK_SET(n) (0x00030 + (n)) /* 0x000c0 + 4*n */ 227 #define FBNIC_INTR_MASK_SET_CNT 8 228 #define FBNIC_INTR_MASK_CLEAR(n) (0x00038 + (n)) /* 0x000e0 + 4*n */ 229 #define FBNIC_INTR_MASK_CLEAR_CNT 8 230 #define FBNIC_MAX_MSIX_VECS 256U 231 #define FBNIC_INTR_MSIX_CTRL(n) (0x00040 + (n)) /* 0x00100 + 4*n */ 232 #define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK CSR_GENMASK(7, 0) 233 #define FBNIC_INTR_MSIX_CTRL_ENABLE CSR_BIT(31) 234 enum { 235 FBNIC_INTR_MSIX_CTRL_RXB_IDX = 7, 236 FBNIC_INTR_MSIX_CTRL_PCS_IDX = 34, 237 }; 238 239 #define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */ 240 241 /* Interrupt MSIX Registers */ 242 #define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */ 243 #define FBNIC_INTR_CQ_REARM(n) \ 244 (0x00400 + 4 * (n)) /* 0x01000 + 16*n */ 245 #define FBNIC_INTR_CQ_REARM_CNT 256 246 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT CSR_GENMASK(13, 0) 247 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN CSR_BIT(14) 248 #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT CSR_GENMASK(28, 15) 249 #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN CSR_BIT(29) 250 #define FBNIC_INTR_CQ_REARM_INTR_RELOAD CSR_BIT(30) 251 #define FBNIC_INTR_CQ_REARM_INTR_UNMASK CSR_BIT(31) 252 253 #define FBNIC_INTR_RCQ_TIMEOUT(n) \ 254 (0x00401 + 4 * (n)) /* 0x01004 + 16*n */ 255 #define FBNIC_INTR_RCQ_TIMEOUT_CNT 256 256 #define FBNIC_INTR_TCQ_TIMEOUT(n) \ 257 (0x00402 + 4 * (n)) /* 0x01008 + 16*n */ 258 #define FBNIC_INTR_TCQ_TIMEOUT_CNT 256 259 #define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */ 260 261 /* Global QM Tx registers */ 262 #define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */ 263 #define FBNIC_QM_TWQ_IDLE(n) (0x00800 + (n)) /* 0x02000 + 4*n */ 264 #define FBNIC_QM_TWQ_IDLE_CNT 8 265 #define FBNIC_QM_TWQ_DEFAULT_META_L 0x00818 /* 0x02060 */ 266 #define FBNIC_QM_TWQ_DEFAULT_META_H 0x00819 /* 0x02064 */ 267 268 #define FBNIC_QM_TQS_CTL0 0x0081b /* 0x0206c */ 269 #define FBNIC_QM_TQS_CTL0_LSO_TS_MASK CSR_BIT(0) 270 enum { 271 FBNIC_QM_TQS_CTL0_LSO_TS_FIRST = 0, 272 FBNIC_QM_TQS_CTL0_LSO_TS_LAST = 1, 273 }; 274 275 #define FBNIC_QM_TQS_CTL0_PREFETCH_THRESH CSR_GENMASK(7, 1) 276 enum { 277 FBNIC_QM_TQS_CTL0_PREFETCH_THRESH_MIN = 16, 278 }; 279 280 #define FBNIC_QM_TQS_CTL1 0x0081c /* 0x02070 */ 281 #define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS CSR_GENMASK(7, 0) 282 #define FBNIC_QM_TQS_CTL1_BULK_MAX_CREDITS CSR_GENMASK(15, 8) 283 #define FBNIC_QM_TQS_MTU_CTL0 0x0081d /* 0x02074 */ 284 #define FBNIC_QM_TQS_MTU_CTL1 0x0081e /* 0x02078 */ 285 #define FBNIC_QM_TQS_MTU_CTL1_BULK CSR_GENMASK(13, 0) 286 #define FBNIC_QM_TCQ_IDLE(n) (0x00821 + (n)) /* 0x02084 + 4*n */ 287 #define FBNIC_QM_TCQ_IDLE_CNT 4 288 #define FBNIC_QM_TCQ_CTL0 0x0082d /* 0x020b4 */ 289 #define FBNIC_QM_TCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0) 290 #define FBNIC_QM_TCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16) 291 #define FBNIC_QM_TQS_IDLE(n) (0x00830 + (n)) /* 0x020c0 + 4*n */ 292 #define FBNIC_QM_TQS_IDLE_CNT 8 293 #define FBNIC_QM_TQS_EDT_TS_RANGE 0x00849 /* 0x2124 */ 294 #define FBNIC_QM_TDE_IDLE(n) (0x00853 + (n)) /* 0x0214c + 4*n */ 295 #define FBNIC_QM_TDE_IDLE_CNT 8 296 #define FBNIC_QM_TNI_TDF_CTL 0x0086c /* 0x021b0 */ 297 #define FBNIC_QM_TNI_TDF_CTL_MRRS CSR_GENMASK(1, 0) 298 #define FBNIC_QM_TNI_TDF_CTL_CLS CSR_GENMASK(3, 2) 299 #define FBNIC_QM_TNI_TDF_CTL_MAX_OT CSR_GENMASK(11, 4) 300 #define FBNIC_QM_TNI_TDF_CTL_MAX_OB CSR_GENMASK(23, 12) 301 #define FBNIC_QM_TNI_TDE_CTL 0x0086d /* 0x021b4 */ 302 #define FBNIC_QM_TNI_TDE_CTL_MRRS CSR_GENMASK(1, 0) 303 #define FBNIC_QM_TNI_TDE_CTL_CLS CSR_GENMASK(3, 2) 304 #define FBNIC_QM_TNI_TDE_CTL_MAX_OT CSR_GENMASK(11, 4) 305 #define FBNIC_QM_TNI_TDE_CTL_MAX_OB CSR_GENMASK(24, 12) 306 #define FBNIC_QM_TNI_TDE_CTL_MRRS_1K CSR_BIT(25) 307 #define FBNIC_QM_TNI_TCM_CTL 0x0086e /* 0x021b8 */ 308 #define FBNIC_QM_TNI_TCM_CTL_MPS CSR_GENMASK(1, 0) 309 #define FBNIC_QM_TNI_TCM_CTL_CLS CSR_GENMASK(3, 2) 310 #define FBNIC_QM_TNI_TCM_CTL_MAX_OT CSR_GENMASK(11, 4) 311 #define FBNIC_QM_TNI_TCM_CTL_MAX_OB CSR_GENMASK(23, 12) 312 #define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */ 313 314 /* Global QM Rx registers */ 315 #define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */ 316 #define FBNIC_QM_RCQ_IDLE(n) (0x00c00 + (n)) /* 0x03000 + 4*n */ 317 #define FBNIC_QM_RCQ_IDLE_CNT 4 318 #define FBNIC_QM_RCQ_CTL0 0x00c0c /* 0x03030 */ 319 #define FBNIC_QM_RCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0) 320 #define FBNIC_QM_RCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16) 321 #define FBNIC_QM_HPQ_IDLE(n) (0x00c0f + (n)) /* 0x0303c + 4*n */ 322 #define FBNIC_QM_HPQ_IDLE_CNT 4 323 #define FBNIC_QM_PPQ_IDLE(n) (0x00c13 + (n)) /* 0x0304c + 4*n */ 324 #define FBNIC_QM_PPQ_IDLE_CNT 4 325 #define FBNIC_QM_RNI_RBP_CTL 0x00c2d /* 0x030b4 */ 326 #define FBNIC_QM_RNI_RBP_CTL_MRRS CSR_GENMASK(1, 0) 327 #define FBNIC_QM_RNI_RBP_CTL_CLS CSR_GENMASK(3, 2) 328 #define FBNIC_QM_RNI_RBP_CTL_MAX_OT CSR_GENMASK(11, 4) 329 #define FBNIC_QM_RNI_RBP_CTL_MAX_OB CSR_GENMASK(23, 12) 330 #define FBNIC_QM_RNI_RDE_CTL 0x00c2e /* 0x030b8 */ 331 #define FBNIC_QM_RNI_RDE_CTL_MPS CSR_GENMASK(1, 0) 332 #define FBNIC_QM_RNI_RDE_CTL_CLS CSR_GENMASK(3, 2) 333 #define FBNIC_QM_RNI_RDE_CTL_MAX_OT CSR_GENMASK(11, 4) 334 #define FBNIC_QM_RNI_RDE_CTL_MAX_OB CSR_GENMASK(23, 12) 335 #define FBNIC_QM_RNI_RCM_CTL 0x00c2f /* 0x030bc */ 336 #define FBNIC_QM_RNI_RCM_CTL_MPS CSR_GENMASK(1, 0) 337 #define FBNIC_QM_RNI_RCM_CTL_CLS CSR_GENMASK(3, 2) 338 #define FBNIC_QM_RNI_RCM_CTL_MAX_OT CSR_GENMASK(11, 4) 339 #define FBNIC_QM_RNI_RCM_CTL_MAX_OB CSR_GENMASK(23, 12) 340 #define FBNIC_CSR_END_QM_RX 0x00c34 /* CSR section delimiter */ 341 342 /* TCE registers */ 343 #define FBNIC_CSR_START_TCE 0x04000 /* CSR section delimiter */ 344 #define FBNIC_TCE_REG_BASE 0x04000 /* 0x10000 */ 345 346 #define FBNIC_TCE_LSO_CTRL 0x04000 /* 0x10000 */ 347 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST CSR_GENMASK(8, 0) 348 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_MID CSR_GENMASK(17, 9) 349 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_END CSR_GENMASK(26, 18) 350 #define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC CSR_BIT(27) 351 352 #define FBNIC_TCE_CSO_CTRL 0x04001 /* 0x10004 */ 353 #define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM CSR_BIT(0) 354 355 #define FBNIC_TCE_TXB_CTRL 0x04002 /* 0x10008 */ 356 #define FBNIC_TCE_TXB_CTRL_LOAD CSR_BIT(0) 357 #define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE CSR_BIT(1) 358 #define FBNIC_TCE_TXB_CTRL_DISABLE CSR_BIT(2) 359 360 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL 0x04003 /* 0x1000c */ 361 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0 CSR_GENMASK(7, 0) 362 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT1 CSR_GENMASK(15, 8) 363 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT2 CSR_GENMASK(23, 16) 364 365 #define FBNIC_TCE_TXB_TEI_Q0_CTRL 0x04004 /* 0x10010 */ 366 #define FBNIC_TCE_TXB_TEI_Q1_CTRL 0x04005 /* 0x10014 */ 367 #define FBNIC_TCE_TXB_MC_Q_CTRL 0x04006 /* 0x10018 */ 368 #define FBNIC_TCE_TXB_RX_TEI_Q_CTRL 0x04007 /* 0x1001c */ 369 #define FBNIC_TCE_TXB_RX_BMC_Q_CTRL 0x04008 /* 0x10020 */ 370 #define FBNIC_TCE_TXB_Q_CTRL_START CSR_GENMASK(10, 0) 371 #define FBNIC_TCE_TXB_Q_CTRL_SIZE CSR_GENMASK(22, 11) 372 373 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL 0x04009 /* 0x10024 */ 374 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0) 375 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8) 376 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL 0x0400a /* 0x10028 */ 377 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0) 378 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8) 379 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM2 CSR_GENMASK(23, 16) 380 381 #define FBNIC_TCE_TXB_CLDR_CFG 0x0400b /* 0x1002c */ 382 #define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT CSR_GENMASK(5, 0) 383 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n) (0x0400c + (n)) /* 0x10030 + 4*n */ 384 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_CNT 16 385 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 CSR_GENMASK(1, 0) 386 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_1 CSR_GENMASK(3, 2) 387 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_2 CSR_GENMASK(5, 4) 388 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_3 CSR_GENMASK(7, 6) 389 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_0 CSR_GENMASK(9, 8) 390 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_1 CSR_GENMASK(11, 10) 391 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_2 CSR_GENMASK(13, 12) 392 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_3 CSR_GENMASK(15, 14) 393 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_0 CSR_GENMASK(17, 16) 394 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_1 CSR_GENMASK(19, 18) 395 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_2 CSR_GENMASK(21, 20) 396 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_3 CSR_GENMASK(23, 22) 397 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_0 CSR_GENMASK(25, 24) 398 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_1 CSR_GENMASK(27, 26) 399 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_2 CSR_GENMASK(29, 28) 400 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_3 CSR_GENMASK(31, 30) 401 402 #define FBNIC_TCE_BMC_MAX_PKTSZ 0x0403a /* 0x100e8 */ 403 #define FBNIC_TCE_BMC_MAX_PKTSZ_TX CSR_GENMASK(13, 0) 404 #define FBNIC_TCE_BMC_MAX_PKTSZ_RX CSR_GENMASK(27, 14) 405 #define FBNIC_TCE_MC_MAX_PKTSZ 0x0403b /* 0x100ec */ 406 #define FBNIC_TCE_MC_MAX_PKTSZ_TMI CSR_GENMASK(13, 0) 407 408 #define FBNIC_TCE_SOP_PROT_CTRL 0x0403c /* 0x100f0 */ 409 #define FBNIC_TCE_SOP_PROT_CTRL_TBI CSR_GENMASK(7, 0) 410 #define FBNIC_TCE_SOP_PROT_CTRL_TTI_FRM CSR_GENMASK(14, 8) 411 #define FBNIC_TCE_SOP_PROT_CTRL_TTI_CM CSR_GENMASK(18, 15) 412 413 #define FBNIC_TCE_DROP_CTRL 0x0403d /* 0x100f4 */ 414 #define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN CSR_BIT(0) 415 #define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN CSR_BIT(1) 416 #define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN CSR_BIT(2) 417 418 #define FBNIC_TCE_TTI_CM_DROP_PKTS 0x0403e /* 0x100f8 */ 419 #define FBNIC_TCE_TTI_CM_DROP_BYTE_L 0x0403f /* 0x100fc */ 420 #define FBNIC_TCE_TTI_CM_DROP_BYTE_H 0x04040 /* 0x10100 */ 421 #define FBNIC_TCE_TTI_FRAME_DROP_PKTS 0x04041 /* 0x10104 */ 422 #define FBNIC_TCE_TTI_FRAME_DROP_BYTE_L 0x04042 /* 0x10108 */ 423 #define FBNIC_TCE_TTI_FRAME_DROP_BYTE_H 0x04043 /* 0x1010c */ 424 #define FBNIC_TCE_TBI_DROP_PKTS 0x04044 /* 0x10110 */ 425 #define FBNIC_TCE_TBI_DROP_BYTE_L 0x04045 /* 0x10114 */ 426 427 #define FBNIC_TCE_TCAM_IDX2DEST_MAP 0x0404A /* 0x10128 */ 428 #define FBNIC_TCE_TCAM_IDX2DEST_MAP_DEST_ID_0 CSR_GENMASK(3, 0) 429 enum { 430 FBNIC_TCE_TCAM_DEST_MAC = 1, 431 FBNIC_TCE_TCAM_DEST_BMC = 2, 432 FBNIC_TCE_TCAM_DEST_FW = 4, 433 }; 434 435 #define FBNIC_TCE_TXB_TX_BMC_Q_CTRL 0x0404B /* 0x1012c */ 436 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL 0x0404C /* 0x10130 */ 437 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0) 438 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8) 439 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT 0x0404D /* 0x10134 */ 440 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT \ 441 0x0404E /* 0x10138 */ 442 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT 0x0404F /* 0x1013c */ 443 #define FBNIC_CSR_END_TCE 0x04050 /* CSR section delimiter */ 444 445 /* TCE RAM registers */ 446 #define FBNIC_CSR_START_TCE_RAM 0x04200 /* CSR section delimiter */ 447 #define FBNIC_TCE_RAM_TCAM(m, n) \ 448 (0x04200 + 0x8 * (n) + (m)) /* 0x10800 + 32*n + 4*m */ 449 #define FBNIC_TCE_RAM_TCAM_MASK CSR_GENMASK(15, 0) 450 #define FBNIC_TCE_RAM_TCAM_VALUE CSR_GENMASK(31, 16) 451 #define FBNIC_TCE_RAM_TCAM3(n) (0x04218 + (n)) /* 0x010860 + 4*n */ 452 #define FBNIC_TCE_RAM_TCAM3_DEST_MASK CSR_GENMASK(5, 3) 453 #define FBNIC_TCE_RAM_TCAM3_MCQ_MASK CSR_BIT(7) 454 #define FBNIC_TCE_RAM_TCAM3_VALIDATE CSR_BIT(31) 455 #define FBNIC_CSR_END_TCE_RAM 0x0421F /* CSR section delimiter */ 456 457 /* TMI registers */ 458 #define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */ 459 #define FBNIC_TMI_SOP_PROT_CTRL 0x04400 /* 0x11000 */ 460 #define FBNIC_TMI_DROP_CTRL 0x04401 /* 0x11004 */ 461 #define FBNIC_TMI_DROP_CTRL_EN CSR_BIT(0) 462 #define FBNIC_TMI_DROP_PKTS 0x04402 /* 0x11008 */ 463 #define FBNIC_TMI_DROP_BYTE_L 0x04403 /* 0x1100c */ 464 #define FBNIC_TMI_ILLEGAL_PTP_REQS 0x04409 /* 0x11024 */ 465 #define FBNIC_TMI_GOOD_PTP_TS 0x0440a /* 0x11028 */ 466 #define FBNIC_TMI_BAD_PTP_TS 0x0440b /* 0x1102c */ 467 #define FBNIC_TMI_STAT_TX_PACKET_1519_2047_BYTES_L \ 468 0x04433 /* 0x110cc */ 469 #define FBNIC_TMI_STAT_TX_PACKET_1519_2047_BYTES_H \ 470 0x04434 /* 0x110d0 */ 471 #define FBNIC_TMI_STAT_TX_PACKET_2048_4095_BYTES_L \ 472 0x04435 /* 0x110d4 */ 473 #define FBNIC_TMI_STAT_TX_PACKET_2048_4095_BYTES_H \ 474 0x04436 /* 0x110d8 */ 475 #define FBNIC_TMI_STAT_TX_PACKET_4096_8191_BYTES_L \ 476 0x04437 /* 0x110dc */ 477 #define FBNIC_TMI_STAT_TX_PACKET_4096_8191_BYTES_H \ 478 0x04438 /* 0x110e0 */ 479 #define FBNIC_TMI_STAT_TX_PACKET_8192_9216_BYTES_L \ 480 0x04439 /* 0x110e4 */ 481 #define FBNIC_TMI_STAT_TX_PACKET_8192_9216_BYTES_H \ 482 0x0443a /* 0x110e8 */ 483 #define FBNIC_TMI_STAT_TX_PACKET_9217_MAX_BYTES_L \ 484 0x0443b /* 0x110ec */ 485 #define FBNIC_TMI_STAT_TX_PACKET_9217_MAX_BYTES_H \ 486 0x0443c /* 0x110f0 */ 487 #define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */ 488 489 /* Precision Time Protocol Registers */ 490 #define FBNIC_CSR_START_PTP 0x04800 /* CSR section delimiter */ 491 #define FBNIC_PTP_REG_BASE 0x04800 /* 0x12000 */ 492 493 #define FBNIC_PTP_CTRL 0x04800 /* 0x12000 */ 494 #define FBNIC_PTP_CTRL_EN CSR_BIT(0) 495 #define FBNIC_PTP_CTRL_MONO_EN CSR_BIT(4) 496 #define FBNIC_PTP_CTRL_TQS_OUT_EN CSR_BIT(8) 497 #define FBNIC_PTP_CTRL_MAC_OUT_IVAL CSR_GENMASK(16, 12) 498 #define FBNIC_PTP_CTRL_TICK_IVAL CSR_GENMASK(23, 20) 499 500 #define FBNIC_PTP_ADJUST 0x04801 /* 0x12004 */ 501 #define FBNIC_PTP_ADJUST_INIT CSR_BIT(0) 502 #define FBNIC_PTP_ADJUST_SUB_NUDGE CSR_BIT(8) 503 #define FBNIC_PTP_ADJUST_ADD_NUDGE CSR_BIT(16) 504 #define FBNIC_PTP_ADJUST_ADDEND_SET CSR_BIT(24) 505 506 #define FBNIC_PTP_INIT_HI 0x04802 /* 0x12008 */ 507 #define FBNIC_PTP_INIT_LO 0x04803 /* 0x1200c */ 508 509 #define FBNIC_PTP_NUDGE_NS 0x04804 /* 0x12010 */ 510 #define FBNIC_PTP_NUDGE_SUBNS 0x04805 /* 0x12014 */ 511 512 #define FBNIC_PTP_ADD_VAL_NS 0x04806 /* 0x12018 */ 513 #define FBNIC_PTP_ADD_VAL_NS_MASK CSR_GENMASK(15, 0) 514 #define FBNIC_PTP_ADD_VAL_SUBNS 0x04807 /* 0x1201c */ 515 516 #define FBNIC_PTP_CTR_VAL_HI 0x04808 /* 0x12020 */ 517 #define FBNIC_PTP_CTR_VAL_LO 0x04809 /* 0x12024 */ 518 519 #define FBNIC_PTP_MONO_PTP_CTR_HI 0x0480a /* 0x12028 */ 520 #define FBNIC_PTP_MONO_PTP_CTR_LO 0x0480b /* 0x1202c */ 521 522 #define FBNIC_PTP_CDC_FIFO_STATUS 0x0480c /* 0x12030 */ 523 #define FBNIC_PTP_SPARE 0x0480d /* 0x12034 */ 524 #define FBNIC_CSR_END_PTP 0x0480d /* CSR section delimiter */ 525 526 /* Rx Buffer Registers */ 527 #define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */ 528 enum { 529 FBNIC_RXB_FIFO_MC = 0, 530 /* Unused */ 531 /* Unused */ 532 FBNIC_RXB_FIFO_NET_TO_BMC = 3, 533 FBNIC_RXB_FIFO_HOST = 4, 534 /* Unused */ 535 FBNIC_RXB_FIFO_BMC_TO_HOST = 6, 536 /* Unused */ 537 FBNIC_RXB_FIFO_INDICES = 8 538 }; 539 540 enum { 541 FBNIC_RXB_INTF_NET = 0, 542 FBNIC_RXB_INTF_RBT = 1, 543 /* Unused */ 544 /* Unused */ 545 FBNIC_RXB_INTF_INDICES = 4 546 }; 547 548 #define FBNIC_RXB_CT_SIZE(n) (0x08000 + (n)) /* 0x20000 + 4*n */ 549 #define FBNIC_RXB_CT_SIZE_CNT 8 550 #define FBNIC_RXB_CT_SIZE_HEADER CSR_GENMASK(5, 0) 551 #define FBNIC_RXB_CT_SIZE_PAYLOAD CSR_GENMASK(11, 6) 552 #define FBNIC_RXB_CT_SIZE_ENABLE CSR_BIT(12) 553 #define FBNIC_RXB_PAUSE_DROP_CTRL 0x08008 /* 0x20020 */ 554 #define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE CSR_GENMASK(7, 0) 555 #define FBNIC_RXB_PAUSE_DROP_CTRL_PAUSE_ENABLE CSR_GENMASK(15, 8) 556 #define FBNIC_RXB_PAUSE_DROP_CTRL_ECN_ENABLE CSR_GENMASK(23, 16) 557 #define FBNIC_RXB_PAUSE_DROP_CTRL_PS_ENABLE CSR_GENMASK(27, 24) 558 #define FBNIC_RXB_PAUSE_THLD(n) (0x08009 + (n)) /* 0x20024 + 4*n */ 559 #define FBNIC_RXB_PAUSE_THLD_CNT 8 560 #define FBNIC_RXB_PAUSE_THLD_ON CSR_GENMASK(12, 0) 561 #define FBNIC_RXB_PAUSE_THLD_OFF CSR_GENMASK(25, 13) 562 #define FBNIC_RXB_DROP_THLD(n) (0x08011 + (n)) /* 0x20044 + 4*n */ 563 #define FBNIC_RXB_DROP_THLD_CNT 8 564 #define FBNIC_RXB_DROP_THLD_ON CSR_GENMASK(12, 0) 565 #define FBNIC_RXB_DROP_THLD_OFF CSR_GENMASK(25, 13) 566 #define FBNIC_RXB_PAUSE_STORM(n) (0x08019 + (n)) /* 0x20064 + 4*n */ 567 #define FBNIC_RXB_PAUSE_STORM_CNT 4 568 #define FBNIC_RXB_PAUSE_STORM_FORCE_NORMAL CSR_BIT(20) 569 #define FBNIC_RXB_PAUSE_STORM_THLD_TIME CSR_GENMASK(19, 0) 570 #define FBNIC_RXB_PAUSE_STORM_UNIT_WR 0x0801d /* 0x20074 */ 571 #define FBNIC_RXB_ECN_THLD(n) (0x0801e + (n)) /* 0x20078 + 4*n */ 572 #define FBNIC_RXB_ECN_THLD_CNT 8 573 #define FBNIC_RXB_ECN_THLD_ON CSR_GENMASK(12, 0) 574 #define FBNIC_RXB_ECN_THLD_OFF CSR_GENMASK(25, 13) 575 #define FBNIC_RXB_PBUF_CFG(n) (0x08027 + (n)) /* 0x2009c + 4*n */ 576 #define FBNIC_RXB_PBUF_CFG_CNT 8 577 #define FBNIC_RXB_PBUF_BASE_ADDR CSR_GENMASK(12, 0) 578 #define FBNIC_RXB_PBUF_SIZE CSR_GENMASK(21, 13) 579 #define FBNIC_RXB_DWRR_RDE_WEIGHT0 0x0802f /* 0x200bc */ 580 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0 CSR_GENMASK(7, 0) 581 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM1 CSR_GENMASK(15, 8) 582 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM2 CSR_GENMASK(23, 16) 583 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM3 CSR_GENMASK(31, 24) 584 #define FBNIC_RXB_DWRR_RDE_WEIGHT1 0x08030 /* 0x200c0 */ 585 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4 CSR_GENMASK(7, 0) 586 #define FBNIC_RXB_DWRR_BMC_WEIGHT 0x08031 /* 0x200c4 */ 587 #define FBNIC_RXB_CLDR_PRIO_CFG(n) (0x8034 + (n)) /* 0x200d0 + 4*n */ 588 #define FBNIC_RXB_CLDR_PRIO_CFG_CNT 16 589 #define FBNIC_RXB_ENDIAN_FCS 0x08044 /* 0x20110 */ 590 enum { 591 /* Unused */ 592 /* Unused */ 593 FBNIC_RXB_DEQUEUE_BMC = 2, 594 FBNIC_RXB_DEQUEUE_HOST = 3, 595 FBNIC_RXB_DEQUEUE_INDICES = 4 596 }; 597 598 #define FBNIC_RXB_PBUF_CREDIT(n) (0x08047 + (n)) /* 0x2011C + 4*n */ 599 #define FBNIC_RXB_PBUF_CREDIT_CNT 8 600 #define FBNIC_RXB_PBUF_CREDIT_MASK CSR_GENMASK(13, 0) 601 #define FBNIC_RXB_INTF_CREDIT 0x0804f /* 0x2013C */ 602 #define FBNIC_RXB_INTF_CREDIT_MASK0 CSR_GENMASK(3, 0) 603 #define FBNIC_RXB_INTF_CREDIT_MASK1 CSR_GENMASK(7, 4) 604 #define FBNIC_RXB_INTF_CREDIT_MASK2 CSR_GENMASK(11, 8) 605 #define FBNIC_RXB_INTF_CREDIT_MASK3 CSR_GENMASK(15, 12) 606 607 #define FBNIC_RXB_ERR_INTR_STS 0x08050 /* 0x20140 */ 608 #define FBNIC_RXB_ERR_INTR_STS_PS CSR_GENMASK(15, 12) 609 #define FBNIC_RXB_ERR_INTR_MASK 0x08052 /* 0x20148 */ 610 #define FBNIC_RXB_PAUSE_EVENT_CNT(n) (0x08053 + (n)) /* 0x2014c + 4*n */ 611 #define FBNIC_RXB_DROP_FRMS_STS(n) (0x08057 + (n)) /* 0x2015c + 4*n */ 612 #define FBNIC_RXB_DROP_BYTES_STS_L(n) \ 613 (0x08080 + 2 * (n)) /* 0x20200 + 8*n */ 614 #define FBNIC_RXB_DROP_BYTES_STS_H(n) \ 615 (0x08081 + 2 * (n)) /* 0x20204 + 8*n */ 616 #define FBNIC_RXB_TRUN_FRMS_STS(n) (0x08091 + (n)) /* 0x20244 + 4*n */ 617 #define FBNIC_RXB_TRUN_BYTES_STS_L(n) \ 618 (0x080c0 + 2 * (n)) /* 0x20300 + 8*n */ 619 #define FBNIC_RXB_TRUN_BYTES_STS_H(n) \ 620 (0x080c1 + 2 * (n)) /* 0x20304 + 8*n */ 621 #define FBNIC_RXB_TRANS_PAUSE_STS(n) (0x080d1 + (n)) /* 0x20344 + 4*n */ 622 #define FBNIC_RXB_TRANS_DROP_STS(n) (0x080d9 + (n)) /* 0x20364 + 4*n */ 623 #define FBNIC_RXB_TRANS_ECN_STS(n) (0x080e1 + (n)) /* 0x20384 + 4*n */ 624 enum { 625 FBNIC_RXB_ENQUEUE_NET = 0, 626 FBNIC_RXB_ENQUEUE_BMC = 1, 627 /* Unused */ 628 /* Unused */ 629 FBNIC_RXB_ENQUEUE_INDICES = 4 630 }; 631 632 #define FBNIC_RXB_INTR_PS_COUNT(n) (0x080e9 + (n)) /* 0x203a4 + 4*n */ 633 #define FBNIC_RXB_DRBO_FRM_CNT_SRC(n) (0x080f9 + (n)) /* 0x203e4 + 4*n */ 634 #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_L(n) \ 635 (0x080fd + (n)) /* 0x203f4 + 4*n */ 636 #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_H(n) \ 637 (0x08101 + (n)) /* 0x20404 + 4*n */ 638 #define FBNIC_RXB_INTF_FRM_CNT_DST(n) (0x08105 + (n)) /* 0x20414 + 4*n */ 639 #define FBNIC_RXB_INTF_BYTE_CNT_DST_L(n) \ 640 (0x08109 + (n)) /* 0x20424 + 4*n */ 641 #define FBNIC_RXB_INTF_BYTE_CNT_DST_H(n) \ 642 (0x0810d + (n)) /* 0x20434 + 4*n */ 643 #define FBNIC_RXB_PBUF_FRM_CNT_DST(n) (0x08111 + (n)) /* 0x20444 + 4*n */ 644 #define FBNIC_RXB_PBUF_BYTE_CNT_DST_L(n) \ 645 (0x08115 + (n)) /* 0x20454 + 4*n */ 646 #define FBNIC_RXB_PBUF_BYTE_CNT_DST_H(n) \ 647 (0x08119 + (n)) /* 0x20464 + 4*n */ 648 649 #define FBNIC_RXB_PBUF_FIFO_LEVEL(n) (0x0811d + (n)) /* 0x20474 + 4*n */ 650 651 #define FBNIC_RXB_PAUSE_STORM_UNIT_RD 0x08125 /* 0x20494 */ 652 #define FBNIC_RXB_INTEGRITY_ERR(n) (0x0812f + (n)) /* 0x204bc + 4*n */ 653 #define FBNIC_RXB_MAC_ERR(n) (0x08133 + (n)) /* 0x204cc + 4*n */ 654 #define FBNIC_RXB_PARSER_ERR(n) (0x08137 + (n)) /* 0x204dc + 4*n */ 655 #define FBNIC_RXB_FRM_ERR(n) (0x0813b + (n)) /* 0x204ec + 4*n */ 656 657 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT 0x08143 /* 0x2050c */ 658 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT 0x08144 /* 0x20510 */ 659 #define FBNIC_CSR_END_RXB 0x081b1 /* CSR section delimiter */ 660 661 /* Rx Parser and Classifier Registers */ 662 #define FBNIC_CSR_START_RPC 0x08400 /* CSR section delimiter */ 663 #define FBNIC_RPC_RMI_CONFIG 0x08400 /* 0x21000 */ 664 #define FBNIC_RPC_RMI_CONFIG_OH_BYTES CSR_GENMASK(4, 0) 665 #define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT CSR_BIT(8) 666 #define FBNIC_RPC_RMI_CONFIG_ENABLE CSR_BIT(12) 667 #define FBNIC_RPC_RMI_CONFIG_MTU CSR_GENMASK(31, 16) 668 669 #define FBNIC_RPC_ACT_TBL0_DEFAULT 0x0840a /* 0x21028 */ 670 #define FBNIC_RPC_ACT_TBL0_DROP CSR_BIT(0) 671 #define FBNIC_RPC_ACT_TBL0_DEST_MASK CSR_GENMASK(3, 1) 672 enum { 673 FBNIC_RPC_ACT_TBL0_DEST_HOST = 1, 674 FBNIC_RPC_ACT_TBL0_DEST_BMC = 2, 675 FBNIC_RPC_ACT_TBL0_DEST_EI = 4, 676 }; 677 678 #define FBNIC_RPC_ACT_TBL0_Q_SEL CSR_BIT(4) 679 #define FBNIC_RPC_ACT_TBL0_Q_ID CSR_GENMASK(15, 8) 680 #define FBNIC_RPC_ACT_TBL0_DMA_HINT CSR_GENMASK(24, 16) 681 #define FBNIC_RPC_ACT_TBL0_TS_ENA CSR_BIT(28) 682 #define FBNIC_RPC_ACT_TBL0_ACT_TBL_IDX CSR_BIT(29) 683 #define FBNIC_RPC_ACT_TBL0_RSS_CTXT_ID CSR_BIT(30) 684 685 #define FBNIC_RPC_ACT_TBL1_DEFAULT 0x0840b /* 0x2102c */ 686 #define FBNIC_RPC_ACT_TBL1_RSS_ENA_MASK CSR_GENMASK(15, 0) 687 enum { 688 FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_SRC = 1, 689 FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_DST = 2, 690 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_SRC = 4, 691 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_DST = 8, 692 FBNIC_RPC_ACT_TBL1_RSS_ENA_L2_DA = 16, 693 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_RSS_BYTE = 32, 694 FBNIC_RPC_ACT_TBL1_RSS_ENA_IV6_FL_LBL = 64, 695 FBNIC_RPC_ACT_TBL1_RSS_ENA_OV6_FL_LBL = 128, 696 FBNIC_RPC_ACT_TBL1_RSS_ENA_DSCP = 256, 697 FBNIC_RPC_ACT_TBL1_RSS_ENA_L3_PROT = 512, 698 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_PROT = 1024, 699 }; 700 701 #define FBNIC_RPC_RSS_KEY(n) (0x0840c + (n)) /* 0x21030 + 4*n */ 702 #define FBNIC_RPC_RSS_KEY_BIT_LEN 425 703 #define FBNIC_RPC_RSS_KEY_BYTE_LEN \ 704 DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 8) 705 #define FBNIC_RPC_RSS_KEY_DWORD_LEN \ 706 DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 32) 707 #define FBNIC_RPC_RSS_KEY_LAST_IDX \ 708 (FBNIC_RPC_RSS_KEY_DWORD_LEN - 1) 709 #define FBNIC_RPC_RSS_KEY_LAST_MASK \ 710 CSR_GENMASK(31, \ 711 FBNIC_RPC_RSS_KEY_DWORD_LEN * 32 - \ 712 FBNIC_RPC_RSS_KEY_BIT_LEN) 713 714 #define FBNIC_RPC_CNTR_TCP_OPT_ERR 0x0849e /* 0x21278 */ 715 #define FBNIC_RPC_CNTR_UNKN_ETYPE 0x0849f /* 0x2127c */ 716 #define FBNIC_RPC_CNTR_IPV4_FRAG 0x084a0 /* 0x21280 */ 717 #define FBNIC_RPC_CNTR_IPV6_FRAG 0x084a1 /* 0x21284 */ 718 #define FBNIC_RPC_CNTR_IPV4_ESP 0x084a2 /* 0x21288 */ 719 #define FBNIC_RPC_CNTR_IPV6_ESP 0x084a3 /* 0x2128c */ 720 #define FBNIC_RPC_CNTR_UNKN_EXT_HDR 0x084a4 /* 0x21290 */ 721 #define FBNIC_RPC_CNTR_OUT_OF_HDR_ERR 0x084a5 /* 0x21294 */ 722 #define FBNIC_RPC_CNTR_OVR_SIZE_ERR 0x084a6 /* 0x21298 */ 723 724 #define FBNIC_RPC_TCAM_MACDA_VALIDATE 0x0852d /* 0x214b4 */ 725 #define FBNIC_RPC_STAT_RX_PACKET_1519_2047_BYTES_L \ 726 0x0855f /* 0x2157c */ 727 #define FBNIC_RPC_STAT_RX_PACKET_1519_2047_BYTES_H \ 728 0x08560 /* 0x21580 */ 729 #define FBNIC_RPC_STAT_RX_PACKET_2048_4095_BYTES_L \ 730 0x08561 /* 0x21584 */ 731 #define FBNIC_RPC_STAT_RX_PACKET_2048_4095_BYTES_H \ 732 0x08562 /* 0x21588 */ 733 #define FBNIC_RPC_STAT_RX_PACKET_4096_8191_BYTES_L \ 734 0x08563 /* 0x2158c */ 735 #define FBNIC_RPC_STAT_RX_PACKET_4096_8191_BYTES_H \ 736 0x08564 /* 0x21590 */ 737 #define FBNIC_RPC_STAT_RX_PACKET_8192_9216_BYTES_L \ 738 0x08565 /* 0x21594 */ 739 #define FBNIC_RPC_STAT_RX_PACKET_8192_9216_BYTES_H \ 740 0x08566 /* 0x21598 */ 741 #define FBNIC_RPC_STAT_RX_PACKET_9217_MAX_BYTES_L \ 742 0x08567 /* 0x2159c */ 743 #define FBNIC_RPC_STAT_RX_PACKET_9217_MAX_BYTES_H \ 744 0x08568 /* 0x215a0 */ 745 #define FBNIC_CSR_END_RPC 0x0856b /* CSR section delimiter */ 746 747 /* RPC RAM Registers */ 748 749 #define FBNIC_CSR_START_RPC_RAM 0x08800 /* CSR section delimiter */ 750 #define FBNIC_RPC_ACT_TBL0(n) (0x08800 + (n)) /* 0x22000 + 4*n */ 751 #define FBNIC_RPC_ACT_TBL1(n) (0x08840 + (n)) /* 0x22100 + 4*n */ 752 #define FBNIC_RPC_ACT_TBL_NUM_ENTRIES 64 753 754 /* TCAM Tables */ 755 #define FBNIC_RPC_TCAM_VALIDATE CSR_BIT(31) 756 757 /* 64 Action TCAM Entries, 12 registers 758 * 3 mixed, src port, dst port, 6 L4 words, and Validate 759 */ 760 #define FBNIC_RPC_TCAM_ACT(m, n) \ 761 (0x08880 + 0x40 * (n) + (m)) /* 0x22200 + 256*n + 4*m */ 762 763 #define FBNIC_RPC_TCAM_ACT_VALUE CSR_GENMASK(15, 0) 764 #define FBNIC_RPC_TCAM_ACT_MASK CSR_GENMASK(31, 16) 765 766 #define FBNIC_RPC_TCAM_MACDA(m, n) \ 767 (0x08b80 + 0x20 * (n) + (m)) /* 0x022e00 + 128*n + 4*m */ 768 #define FBNIC_RPC_TCAM_MACDA_VALUE CSR_GENMASK(15, 0) 769 #define FBNIC_RPC_TCAM_MACDA_MASK CSR_GENMASK(31, 16) 770 771 #define FBNIC_RPC_TCAM_OUTER_IPSRC(m, n)\ 772 (0x08c00 + 0x08 * (n) + (m)) /* 0x023000 + 32*n + 4*m */ 773 #define FBNIC_RPC_TCAM_IP_ADDR_VALUE CSR_GENMASK(15, 0) 774 #define FBNIC_RPC_TCAM_IP_ADDR_MASK CSR_GENMASK(31, 16) 775 776 #define FBNIC_RPC_TCAM_OUTER_IPDST(m, n)\ 777 (0x08c48 + 0x08 * (n) + (m)) /* 0x023120 + 32*n + 4*m */ 778 #define FBNIC_RPC_TCAM_IPSRC(m, n)\ 779 (0x08c90 + 0x08 * (n) + (m)) /* 0x023240 + 32*n + 4*m */ 780 #define FBNIC_RPC_TCAM_IPDST(m, n)\ 781 (0x08cd8 + 0x08 * (n) + (m)) /* 0x023360 + 32*n + 4*m */ 782 783 #define FBNIC_RPC_RSS_TBL(n, m) \ 784 (0x08d20 + 0x100 * (n) + (m)) /* 0x023480 + 1024*n + 4*m */ 785 #define FBNIC_RPC_RSS_TBL_COUNT 2 786 #define FBNIC_RPC_RSS_TBL_SIZE 256 787 #define FBNIC_CSR_END_RPC_RAM 0x08f1f /* CSR section delimiter */ 788 789 /* Fab Registers */ 790 #define FBNIC_CSR_START_FAB 0x0C000 /* CSR section delimiter */ 791 #define FBNIC_FAB_AXI4_AR_SPACER_2_CFG 0x0C005 /* 0x30014 */ 792 #define FBNIC_FAB_AXI4_AR_SPACER_MASK CSR_BIT(16) 793 #define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD CSR_GENMASK(15, 0) 794 #define FBNIC_CSR_END_FAB 0x0C020 /* CSR section delimiter */ 795 796 /* Master Registers */ 797 #define FBNIC_CSR_START_MASTER 0x0C400 /* CSR section delimiter */ 798 #define FBNIC_MASTER_SPARE_0 0x0C41B /* 0x3106c */ 799 #define FBNIC_CSR_END_MASTER 0x0C452 /* CSR section delimiter */ 800 801 /* MAC PCS registers */ 802 #define FBNIC_CSR_START_PCS 0x10000 /* CSR section delimiter */ 803 #define FBNIC_PCS_PAGE(n) (0x10000 + 0x400 * (n)) /* 0x40000 + 1024*n */ 804 #define FBNIC_PCS(reg, n) ((reg) + FBNIC_PCS_PAGE(n)) 805 #define FBNIC_CSR_END_PCS 0x10668 /* CSR section delimiter */ 806 807 #define FBNIC_CSR_START_RSFEC 0x10800 /* CSR section delimiter */ 808 #define FBNIC_RSFEC_CONTROL(n) (0x10800 + 8 * (n)) /* 0x42000 + 32*n */ 809 810 /* We have 4 RSFEC engines present in our part, however we are only using 1. 811 * As such only CCW(0) and NCCW(0) will never be non-zero and the other 812 * registers can be ignored. 813 */ 814 #define FBNIC_RSFEC_CCW_LO(n) (0x10802 + 8 * (n)) /* 0x42008 + 32*n */ 815 #define FBNIC_RSFEC_CCW_HI(n) (0x10803 + 8 * (n)) /* 0x4200c + 32*n */ 816 #define FBNIC_RSFEC_NCCW_LO(n) (0x10804 + 8 * (n)) /* 0x42010 + 32*n */ 817 #define FBNIC_RSFEC_NCCW_HI(n) (0x10805 + 8 * (n)) /* 0x42014 + 32*n */ 818 819 #define FBNIC_PCS_MAX_LANES 4 820 #define FBNIC_PCS_SYMBLERR_LO(n) \ 821 (0x10880 + 2 * (n)) /* 0x42200 + 8*n */ 822 #define FBNIC_PCS_SYMBLERR_HI(n) \ 823 (0x10881 + 2 * (n)) /* 0x42204 + 8*n */ 824 #define FBNIC_CSR_END_RSFEC 0x108c8 /* CSR section delimiter */ 825 826 /* MAC MAC registers (ASIC only) */ 827 #define FBNIC_CSR_START_MAC_MAC 0x11000 /* CSR section delimiter */ 828 #define FBNIC_MAC_COMMAND_CONFIG 0x11002 /* 0x44008 */ 829 #define FBNIC_MAC_COMMAND_CONFIG_RX_PAUSE_DIS CSR_BIT(29) 830 #define FBNIC_MAC_COMMAND_CONFIG_TX_PAUSE_DIS CSR_BIT(28) 831 #define FBNIC_MAC_COMMAND_CONFIG_FLT_HDL_DIS CSR_BIT(27) 832 #define FBNIC_MAC_COMMAND_CONFIG_TX_PAD_EN CSR_BIT(11) 833 #define FBNIC_MAC_COMMAND_CONFIG_LOOPBACK_EN CSR_BIT(10) 834 #define FBNIC_MAC_COMMAND_CONFIG_PROMISC_EN CSR_BIT(4) 835 #define FBNIC_MAC_COMMAND_CONFIG_RX_ENA CSR_BIT(1) 836 #define FBNIC_MAC_COMMAND_CONFIG_TX_ENA CSR_BIT(0) 837 #define FBNIC_MAC_CL01_PAUSE_QUANTA 0x11015 /* 0x44054 */ 838 #define FBNIC_MAC_CL01_QUANTA_THRESH 0x11019 /* 0x44064 */ 839 #define FBNIC_CSR_END_MAC_MAC 0x11028 /* CSR section delimiter */ 840 841 /* Signals from MAC, AN, PCS, and LED CSR registers (ASIC only) */ 842 #define FBNIC_CSR_START_SIG 0x11800 /* CSR section delimiter */ 843 #define FBNIC_SIG_MAC_IN0 0x11800 /* 0x46000 */ 844 #define FBNIC_SIG_MAC_IN0_RESET_FF_TX_CLK CSR_BIT(14) 845 #define FBNIC_SIG_MAC_IN0_RESET_FF_RX_CLK CSR_BIT(13) 846 #define FBNIC_SIG_MAC_IN0_RESET_TX_CLK CSR_BIT(12) 847 #define FBNIC_SIG_MAC_IN0_RESET_RX_CLK CSR_BIT(11) 848 #define FBNIC_SIG_MAC_IN0_TX_CRC CSR_BIT(8) 849 #define FBNIC_SIG_MAC_IN0_CFG_MODE128 CSR_BIT(10) 850 #define FBNIC_SIG_PCS_OUT0 0x11808 /* 0x46020 */ 851 #define FBNIC_SIG_PCS_OUT0_LINK CSR_BIT(27) 852 #define FBNIC_SIG_PCS_OUT0_BLOCK_LOCK CSR_GENMASK(24, 5) 853 #define FBNIC_SIG_PCS_OUT0_AMPS_LOCK CSR_GENMASK(4, 1) 854 #define FBNIC_SIG_PCS_OUT1 0x11809 /* 0x46024 */ 855 #define FBNIC_SIG_PCS_OUT1_FCFEC_LOCK CSR_GENMASK(11, 8) 856 #define FBNIC_SIG_PCS_INTR_STS 0x11814 /* 0x46050 */ 857 #define FBNIC_SIG_PCS_INTR_LINK_DOWN CSR_BIT(1) 858 #define FBNIC_SIG_PCS_INTR_LINK_UP CSR_BIT(0) 859 #define FBNIC_SIG_PCS_INTR_MASK 0x11816 /* 0x46058 */ 860 #define FBNIC_CSR_END_SIG 0x1184e /* CSR section delimiter */ 861 862 #define FBNIC_CSR_START_MAC_STAT 0x11a00 863 #define FBNIC_MAC_STAT_RX_XOFF_STB_L 0x11a00 /* 0x46800 */ 864 #define FBNIC_MAC_STAT_RX_XOFF_STB_H 0x11a01 /* 0x46804 */ 865 #define FBNIC_MAC_STAT_TX_XOFF_STB_L 0x11a04 /* 0x46810 */ 866 #define FBNIC_MAC_STAT_TX_XOFF_STB_H 0x11a05 /* 0x46814 */ 867 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_L 0x11a08 /* 0x46820 */ 868 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_H 0x11a09 /* 0x46824 */ 869 #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_L 0x11a0a /* 0x46828 */ 870 #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_H 0x11a0b /* 0x4682c */ 871 #define FBNIC_MAC_STAT_RX_TOOLONG_L 0x11a0e /* 0x46838 */ 872 #define FBNIC_MAC_STAT_RX_TOOLONG_H 0x11a0f /* 0x4683c */ 873 #define FBNIC_MAC_STAT_RX_RECEIVED_OK_L 0x11a12 /* 0x46848 */ 874 #define FBNIC_MAC_STAT_RX_RECEIVED_OK_H 0x11a13 /* 0x4684c */ 875 #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_L \ 876 0x11a14 /* 0x46850 */ 877 #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_H \ 878 0x11a15 /* 0x46854 */ 879 #define FBNIC_MAC_STAT_RX_IFINERRORS_L 0x11a18 /* 0x46860 */ 880 #define FBNIC_MAC_STAT_RX_IFINERRORS_H 0x11a19 /* 0x46864 */ 881 #define FBNIC_MAC_STAT_RX_MULTICAST_L 0x11a1c /* 0x46870 */ 882 #define FBNIC_MAC_STAT_RX_MULTICAST_H 0x11a1d /* 0x46874 */ 883 #define FBNIC_MAC_STAT_RX_BROADCAST_L 0x11a1e /* 0x46878 */ 884 #define FBNIC_MAC_STAT_RX_BROADCAST_H 0x11a1f /* 0x4687c */ 885 #define FBNIC_MAC_STAT_RX_UNDERSIZE_L 0x11a24 /* 0x46890 */ 886 #define FBNIC_MAC_STAT_RX_UNDERSIZE_H 0x11a25 /* 0x46894 */ 887 #define FBNIC_MAC_STAT_RX_PACKET_64_BYTES_L \ 888 0x11a26 /* 0x46898 */ 889 #define FBNIC_MAC_STAT_RX_PACKET_64_BYTES_H \ 890 0x11a27 /* 0x4689c */ 891 #define FBNIC_MAC_STAT_RX_PACKET_65_127_BYTES_L \ 892 0x11a28 /* 0x468a0 */ 893 #define FBNIC_MAC_STAT_RX_PACKET_65_127_BYTES_H \ 894 0x11a29 /* 0x468a4 */ 895 #define FBNIC_MAC_STAT_RX_PACKET_128_255_BYTES_L \ 896 0x11a2a /* 0x468a8 */ 897 #define FBNIC_MAC_STAT_RX_PACKET_128_255_BYTES_H \ 898 0x11a2b /* 0x468ac */ 899 #define FBNIC_MAC_STAT_RX_PACKET_256_511_BYTES_L \ 900 0x11a2c /* 0x468b0 */ 901 #define FBNIC_MAC_STAT_RX_PACKET_256_511_BYTES_H \ 902 0x11a2d /* 0x468b4 */ 903 #define FBNIC_MAC_STAT_RX_PACKET_512_1023_BYTES_L \ 904 0x11a2e /* 0x468b8 */ 905 #define FBNIC_MAC_STAT_RX_PACKET_512_1023_BYTES_H \ 906 0x11a2f /* 0x468bc */ 907 #define FBNIC_MAC_STAT_RX_PACKET_1024_1518_BYTES_L \ 908 0x11a30 /* 0x468c0 */ 909 #define FBNIC_MAC_STAT_RX_PACKET_1024_1518_BYTES_H \ 910 0x11a31 /* 0x468c4 */ 911 #define FBNIC_MAC_STAT_RX_PACKET_1519_MAX_BYTES_L \ 912 0x11a32 /* 0x468c8 */ 913 #define FBNIC_MAC_STAT_RX_PACKET_1519_MAX_BYTES_H \ 914 0x11a33 /* 0x468cc */ 915 #define FBNIC_MAC_STAT_RX_OVERSIZE_L 0x11a34 /* 0x468d0 */ 916 #define FBNIC_MAC_STAT_RX_OVERSSIZE_H 0x11a35 /* 0x468d4 */ 917 #define FBNIC_MAC_STAT_RX_JABBER_L 0x11a36 /* 0x468d8 */ 918 #define FBNIC_MAC_STAT_RX_JABBER_H 0x11a37 /* 0x468dc */ 919 #define FBNIC_MAC_STAT_RX_FRAGMENT_L 0x11a38 /* 0x468e0 */ 920 #define FBNIC_MAC_STAT_RX_FRAGMENT_H 0x11a39 /* 0x468e4 */ 921 #define FBNIC_MAC_STAT_RX_CONTROL_FRAMES_L \ 922 0x11a3c /* 0x468f0 */ 923 #define FBNIC_MAC_STAT_RX_CONTROL_FRAMES_H \ 924 0x11a3d /* 0x468f4 */ 925 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_L 0x11a3e /* 0x468f8 */ 926 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_H 0x11a3f /* 0x468fc */ 927 #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_L \ 928 0x11a42 /* 0x46908 */ 929 #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_H \ 930 0x11a43 /* 0x4690c */ 931 #define FBNIC_MAC_STAT_TX_IFOUTERRORS_L 0x11a46 /* 0x46918 */ 932 #define FBNIC_MAC_STAT_TX_IFOUTERRORS_H 0x11a47 /* 0x4691c */ 933 #define FBNIC_MAC_STAT_TX_MULTICAST_L 0x11a4a /* 0x46928 */ 934 #define FBNIC_MAC_STAT_TX_MULTICAST_H 0x11a4b /* 0x4692c */ 935 #define FBNIC_MAC_STAT_TX_BROADCAST_L 0x11a4c /* 0x46930 */ 936 #define FBNIC_MAC_STAT_TX_BROADCAST_H 0x11a4d /* 0x46934 */ 937 #define FBNIC_MAC_STAT_TX_PACKET_64_BYTES_L \ 938 0x11a4e /* 0x46938 */ 939 #define FBNIC_MAC_STAT_TX_PACKET_64_BYTES_H \ 940 0x11a4f /* 0x4693c */ 941 #define FBNIC_MAC_STAT_TX_PACKET_65_127_BYTES_L \ 942 0x11a50 /* 0x46940 */ 943 #define FBNIC_MAC_STAT_TX_PACKET_65_127_BYTES_H \ 944 0x11a51 /* 0x46944 */ 945 #define FBNIC_MAC_STAT_TX_PACKET_128_255_BYTES_L \ 946 0x11a52 /* 0x46948 */ 947 #define FBNIC_MAC_STAT_TX_PACKET_128_255_BYTES_H \ 948 0x11a53 /* 0x4694c */ 949 #define FBNIC_MAC_STAT_TX_PACKET_256_511_BYTES_L \ 950 0x11a54 /* 0x46950 */ 951 #define FBNIC_MAC_STAT_TX_PACKET_256_511_BYTES_H \ 952 0x11a55 /* 0x46954 */ 953 #define FBNIC_MAC_STAT_TX_PACKET_512_1023_BYTES_L \ 954 0x11a56 /* 0x46958 */ 955 #define FBNIC_MAC_STAT_TX_PACKET_512_1023_BYTES_H \ 956 0x11a57 /* 0x4695c */ 957 #define FBNIC_MAC_STAT_TX_PACKET_1024_1518_BYTES_L \ 958 0x11a58 /* 0x46960 */ 959 #define FBNIC_MAC_STAT_TX_PACKET_1024_1518_BYTES_H \ 960 0x11a59 /* 0x46964 */ 961 #define FBNIC_MAC_STAT_TX_PACKET_1519_MAX_BYTES_L \ 962 0x11a5a /* 0x46968 */ 963 #define FBNIC_MAC_STAT_TX_PACKET_1519_MAX_BYTES_H \ 964 0x11a5b /* 0x4696c */ 965 #define FBNIC_MAC_STAT_TX_CONTROL_FRAMES_L \ 966 0x11a5e /* 0x46978 */ 967 #define FBNIC_MAC_STAT_TX_CONTROL_FRAMES_H \ 968 0x11a5f /* 0x4697c */ 969 970 /* PCIE Comphy Registers */ 971 #define FBNIC_CSR_START_PCIE_SS_COMPHY 0x2442e /* CSR section delimiter */ 972 #define FBNIC_CSR_END_PCIE_SS_COMPHY 0x279d7 /* CSR section delimiter */ 973 974 /* PUL User Registers */ 975 #define FBNIC_CSR_START_PUL_USER 0x31000 /* CSR section delimiter */ 976 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG 0x3103d /* 0xc40f4 */ 977 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_FLUSH_MODE CSR_BIT(20) 978 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_FLUSH CSR_BIT(19) 979 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME CSR_BIT(18) 980 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_RDE_ATTR CSR_GENMASK(17, 15) 981 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_RQM_ATTR CSR_GENMASK(14, 12) 982 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_TQM_ATTR CSR_GENMASK(11, 9) 983 enum { 984 FBNIC_TLP_ATTR_NS = 1, 985 FBNIC_TLP_ATTR_RO = 2, 986 FBNIC_TLP_ATTR_IDO = 4, 987 }; 988 989 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG 0x3103e /* 0xc40f8 */ 990 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_FLUSH CSR_BIT(19) 991 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME CSR_BIT(18) 992 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_TDE_ATTR CSR_GENMASK(17, 15) 993 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_RQM_ATTR CSR_GENMASK(14, 12) 994 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_TQM_ATTR CSR_GENMASK(11, 9) 995 #define FBNIC_PUL_USER_OB_RD_TLP_CNT_31_0 \ 996 0x3106e /* 0xc41b8 */ 997 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_31_0 \ 998 0x31070 /* 0xc41c0 */ 999 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_63_32 \ 1000 0x31071 /* 0xc41c4 */ 1001 #define FBNIC_PUL_USER_OB_WR_TLP_CNT_31_0 \ 1002 0x31072 /* 0xc41c8 */ 1003 #define FBNIC_PUL_USER_OB_WR_TLP_CNT_63_32 \ 1004 0x31073 /* 0xc41cc */ 1005 #define FBNIC_PUL_USER_OB_WR_DWORD_CNT_31_0 \ 1006 0x31074 /* 0xc41d0 */ 1007 #define FBNIC_PUL_USER_OB_WR_DWORD_CNT_63_32 \ 1008 0x31075 /* 0xc41d4 */ 1009 #define FBNIC_PUL_USER_OB_CPL_TLP_CNT_31_0 \ 1010 0x31076 /* 0xc41d8 */ 1011 #define FBNIC_PUL_USER_OB_CPL_TLP_CNT_63_32 \ 1012 0x31077 /* 0xc41dc */ 1013 #define FBNIC_PUL_USER_OB_CPL_DWORD_CNT_31_0 \ 1014 0x31078 /* 0xc41e0 */ 1015 #define FBNIC_PUL_USER_OB_CPL_DWORD_CNT_63_32 \ 1016 0x31079 /* 0xc41e4 */ 1017 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_31_0 \ 1018 0x3107a /* 0xc41e8 */ 1019 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_63_32 \ 1020 0x3107b /* 0xc41ec */ 1021 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_31_0 \ 1022 0x3107c /* 0xc41f0 */ 1023 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_63_32 \ 1024 0x3107d /* 0xc41f4 */ 1025 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_31_0 \ 1026 0x3107e /* 0xc41f8 */ 1027 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_63_32 \ 1028 0x3107f /* 0xc41fc */ 1029 #define FBNIC_CSR_END_PUL_USER 0x310ea /* CSR section delimiter */ 1030 1031 /* Queue Registers 1032 * 1033 * The queue register offsets are specific for a given queue grouping. So to 1034 * find the actual register offset it is necessary to combine FBNIC_QUEUE(n) 1035 * with the register to get the actual register offset like so: 1036 * FBNIC_QUEUE_TWQ0_CTL(n) == FBNIC_QUEUE(n) + FBNIC_QUEUE_TWQ0_CTL 1037 */ 1038 #define FBNIC_CSR_START_QUEUE 0x40000 /* CSR section delimiter */ 1039 #define FBNIC_QUEUE_STRIDE 0x400 /* 0x1000 */ 1040 #define FBNIC_QUEUE(n)\ 1041 (0x40000 + FBNIC_QUEUE_STRIDE * (n)) /* 0x100000 + 4096*n */ 1042 1043 #define FBNIC_QUEUE_TWQ0_CTL 0x000 /* 0x000 */ 1044 #define FBNIC_QUEUE_TWQ1_CTL 0x001 /* 0x004 */ 1045 #define FBNIC_QUEUE_TWQ_CTL_RESET CSR_BIT(0) 1046 #define FBNIC_QUEUE_TWQ_CTL_ENABLE CSR_BIT(1) 1047 #define FBNIC_QUEUE_TWQ0_TAIL 0x002 /* 0x008 */ 1048 #define FBNIC_QUEUE_TWQ1_TAIL 0x003 /* 0x00c */ 1049 #define FBNIC_QUEUE_TWQ0_PTRS 0x004 /* 0x010 */ 1050 #define FBNIC_QUEUE_TWQ1_PTRS 0x005 /* 0x014 */ 1051 #define FBNIC_QUEUE_TWQ_PTRS_HEAD_MASK CSR_GENMASK(31, 16) 1052 1053 #define FBNIC_QUEUE_TWQ0_SIZE 0x00a /* 0x028 */ 1054 #define FBNIC_QUEUE_TWQ1_SIZE 0x00b /* 0x02c */ 1055 #define FBNIC_QUEUE_TWQ_SIZE_MASK CSR_GENMASK(3, 0) 1056 1057 #define FBNIC_QUEUE_TWQ0_BAL 0x020 /* 0x080 */ 1058 #define FBNIC_QUEUE_BAL_MASK CSR_GENMASK(31, 7) 1059 #define FBNIC_QUEUE_TWQ0_BAH 0x021 /* 0x084 */ 1060 #define FBNIC_QUEUE_TWQ1_BAL 0x022 /* 0x088 */ 1061 #define FBNIC_QUEUE_TWQ1_BAH 0x023 /* 0x08c */ 1062 1063 /* Tx Work Queue Statistics Registers */ 1064 #define FBNIC_QUEUE_TWQ0_PKT_CNT 0x062 /* 0x188 */ 1065 #define FBNIC_QUEUE_TWQ0_ERR_CNT 0x063 /* 0x18c */ 1066 #define FBNIC_QUEUE_TWQ1_PKT_CNT 0x072 /* 0x1c8 */ 1067 #define FBNIC_QUEUE_TWQ1_ERR_CNT 0x073 /* 0x1cc */ 1068 1069 /* Tx Completion Queue Registers */ 1070 #define FBNIC_QUEUE_TCQ_CTL 0x080 /* 0x200 */ 1071 #define FBNIC_QUEUE_TCQ_CTL_RESET CSR_BIT(0) 1072 #define FBNIC_QUEUE_TCQ_CTL_ENABLE CSR_BIT(1) 1073 1074 #define FBNIC_QUEUE_TCQ_HEAD 0x081 /* 0x204 */ 1075 #define FBNIC_QUEUE_TCQ_PTRS 0x082 /* 0x208 */ 1076 #define FBNIC_QUEUE_TCQ_PTRS_TAIL_MASK CSR_GENMASK(31, 16) 1077 1078 #define FBNIC_QUEUE_TCQ_SIZE 0x084 /* 0x210 */ 1079 #define FBNIC_QUEUE_TCQ_SIZE_MASK CSR_GENMASK(3, 0) 1080 1081 #define FBNIC_QUEUE_TCQ_BAL 0x0a0 /* 0x280 */ 1082 #define FBNIC_QUEUE_TCQ_BAH 0x0a1 /* 0x284 */ 1083 1084 /* Tx Interrupt Manager Registers */ 1085 #define FBNIC_QUEUE_TIM_CTL 0x0c0 /* 0x300 */ 1086 #define FBNIC_QUEUE_TIM_CTL_MSIX_MASK CSR_GENMASK(7, 0) 1087 1088 #define FBNIC_QUEUE_TIM_THRESHOLD 0x0c1 /* 0x304 */ 1089 #define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK CSR_GENMASK(14, 0) 1090 1091 #define FBNIC_QUEUE_TIM_CLEAR 0x0c2 /* 0x308 */ 1092 #define FBNIC_QUEUE_TIM_CLEAR_MASK CSR_BIT(0) 1093 #define FBNIC_QUEUE_TIM_SET 0x0c3 /* 0x30c */ 1094 #define FBNIC_QUEUE_TIM_SET_MASK CSR_BIT(0) 1095 #define FBNIC_QUEUE_TIM_MASK 0x0c4 /* 0x310 */ 1096 #define FBNIC_QUEUE_TIM_MASK_MASK CSR_BIT(0) 1097 1098 #define FBNIC_QUEUE_TIM_TIMER 0x0c5 /* 0x314 */ 1099 1100 #define FBNIC_QUEUE_TIM_COUNTS 0x0c6 /* 0x318 */ 1101 #define FBNIC_QUEUE_TIM_COUNTS_CNT1_MASK CSR_GENMASK(30, 16) 1102 #define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK CSR_GENMASK(14, 0) 1103 1104 /* Rx Completion Queue Registers */ 1105 #define FBNIC_QUEUE_RCQ_CTL 0x200 /* 0x800 */ 1106 #define FBNIC_QUEUE_RCQ_CTL_RESET CSR_BIT(0) 1107 #define FBNIC_QUEUE_RCQ_CTL_ENABLE CSR_BIT(1) 1108 1109 #define FBNIC_QUEUE_RCQ_HEAD 0x201 /* 0x804 */ 1110 #define FBNIC_QUEUE_RCQ_PTRS 0x202 /* 0x808 */ 1111 #define FBNIC_QUEUE_RCQ_PTRS_TAIL_MASK CSR_GENMASK(31, 16) 1112 #define FBNIC_QUEUE_RCQ_PTRS_HEAD_MASK CSR_GENMASK(15, 0) 1113 1114 #define FBNIC_QUEUE_RCQ_SIZE 0x204 /* 0x810 */ 1115 #define FBNIC_QUEUE_RCQ_SIZE_MASK CSR_GENMASK(3, 0) 1116 1117 #define FBNIC_QUEUE_RCQ_BAL 0x220 /* 0x880 */ 1118 #define FBNIC_QUEUE_RCQ_BAH 0x221 /* 0x884 */ 1119 1120 /* Rx Buffer Descriptor Queue Registers */ 1121 #define FBNIC_QUEUE_BDQ_CTL 0x240 /* 0x900 */ 1122 #define FBNIC_QUEUE_BDQ_CTL_RESET CSR_BIT(0) 1123 #define FBNIC_QUEUE_BDQ_CTL_ENABLE CSR_BIT(1) 1124 #define FBNIC_QUEUE_BDQ_CTL_PPQ_ENABLE CSR_BIT(30) 1125 1126 #define FBNIC_QUEUE_BDQ_HPQ_TAIL 0x241 /* 0x904 */ 1127 #define FBNIC_QUEUE_BDQ_PPQ_TAIL 0x242 /* 0x908 */ 1128 #define FBNIC_QUEUE_BDQ_HPQ_PTRS 0x243 /* 0x90c */ 1129 #define FBNIC_QUEUE_BDQ_PPQ_PTRS 0x244 /* 0x910 */ 1130 #define FBNIC_QUEUE_BDQ_PTRS_HEAD_MASK CSR_GENMASK(31, 16) 1131 #define FBNIC_QUEUE_BDQ_PTRS_TAIL_MASK CSR_GENMASK(15, 0) 1132 1133 #define FBNIC_QUEUE_BDQ_HPQ_SIZE 0x247 /* 0x91c */ 1134 #define FBNIC_QUEUE_BDQ_PPQ_SIZE 0x248 /* 0x920 */ 1135 #define FBNIC_QUEUE_BDQ_SIZE_MASK CSR_GENMASK(3, 0) 1136 1137 #define FBNIC_QUEUE_BDQ_HPQ_BAL 0x260 /* 0x980 */ 1138 #define FBNIC_QUEUE_BDQ_HPQ_BAH 0x261 /* 0x984 */ 1139 #define FBNIC_QUEUE_BDQ_PPQ_BAL 0x262 /* 0x988 */ 1140 #define FBNIC_QUEUE_BDQ_PPQ_BAH 0x263 /* 0x98c */ 1141 1142 /* Rx DMA Engine Configuration */ 1143 #define FBNIC_QUEUE_RDE_CTL0 0x2a0 /* 0xa80 */ 1144 #define FBNIC_QUEUE_RDE_CTL0_EN_HDR_SPLIT CSR_BIT(31) 1145 #define FBNIC_QUEUE_RDE_CTL0_DROP_MODE_MASK CSR_GENMASK(30, 29) 1146 enum { 1147 FBNIC_QUEUE_RDE_CTL0_DROP_IMMEDIATE = 0, 1148 FBNIC_QUEUE_RDE_CTL0_DROP_WAIT = 1, 1149 FBNIC_QUEUE_RDE_CTL0_DROP_NEVER = 2, 1150 }; 1151 1152 #define FBNIC_QUEUE_RDE_CTL0_MIN_HROOM_MASK CSR_GENMASK(28, 20) 1153 #define FBNIC_QUEUE_RDE_CTL0_MIN_TROOM_MASK CSR_GENMASK(19, 11) 1154 1155 #define FBNIC_QUEUE_RDE_CTL1 0x2a1 /* 0xa84 */ 1156 #define FBNIC_QUEUE_RDE_CTL1_MAX_HDR_MASK CSR_GENMASK(24, 12) 1157 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_OFF_MASK CSR_GENMASK(11, 9) 1158 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PG_CL_MASK CSR_GENMASK(8, 6) 1159 #define FBNIC_QUEUE_RDE_CTL1_PADLEN_MASK CSR_GENMASK(5, 2) 1160 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK CSR_GENMASK(1, 0) 1161 enum { 1162 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_NONE = 0, 1163 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_ALL = 1, 1164 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_RSS = 2, 1165 }; 1166 1167 /* Rx Per CQ Statistics Counters */ 1168 #define FBNIC_QUEUE_RDE_PKT_CNT 0x2a2 /* 0xa88 */ 1169 #define FBNIC_QUEUE_RDE_PKT_ERR_CNT 0x2a3 /* 0xa8c */ 1170 #define FBNIC_QUEUE_RDE_CQ_DROP_CNT 0x2a4 /* 0xa90 */ 1171 #define FBNIC_QUEUE_RDE_BDQ_DROP_CNT 0x2a5 /* 0xa94 */ 1172 1173 /* Rx Interrupt Manager Registers */ 1174 #define FBNIC_QUEUE_RIM_CTL 0x2c0 /* 0xb00 */ 1175 #define FBNIC_QUEUE_RIM_CTL_MSIX_MASK CSR_GENMASK(7, 0) 1176 1177 #define FBNIC_QUEUE_RIM_THRESHOLD 0x2c1 /* 0xb04 */ 1178 #define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK CSR_GENMASK(14, 0) 1179 1180 #define FBNIC_QUEUE_RIM_CLEAR 0x2c2 /* 0xb08 */ 1181 #define FBNIC_QUEUE_RIM_CLEAR_MASK CSR_BIT(0) 1182 #define FBNIC_QUEUE_RIM_SET 0x2c3 /* 0xb0c */ 1183 #define FBNIC_QUEUE_RIM_SET_MASK CSR_BIT(0) 1184 #define FBNIC_QUEUE_RIM_MASK 0x2c4 /* 0xb10 */ 1185 #define FBNIC_QUEUE_RIM_MASK_MASK CSR_BIT(0) 1186 1187 #define FBNIC_QUEUE_RIM_COAL_STATUS 0x2c5 /* 0xb14 */ 1188 #define FBNIC_QUEUE_RIM_RCD_COUNT_MASK CSR_GENMASK(30, 16) 1189 #define FBNIC_QUEUE_RIM_TIMER_MASK CSR_GENMASK(13, 0) 1190 #define FBNIC_MAX_QUEUES 128 1191 #define FBNIC_CSR_END_QUEUE (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1) 1192 1193 /* BAR 4 CSRs */ 1194 1195 /* The IPC mailbox consists of 32 mailboxes, with each mailbox consisting 1196 * of 32 4 byte registers. We will use 2 registers per descriptor so the 1197 * length of the mailbox is reduced to 16. 1198 * 1199 * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just 1200 * have to do the math and determine the offset based on the mailbox 1201 * direction and index inside that mailbox. 1202 */ 1203 #define FBNIC_IPC_MBX_DESC_LEN 16 1204 #define FBNIC_IPC_MBX(mbx_idx, desc_idx) \ 1205 ((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000) 1206 1207 /* Use first register in mailbox to flush writes */ 1208 #define FBNIC_FW_ZERO_REG FBNIC_IPC_MBX(0, 0) 1209 1210 enum { 1211 FBNIC_IPC_MBX_RX_IDX, 1212 FBNIC_IPC_MBX_TX_IDX, 1213 FBNIC_IPC_MBX_INDICES, 1214 }; 1215 1216 #define FBNIC_IPC_MBX_DESC_LEN_MASK DESC_GENMASK(63, 48) 1217 #define FBNIC_IPC_MBX_DESC_EOM DESC_BIT(46) 1218 #define FBNIC_IPC_MBX_DESC_ADDR_MASK DESC_GENMASK(45, 3) 1219 /* Set with FW_CMPL when the FW completed a descriptor without successfully 1220 * processing it (e.g. a mailbox DMA error); the completion has no valid data. 1221 */ 1222 #define FBNIC_IPC_MBX_DESC_FW_ERR DESC_BIT(2) 1223 #define FBNIC_IPC_MBX_DESC_FW_CMPL DESC_BIT(1) 1224 #define FBNIC_IPC_MBX_DESC_HOST_CMPL DESC_BIT(0) 1225 1226 /* OTP Registers 1227 * These registers are accessible via bar4 offset and are written by CMRT 1228 * on boot. For the write status, the register is broken up in half with OTP 1229 * Write Data Status occupying the top 16 bits and the ECC status occupying the 1230 * bottom 16 bits. 1231 */ 1232 #define FBNIC_NS_OTP_STATUS 0x0021d 1233 #define FBNIC_NS_OTP_WRITE_STATUS 0x0021e 1234 1235 #define FBNIC_NS_OTP_WRITE_DATA_STATUS_MASK CSR_GENMASK(31, 16) 1236 #define FBNIC_NS_OTP_WRITE_ECC_STATUS_MASK CSR_GENMASK(15, 0) 1237 1238 #define FBNIC_REGS_VERSION CSR_GENMASK(31, 16) 1239 #define FBNIC_REGS_HW_TYPE CSR_GENMASK(15, 8) 1240 enum{ 1241 FBNIC_CSR_VERSION_V1_0_ASIC = 1, 1242 }; 1243 1244 /** 1245 * enum fbnic_reg_self_test_codes - return codes from self test routines 1246 * 1247 * This is the code that is returned from the register self test 1248 * routines. 1249 * 1250 * The test either returns success or the register number 1251 * that failed during the test. 1252 * 1253 * @FBNIC_REG_TEST_SUCCESS: no errors 1254 */ 1255 enum fbnic_reg_self_test_codes { 1256 FBNIC_REG_TEST_SUCCESS = 0, 1257 }; 1258 1259 enum fbnic_reg_self_test_codes fbnic_csr_regs_test(struct fbnic_dev *fbd); 1260 1261 #endif /* _FBNIC_CSR_H_ */ 1262