1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic iSCSI HBA Driver 4 * Copyright (c) 2003-2013 QLogic Corporation 5 */ 6 #include <linux/delay.h> 7 #include <linux/io.h> 8 #include <linux/pci.h> 9 #include <linux/ratelimit.h> 10 #include "ql4_def.h" 11 #include "ql4_glbl.h" 12 #include "ql4_inline.h" 13 14 #include <linux/io-64-nonatomic-lo-hi.h> 15 16 #define TIMEOUT_100_MS 100 17 #define MASK(n) DMA_BIT_MASK(n) 18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 20 #define MS_WIN(addr) (addr & 0x0ffc0000) 21 #define QLA82XX_PCI_MN_2M (0) 22 #define QLA82XX_PCI_MS_2M (0x80000) 23 #define QLA82XX_PCI_OCM0_2M (0xc0000) 24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 25 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 32 ((off) & 0xf0000)) 33 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 static inline void __iomem * 38 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 39 { 40 if ((off < ha->first_page_group_end) && 41 (off >= ha->first_page_group_start)) 42 return (void __iomem *)(ha->nx_pcibase + off); 43 44 return NULL; 45 } 46 47 static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, 48 0x410000AC, 0x410000B8, 0x410000BC }; 49 #define MAX_CRB_XFORM 60 50 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 51 static int qla4_8xxx_crb_table_initialized; 52 53 #define qla4_8xxx_crb_addr_transform(name) \ 54 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 55 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 56 static void 57 qla4_82xx_crb_addr_transform_setup(void) 58 { 59 qla4_8xxx_crb_addr_transform(XDMA); 60 qla4_8xxx_crb_addr_transform(TIMR); 61 qla4_8xxx_crb_addr_transform(SRE); 62 qla4_8xxx_crb_addr_transform(SQN3); 63 qla4_8xxx_crb_addr_transform(SQN2); 64 qla4_8xxx_crb_addr_transform(SQN1); 65 qla4_8xxx_crb_addr_transform(SQN0); 66 qla4_8xxx_crb_addr_transform(SQS3); 67 qla4_8xxx_crb_addr_transform(SQS2); 68 qla4_8xxx_crb_addr_transform(SQS1); 69 qla4_8xxx_crb_addr_transform(SQS0); 70 qla4_8xxx_crb_addr_transform(RPMX7); 71 qla4_8xxx_crb_addr_transform(RPMX6); 72 qla4_8xxx_crb_addr_transform(RPMX5); 73 qla4_8xxx_crb_addr_transform(RPMX4); 74 qla4_8xxx_crb_addr_transform(RPMX3); 75 qla4_8xxx_crb_addr_transform(RPMX2); 76 qla4_8xxx_crb_addr_transform(RPMX1); 77 qla4_8xxx_crb_addr_transform(RPMX0); 78 qla4_8xxx_crb_addr_transform(ROMUSB); 79 qla4_8xxx_crb_addr_transform(SN); 80 qla4_8xxx_crb_addr_transform(QMN); 81 qla4_8xxx_crb_addr_transform(QMS); 82 qla4_8xxx_crb_addr_transform(PGNI); 83 qla4_8xxx_crb_addr_transform(PGND); 84 qla4_8xxx_crb_addr_transform(PGN3); 85 qla4_8xxx_crb_addr_transform(PGN2); 86 qla4_8xxx_crb_addr_transform(PGN1); 87 qla4_8xxx_crb_addr_transform(PGN0); 88 qla4_8xxx_crb_addr_transform(PGSI); 89 qla4_8xxx_crb_addr_transform(PGSD); 90 qla4_8xxx_crb_addr_transform(PGS3); 91 qla4_8xxx_crb_addr_transform(PGS2); 92 qla4_8xxx_crb_addr_transform(PGS1); 93 qla4_8xxx_crb_addr_transform(PGS0); 94 qla4_8xxx_crb_addr_transform(PS); 95 qla4_8xxx_crb_addr_transform(PH); 96 qla4_8xxx_crb_addr_transform(NIU); 97 qla4_8xxx_crb_addr_transform(I2Q); 98 qla4_8xxx_crb_addr_transform(EG); 99 qla4_8xxx_crb_addr_transform(MN); 100 qla4_8xxx_crb_addr_transform(MS); 101 qla4_8xxx_crb_addr_transform(CAS2); 102 qla4_8xxx_crb_addr_transform(CAS1); 103 qla4_8xxx_crb_addr_transform(CAS0); 104 qla4_8xxx_crb_addr_transform(CAM); 105 qla4_8xxx_crb_addr_transform(C2C1); 106 qla4_8xxx_crb_addr_transform(C2C0); 107 qla4_8xxx_crb_addr_transform(SMB); 108 qla4_8xxx_crb_addr_transform(OCM0); 109 qla4_8xxx_crb_addr_transform(I2C0); 110 111 qla4_8xxx_crb_table_initialized = 1; 112 } 113 114 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 115 {{{0, 0, 0, 0} } }, /* 0: PCI */ 116 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 117 {1, 0x0110000, 0x0120000, 0x130000}, 118 {1, 0x0120000, 0x0122000, 0x124000}, 119 {1, 0x0130000, 0x0132000, 0x126000}, 120 {1, 0x0140000, 0x0142000, 0x128000}, 121 {1, 0x0150000, 0x0152000, 0x12a000}, 122 {1, 0x0160000, 0x0170000, 0x110000}, 123 {1, 0x0170000, 0x0172000, 0x12e000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {0, 0x0000000, 0x0000000, 0x000000}, 128 {0, 0x0000000, 0x0000000, 0x000000}, 129 {0, 0x0000000, 0x0000000, 0x000000}, 130 {1, 0x01e0000, 0x01e0800, 0x122000}, 131 {0, 0x0000000, 0x0000000, 0x000000} } }, 132 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 133 {{{0, 0, 0, 0} } }, /* 3: */ 134 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 135 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 136 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 137 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 138 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 154 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 170 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 186 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {0, 0x0000000, 0x0000000, 0x000000}, 198 {0, 0x0000000, 0x0000000, 0x000000}, 199 {0, 0x0000000, 0x0000000, 0x000000}, 200 {0, 0x0000000, 0x0000000, 0x000000}, 201 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 202 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 203 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 204 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 205 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 206 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 207 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 208 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 209 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 210 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 211 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 212 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 213 {{{0, 0, 0, 0} } }, /* 23: */ 214 {{{0, 0, 0, 0} } }, /* 24: */ 215 {{{0, 0, 0, 0} } }, /* 25: */ 216 {{{0, 0, 0, 0} } }, /* 26: */ 217 {{{0, 0, 0, 0} } }, /* 27: */ 218 {{{0, 0, 0, 0} } }, /* 28: */ 219 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 220 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 221 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 222 {{{0} } }, /* 32: PCI */ 223 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 224 {1, 0x2110000, 0x2120000, 0x130000}, 225 {1, 0x2120000, 0x2122000, 0x124000}, 226 {1, 0x2130000, 0x2132000, 0x126000}, 227 {1, 0x2140000, 0x2142000, 0x128000}, 228 {1, 0x2150000, 0x2152000, 0x12a000}, 229 {1, 0x2160000, 0x2170000, 0x110000}, 230 {1, 0x2170000, 0x2172000, 0x12e000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000}, 235 {0, 0x0000000, 0x0000000, 0x000000}, 236 {0, 0x0000000, 0x0000000, 0x000000}, 237 {0, 0x0000000, 0x0000000, 0x000000}, 238 {0, 0x0000000, 0x0000000, 0x000000} } }, 239 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 240 {{{0} } }, /* 35: */ 241 {{{0} } }, /* 36: */ 242 {{{0} } }, /* 37: */ 243 {{{0} } }, /* 38: */ 244 {{{0} } }, /* 39: */ 245 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 246 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 247 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 248 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 249 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 250 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 251 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 252 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 253 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 254 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 255 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 256 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 257 {{{0} } }, /* 52: */ 258 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 259 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 260 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 261 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 262 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 263 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 264 {{{0} } }, /* 59: I2C0 */ 265 {{{0} } }, /* 60: I2C1 */ 266 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 267 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 268 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 269 }; 270 271 /* 272 * top 12 bits of crb internal address (hub, agent) 273 */ 274 static unsigned qla4_82xx_crb_hub_agt[64] = { 275 0, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 279 0, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 301 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 302 0, 303 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 304 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 310 0, 311 0, 312 0, 313 0, 314 0, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 316 0, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 323 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 329 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 332 0, 333 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 334 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 335 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 336 0, 337 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 338 0, 339 }; 340 341 /* Device states */ 342 static char *qdev_state[] = { 343 "Unknown", 344 "Cold", 345 "Initializing", 346 "Ready", 347 "Need Reset", 348 "Need Quiescent", 349 "Failed", 350 "Quiescent", 351 }; 352 353 /* 354 * In: 'off' is offset from CRB space in 128M pci map 355 * Out: 'off' is 2M pci map addr 356 * side effect: lock crb window 357 */ 358 static void 359 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 360 { 361 u32 win_read; 362 363 ha->crb_win = CRB_HI(*off); 364 writel(ha->crb_win, 365 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 366 367 /* Read back value to make sure write has gone through before trying 368 * to use it. */ 369 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 370 if (win_read != ha->crb_win) { 371 DEBUG2(ql4_printk(KERN_INFO, ha, 372 "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 373 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 374 } 375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376 } 377 378 #define CRB_WIN_LOCK_TIMEOUT 100000000 379 380 /* 381 * Context: atomic 382 */ 383 static int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha) 384 { 385 int done = 0, timeout = 0; 386 387 while (!done) { 388 /* acquire semaphore3 from PCI HW block */ 389 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 390 if (done == 1) 391 break; 392 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 393 return -1; 394 395 timeout++; 396 udelay(10); 397 } 398 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 399 return 0; 400 } 401 402 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha) 403 { 404 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 405 } 406 407 void 408 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 409 __context_unsafe(/*conditional locking*/) 410 { 411 unsigned long flags = 0; 412 int rv; 413 414 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 415 416 BUG_ON(rv == -1); 417 418 if (rv == 1) { 419 write_lock_irqsave(&ha->hw_lock, flags); 420 qla4_82xx_crb_win_lock(ha); 421 qla4_82xx_pci_set_crbwindow_2M(ha, &off); 422 } 423 424 writel(data, (void __iomem *)off); 425 426 if (rv == 1) { 427 qla4_82xx_crb_win_unlock(ha); 428 write_unlock_irqrestore(&ha->hw_lock, flags); 429 } 430 } 431 432 uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) 433 __context_unsafe(/*conditional locking*/) 434 { 435 unsigned long flags = 0; 436 int rv; 437 u32 data; 438 439 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 440 441 BUG_ON(rv == -1); 442 443 if (rv == 1) { 444 write_lock_irqsave(&ha->hw_lock, flags); 445 qla4_82xx_crb_win_lock(ha); 446 qla4_82xx_pci_set_crbwindow_2M(ha, &off); 447 } 448 data = readl((void __iomem *)off); 449 450 if (rv == 1) { 451 qla4_82xx_crb_win_unlock(ha); 452 write_unlock_irqrestore(&ha->hw_lock, flags); 453 } 454 return data; 455 } 456 457 /* Minidump related functions */ 458 int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data) 459 { 460 uint32_t win_read, off_value; 461 int rval = QLA_SUCCESS; 462 463 off_value = off & 0xFFFF0000; 464 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 465 466 /* 467 * Read back value to make sure write has gone through before trying 468 * to use it. 469 */ 470 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 471 if (win_read != off_value) { 472 DEBUG2(ql4_printk(KERN_INFO, ha, 473 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 474 __func__, off_value, win_read, off)); 475 rval = QLA_ERROR; 476 } else { 477 off_value = off & 0x0000FFFF; 478 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + 479 ha->nx_pcibase)); 480 } 481 return rval; 482 } 483 484 int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data) 485 { 486 uint32_t win_read, off_value; 487 int rval = QLA_SUCCESS; 488 489 off_value = off & 0xFFFF0000; 490 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 491 492 /* Read back value to make sure write has gone through before trying 493 * to use it. 494 */ 495 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 496 if (win_read != off_value) { 497 DEBUG2(ql4_printk(KERN_INFO, ha, 498 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 499 __func__, off_value, win_read, off)); 500 rval = QLA_ERROR; 501 } else { 502 off_value = off & 0x0000FFFF; 503 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 504 ha->nx_pcibase)); 505 } 506 return rval; 507 } 508 509 #define IDC_LOCK_TIMEOUT 100000000 510 511 /** 512 * qla4_82xx_idc_lock - hw_lock 513 * @ha: pointer to adapter structure 514 * 515 * General purpose lock used to synchronize access to 516 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 517 * 518 * Context: task, can sleep 519 **/ 520 int qla4_82xx_idc_lock(struct scsi_qla_host *ha) 521 { 522 int done = 0, timeout = 0; 523 524 might_sleep(); 525 526 while (!done) { 527 /* acquire semaphore5 from PCI HW block */ 528 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 529 if (done == 1) 530 break; 531 if (timeout >= IDC_LOCK_TIMEOUT) 532 return -1; 533 534 timeout++; 535 msleep(100); 536 } 537 return 0; 538 } 539 540 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha) 541 { 542 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 543 } 544 545 int 546 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 547 { 548 struct crb_128M_2M_sub_block_map *m; 549 550 if (*off >= QLA82XX_CRB_MAX) 551 return -1; 552 553 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 554 *off = (*off - QLA82XX_PCI_CAMQM) + 555 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 556 return 0; 557 } 558 559 if (*off < QLA82XX_PCI_CRBSPACE) 560 return -1; 561 562 *off -= QLA82XX_PCI_CRBSPACE; 563 /* 564 * Try direct map 565 */ 566 567 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 568 569 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 570 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 571 return 0; 572 } 573 574 /* 575 * Not in direct map, use crb window 576 */ 577 return 1; 578 } 579 580 /* 581 * check memory access boundary. 582 * used by test agent. support ddr access only for now 583 */ 584 static unsigned long 585 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, 586 unsigned long long addr, int size) 587 { 588 if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 589 QLA8XXX_ADDR_DDR_NET_MAX) || 590 !QLA8XXX_ADDR_IN_RANGE(addr + size - 1, 591 QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) || 592 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 593 return 0; 594 } 595 return 1; 596 } 597 598 static int qla4_82xx_pci_set_window_warning_count; 599 600 static unsigned long 601 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 602 { 603 int window; 604 u32 win_read; 605 606 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 607 QLA8XXX_ADDR_DDR_NET_MAX)) { 608 /* DDR network side */ 609 window = MN_WIN(addr); 610 ha->ddr_mn_window = window; 611 qla4_82xx_wr_32(ha, ha->mn_win_crb | 612 QLA82XX_PCI_CRBSPACE, window); 613 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 614 QLA82XX_PCI_CRBSPACE); 615 if ((win_read << 17) != window) { 616 ql4_printk(KERN_WARNING, ha, 617 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 618 __func__, window, win_read); 619 } 620 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 621 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 622 QLA8XXX_ADDR_OCM0_MAX)) { 623 unsigned int temp1; 624 /* if bits 19:18&17:11 are on */ 625 if ((addr & 0x00ff800) == 0xff800) { 626 printk("%s: QM access not handled.\n", __func__); 627 addr = -1UL; 628 } 629 630 window = OCM_WIN(addr); 631 ha->ddr_mn_window = window; 632 qla4_82xx_wr_32(ha, ha->mn_win_crb | 633 QLA82XX_PCI_CRBSPACE, window); 634 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 635 QLA82XX_PCI_CRBSPACE); 636 temp1 = ((window & 0x1FF) << 7) | 637 ((window & 0x0FFFE0000) >> 17); 638 if (win_read != temp1) { 639 printk("%s: Written OCMwin (0x%x) != Read" 640 " OCMwin (0x%x)\n", __func__, temp1, win_read); 641 } 642 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 643 644 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 645 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 646 /* QDR network side */ 647 window = MS_WIN(addr); 648 ha->qdr_sn_window = window; 649 qla4_82xx_wr_32(ha, ha->ms_win_crb | 650 QLA82XX_PCI_CRBSPACE, window); 651 win_read = qla4_82xx_rd_32(ha, 652 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 653 if (win_read != window) { 654 printk("%s: Written MSwin (0x%x) != Read " 655 "MSwin (0x%x)\n", __func__, window, win_read); 656 } 657 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 658 659 } else { 660 /* 661 * peg gdb frequently accesses memory that doesn't exist, 662 * this limits the chit chat so debugging isn't slowed down. 663 */ 664 if ((qla4_82xx_pci_set_window_warning_count++ < 8) || 665 (qla4_82xx_pci_set_window_warning_count%64 == 0)) { 666 printk("%s: Warning:%s Unknown address range!\n", 667 __func__, DRIVER_NAME); 668 } 669 addr = -1UL; 670 } 671 return addr; 672 } 673 674 /* check if address is in the same windows as the previous access */ 675 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, 676 unsigned long long addr) 677 { 678 int window; 679 unsigned long long qdr_max; 680 681 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 682 683 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 684 QLA8XXX_ADDR_DDR_NET_MAX)) { 685 /* DDR network side */ 686 BUG(); /* MN access can not come here */ 687 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 688 QLA8XXX_ADDR_OCM0_MAX)) { 689 return 1; 690 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1, 691 QLA8XXX_ADDR_OCM1_MAX)) { 692 return 1; 693 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 694 qdr_max)) { 695 /* QDR network side */ 696 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; 697 if (ha->qdr_sn_window == window) 698 return 1; 699 } 700 701 return 0; 702 } 703 704 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha, 705 u64 off, void *data, int size) 706 { 707 unsigned long flags; 708 void __iomem *addr; 709 int ret = 0; 710 u64 start; 711 void __iomem *mem_ptr = NULL; 712 unsigned long mem_base; 713 unsigned long mem_page; 714 715 write_lock_irqsave(&ha->hw_lock, flags); 716 717 /* 718 * If attempting to access unknown address or straddle hw windows, 719 * do not access. 720 */ 721 start = qla4_82xx_pci_set_window(ha, off); 722 if ((start == -1UL) || 723 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 724 write_unlock_irqrestore(&ha->hw_lock, flags); 725 printk(KERN_ERR"%s out of bound pci memory access. " 726 "offset is 0x%llx\n", DRIVER_NAME, off); 727 return -1; 728 } 729 730 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 731 if (!addr) { 732 write_unlock_irqrestore(&ha->hw_lock, flags); 733 mem_base = pci_resource_start(ha->pdev, 0); 734 mem_page = start & PAGE_MASK; 735 /* Map two pages whenever user tries to access addresses in two 736 consecutive pages. 737 */ 738 if (mem_page != ((start + size - 1) & PAGE_MASK)) 739 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 740 else 741 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 742 743 if (mem_ptr == NULL) { 744 *(u8 *)data = 0; 745 return -1; 746 } 747 addr = mem_ptr; 748 addr += start & (PAGE_SIZE - 1); 749 write_lock_irqsave(&ha->hw_lock, flags); 750 } 751 752 switch (size) { 753 case 1: 754 *(u8 *)data = readb(addr); 755 break; 756 case 2: 757 *(u16 *)data = readw(addr); 758 break; 759 case 4: 760 *(u32 *)data = readl(addr); 761 break; 762 case 8: 763 *(u64 *)data = readq(addr); 764 break; 765 default: 766 ret = -1; 767 break; 768 } 769 write_unlock_irqrestore(&ha->hw_lock, flags); 770 771 if (mem_ptr) 772 iounmap(mem_ptr); 773 return ret; 774 } 775 776 static int 777 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 778 void *data, int size) 779 { 780 unsigned long flags; 781 void __iomem *addr; 782 int ret = 0; 783 u64 start; 784 void __iomem *mem_ptr = NULL; 785 unsigned long mem_base; 786 unsigned long mem_page; 787 788 write_lock_irqsave(&ha->hw_lock, flags); 789 790 /* 791 * If attempting to access unknown address or straddle hw windows, 792 * do not access. 793 */ 794 start = qla4_82xx_pci_set_window(ha, off); 795 if ((start == -1UL) || 796 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 797 write_unlock_irqrestore(&ha->hw_lock, flags); 798 printk(KERN_ERR"%s out of bound pci memory access. " 799 "offset is 0x%llx\n", DRIVER_NAME, off); 800 return -1; 801 } 802 803 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 804 if (!addr) { 805 write_unlock_irqrestore(&ha->hw_lock, flags); 806 mem_base = pci_resource_start(ha->pdev, 0); 807 mem_page = start & PAGE_MASK; 808 /* Map two pages whenever user tries to access addresses in two 809 consecutive pages. 810 */ 811 if (mem_page != ((start + size - 1) & PAGE_MASK)) 812 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 813 else 814 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 815 if (mem_ptr == NULL) 816 return -1; 817 818 addr = mem_ptr; 819 addr += start & (PAGE_SIZE - 1); 820 write_lock_irqsave(&ha->hw_lock, flags); 821 } 822 823 switch (size) { 824 case 1: 825 writeb(*(u8 *)data, addr); 826 break; 827 case 2: 828 writew(*(u16 *)data, addr); 829 break; 830 case 4: 831 writel(*(u32 *)data, addr); 832 break; 833 case 8: 834 writeq(*(u64 *)data, addr); 835 break; 836 default: 837 ret = -1; 838 break; 839 } 840 write_unlock_irqrestore(&ha->hw_lock, flags); 841 if (mem_ptr) 842 iounmap(mem_ptr); 843 return ret; 844 } 845 846 #define MTU_FUDGE_FACTOR 100 847 848 static unsigned long 849 qla4_82xx_decode_crb_addr(unsigned long addr) 850 { 851 int i; 852 unsigned long base_addr, offset, pci_base; 853 854 if (!qla4_8xxx_crb_table_initialized) 855 qla4_82xx_crb_addr_transform_setup(); 856 857 pci_base = ADDR_ERROR; 858 base_addr = addr & 0xfff00000; 859 offset = addr & 0x000fffff; 860 861 for (i = 0; i < MAX_CRB_XFORM; i++) { 862 if (crb_addr_xform[i] == base_addr) { 863 pci_base = i << 20; 864 break; 865 } 866 } 867 if (pci_base == ADDR_ERROR) 868 return pci_base; 869 else 870 return pci_base + offset; 871 } 872 873 static long rom_max_timeout = 100; 874 static long qla4_82xx_rom_lock_timeout = 100; 875 876 /* 877 * Context: task, can_sleep 878 */ 879 static int 880 qla4_82xx_rom_lock(struct scsi_qla_host *ha) 881 { 882 int done = 0, timeout = 0; 883 884 might_sleep(); 885 886 while (!done) { 887 /* acquire semaphore2 from PCI HW block */ 888 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 889 if (done == 1) 890 break; 891 if (timeout >= qla4_82xx_rom_lock_timeout) 892 return -1; 893 894 timeout++; 895 msleep(20); 896 } 897 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 898 return 0; 899 } 900 901 static void 902 qla4_82xx_rom_unlock(struct scsi_qla_host *ha) 903 { 904 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 905 } 906 907 static int 908 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha) 909 { 910 long timeout = 0; 911 long done = 0 ; 912 913 while (done == 0) { 914 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 915 done &= 2; 916 timeout++; 917 if (timeout >= rom_max_timeout) { 918 printk("%s: Timeout reached waiting for rom done", 919 DRIVER_NAME); 920 return -1; 921 } 922 } 923 return 0; 924 } 925 926 static int 927 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 928 { 929 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 930 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 931 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 932 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 933 if (qla4_82xx_wait_rom_done(ha)) { 934 printk("%s: Error waiting for rom done\n", DRIVER_NAME); 935 return -1; 936 } 937 /* reset abyte_cnt and dummy_byte_cnt */ 938 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 939 udelay(10); 940 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 941 942 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 943 return 0; 944 } 945 946 static int 947 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 948 { 949 int ret, loops = 0; 950 951 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 952 udelay(100); 953 loops++; 954 } 955 if (loops >= 50000) { 956 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n", 957 DRIVER_NAME); 958 return -1; 959 } 960 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp); 961 qla4_82xx_rom_unlock(ha); 962 return ret; 963 } 964 965 /* 966 * This routine does CRB initialize sequence 967 * to put the ISP into operational state 968 */ 969 static int 970 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 971 { 972 int addr, val; 973 int i ; 974 struct crb_addr_pair *buf; 975 unsigned long off; 976 unsigned offset, n; 977 978 /* Halt all the indiviual PEGs and other blocks of the ISP */ 979 qla4_82xx_rom_lock(ha); 980 981 /* disable all I2Q */ 982 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 983 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 984 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 985 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 986 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 987 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 988 989 /* disable all niu interrupts */ 990 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 991 /* disable xge rx/tx */ 992 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 993 /* disable xg1 rx/tx */ 994 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 995 /* disable sideband mac */ 996 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 997 /* disable ap0 mac */ 998 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 999 /* disable ap1 mac */ 1000 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1001 1002 /* halt sre */ 1003 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1004 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1005 1006 /* halt epg */ 1007 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1008 1009 /* halt timers */ 1010 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1011 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1012 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1013 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1014 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1015 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1016 1017 /* halt pegs */ 1018 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1019 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1020 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1021 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1022 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1023 msleep(5); 1024 1025 /* big hammer */ 1026 if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 1027 /* don't reset CAM block on reset */ 1028 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1029 else 1030 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1031 1032 qla4_82xx_rom_unlock(ha); 1033 1034 /* Read the signature value from the flash. 1035 * Offset 0: Contain signature (0xcafecafe) 1036 * Offset 4: Offset and number of addr/value pairs 1037 * that present in CRB initialize sequence 1038 */ 1039 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1040 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { 1041 ql4_printk(KERN_WARNING, ha, 1042 "[ERROR] Reading crb_init area: n: %08x\n", n); 1043 return -1; 1044 } 1045 1046 /* Offset in flash = lower 16 bits 1047 * Number of enteries = upper 16 bits 1048 */ 1049 offset = n & 0xffffU; 1050 n = (n >> 16) & 0xffffU; 1051 1052 /* number of addr/value pair should not exceed 1024 enteries */ 1053 if (n >= 1024) { 1054 ql4_printk(KERN_WARNING, ha, 1055 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1056 DRIVER_NAME, __func__, n); 1057 return -1; 1058 } 1059 1060 ql4_printk(KERN_INFO, ha, 1061 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1062 1063 buf = kmalloc_objs(struct crb_addr_pair, n); 1064 if (buf == NULL) { 1065 ql4_printk(KERN_WARNING, ha, 1066 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1067 return -1; 1068 } 1069 1070 for (i = 0; i < n; i++) { 1071 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1072 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1073 0) { 1074 kfree(buf); 1075 return -1; 1076 } 1077 1078 buf[i].addr = addr; 1079 buf[i].data = val; 1080 } 1081 1082 for (i = 0; i < n; i++) { 1083 /* Translate internal CRB initialization 1084 * address to PCI bus address 1085 */ 1086 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1087 QLA82XX_PCI_CRBSPACE; 1088 /* Not all CRB addr/value pair to be written, 1089 * some of them are skipped 1090 */ 1091 1092 /* skip if LS bit is set*/ 1093 if (off & 0x1) { 1094 DEBUG2(ql4_printk(KERN_WARNING, ha, 1095 "Skip CRB init replay for offset = 0x%lx\n", off)); 1096 continue; 1097 } 1098 1099 /* skipping cold reboot MAGIC */ 1100 if (off == QLA82XX_CAM_RAM(0x1fc)) 1101 continue; 1102 1103 /* do not reset PCI */ 1104 if (off == (ROMUSB_GLB + 0xbc)) 1105 continue; 1106 1107 /* skip core clock, so that firmware can increase the clock */ 1108 if (off == (ROMUSB_GLB + 0xc8)) 1109 continue; 1110 1111 /* skip the function enable register */ 1112 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1113 continue; 1114 1115 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1116 continue; 1117 1118 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1119 continue; 1120 1121 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1122 continue; 1123 1124 if (off == ADDR_ERROR) { 1125 ql4_printk(KERN_WARNING, ha, 1126 "%s: [ERROR] Unknown addr: 0x%08lx\n", 1127 DRIVER_NAME, buf[i].addr); 1128 continue; 1129 } 1130 1131 qla4_82xx_wr_32(ha, off, buf[i].data); 1132 1133 /* ISP requires much bigger delay to settle down, 1134 * else crb_window returns 0xffffffff 1135 */ 1136 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1137 msleep(1000); 1138 1139 /* ISP requires millisec delay between 1140 * successive CRB register updation 1141 */ 1142 msleep(1); 1143 } 1144 1145 kfree(buf); 1146 1147 /* Resetting the data and instruction cache */ 1148 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1149 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1150 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1151 1152 /* Clear all protocol processing engines */ 1153 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1154 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1155 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1156 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1157 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1158 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1159 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1160 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1161 1162 return 0; 1163 } 1164 1165 /** 1166 * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory 1167 * @ha: Pointer to adapter structure 1168 * @addr: Flash address to write to 1169 * @data: Data to be written 1170 * @count: word_count to be written 1171 * 1172 * Return: On success return QLA_SUCCESS 1173 * On error return QLA_ERROR 1174 **/ 1175 int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr, 1176 uint32_t *data, uint32_t count) 1177 { 1178 int i, j; 1179 uint32_t agt_ctrl; 1180 unsigned long flags; 1181 int ret_val = QLA_SUCCESS; 1182 1183 /* Only 128-bit aligned access */ 1184 if (addr & 0xF) { 1185 ret_val = QLA_ERROR; 1186 goto exit_ms_mem_write; 1187 } 1188 1189 write_lock_irqsave(&ha->hw_lock, flags); 1190 1191 /* Write address */ 1192 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0); 1193 if (ret_val == QLA_ERROR) { 1194 ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n", 1195 __func__); 1196 goto exit_ms_mem_write_unlock; 1197 } 1198 1199 for (i = 0; i < count; i++, addr += 16) { 1200 if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 1201 QLA8XXX_ADDR_QDR_NET_MAX)) || 1202 (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 1203 QLA8XXX_ADDR_DDR_NET_MAX)))) { 1204 ret_val = QLA_ERROR; 1205 goto exit_ms_mem_write_unlock; 1206 } 1207 1208 ret_val = ha->isp_ops->wr_reg_indirect(ha, 1209 MD_MIU_TEST_AGT_ADDR_LO, 1210 addr); 1211 /* Write data */ 1212 ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1213 MD_MIU_TEST_AGT_WRDATA_LO, 1214 *data++); 1215 ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1216 MD_MIU_TEST_AGT_WRDATA_HI, 1217 *data++); 1218 ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1219 MD_MIU_TEST_AGT_WRDATA_ULO, 1220 *data++); 1221 ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1222 MD_MIU_TEST_AGT_WRDATA_UHI, 1223 *data++); 1224 if (ret_val == QLA_ERROR) { 1225 ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n", 1226 __func__); 1227 goto exit_ms_mem_write_unlock; 1228 } 1229 1230 /* Check write status */ 1231 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 1232 MIU_TA_CTL_WRITE_ENABLE); 1233 ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1234 MD_MIU_TEST_AGT_CTRL, 1235 MIU_TA_CTL_WRITE_START); 1236 if (ret_val == QLA_ERROR) { 1237 ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n", 1238 __func__); 1239 goto exit_ms_mem_write_unlock; 1240 } 1241 1242 for (j = 0; j < MAX_CTL_CHECK; j++) { 1243 ret_val = ha->isp_ops->rd_reg_indirect(ha, 1244 MD_MIU_TEST_AGT_CTRL, 1245 &agt_ctrl); 1246 if (ret_val == QLA_ERROR) { 1247 ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n", 1248 __func__); 1249 goto exit_ms_mem_write_unlock; 1250 } 1251 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) 1252 break; 1253 } 1254 1255 /* Status check failed */ 1256 if (j >= MAX_CTL_CHECK) { 1257 printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n", 1258 __func__); 1259 ret_val = QLA_ERROR; 1260 goto exit_ms_mem_write_unlock; 1261 } 1262 } 1263 1264 exit_ms_mem_write_unlock: 1265 write_unlock_irqrestore(&ha->hw_lock, flags); 1266 1267 exit_ms_mem_write: 1268 return ret_val; 1269 } 1270 1271 static int 1272 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1273 { 1274 int i, rval = 0; 1275 long size = 0; 1276 long flashaddr, memaddr; 1277 u64 data; 1278 u32 high, low; 1279 1280 flashaddr = memaddr = ha->hw.flt_region_bootload; 1281 size = (image_start - flashaddr) / 8; 1282 1283 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1284 ha->host_no, __func__, flashaddr, image_start)); 1285 1286 for (i = 0; i < size; i++) { 1287 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1288 (qla4_82xx_rom_fast_read(ha, flashaddr + 4, 1289 (int *)&high))) { 1290 rval = -1; 1291 goto exit_load_from_flash; 1292 } 1293 data = ((u64)high << 32) | low ; 1294 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1295 if (rval) 1296 goto exit_load_from_flash; 1297 1298 flashaddr += 8; 1299 memaddr += 8; 1300 1301 if (i % 0x1000 == 0) 1302 msleep(1); 1303 1304 } 1305 1306 udelay(100); 1307 1308 read_lock(&ha->hw_lock); 1309 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1310 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1311 read_unlock(&ha->hw_lock); 1312 1313 exit_load_from_flash: 1314 return rval; 1315 } 1316 1317 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1318 { 1319 u32 rst; 1320 1321 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1322 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1323 printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1324 __func__); 1325 return QLA_ERROR; 1326 } 1327 1328 udelay(500); 1329 1330 /* at this point, QM is in reset. This could be a problem if there are 1331 * incoming d* transition queue messages. QM/PCIE could wedge. 1332 * To get around this, QM is brought out of reset. 1333 */ 1334 1335 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1336 /* unreset qm */ 1337 rst &= ~(1 << 28); 1338 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1339 1340 if (qla4_82xx_load_from_flash(ha, image_start)) { 1341 printk("%s: Error trying to load fw from flash!\n", __func__); 1342 return QLA_ERROR; 1343 } 1344 1345 return QLA_SUCCESS; 1346 } 1347 1348 int 1349 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, 1350 u64 off, void *data, int size) 1351 { 1352 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1353 int shift_amount; 1354 uint32_t temp; 1355 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1356 1357 /* 1358 * If not MN, go check for MS or invalid. 1359 */ 1360 1361 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1362 mem_crb = QLA82XX_CRB_QDR_NET; 1363 else { 1364 mem_crb = QLA82XX_CRB_DDR_NET; 1365 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1366 return qla4_82xx_pci_mem_read_direct(ha, 1367 off, data, size); 1368 } 1369 1370 1371 off8 = off & 0xfffffff0; 1372 off0[0] = off & 0xf; 1373 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1374 shift_amount = 4; 1375 1376 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1377 off0[1] = 0; 1378 sz[1] = size - sz[0]; 1379 1380 for (i = 0; i < loop; i++) { 1381 temp = off8 + (i << shift_amount); 1382 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1383 temp = 0; 1384 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1385 temp = MIU_TA_CTL_ENABLE; 1386 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1387 temp = MIU_TA_CTL_START_ENABLE; 1388 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1389 1390 for (j = 0; j < MAX_CTL_CHECK; j++) { 1391 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1392 if ((temp & MIU_TA_CTL_BUSY) == 0) 1393 break; 1394 } 1395 1396 if (j >= MAX_CTL_CHECK) { 1397 printk_ratelimited(KERN_ERR 1398 "%s: failed to read through agent\n", 1399 __func__); 1400 break; 1401 } 1402 1403 start = off0[i] >> 2; 1404 end = (off0[i] + sz[i] - 1) >> 2; 1405 for (k = start; k <= end; k++) { 1406 temp = qla4_82xx_rd_32(ha, 1407 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1408 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1409 } 1410 } 1411 1412 if (j >= MAX_CTL_CHECK) 1413 return -1; 1414 1415 if ((off0[0] & 7) == 0) { 1416 val = word[0]; 1417 } else { 1418 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1419 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1420 } 1421 1422 switch (size) { 1423 case 1: 1424 *(uint8_t *)data = val; 1425 break; 1426 case 2: 1427 *(uint16_t *)data = val; 1428 break; 1429 case 4: 1430 *(uint32_t *)data = val; 1431 break; 1432 case 8: 1433 *(uint64_t *)data = val; 1434 break; 1435 } 1436 return 0; 1437 } 1438 1439 int 1440 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, 1441 u64 off, void *data, int size) 1442 { 1443 int i, j, ret = 0, loop, sz[2], off0; 1444 int scale, shift_amount, startword; 1445 uint32_t temp; 1446 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1447 1448 /* 1449 * If not MN, go check for MS or invalid. 1450 */ 1451 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1452 mem_crb = QLA82XX_CRB_QDR_NET; 1453 else { 1454 mem_crb = QLA82XX_CRB_DDR_NET; 1455 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1456 return qla4_82xx_pci_mem_write_direct(ha, 1457 off, data, size); 1458 } 1459 1460 off0 = off & 0x7; 1461 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1462 sz[1] = size - sz[0]; 1463 1464 off8 = off & 0xfffffff0; 1465 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1466 shift_amount = 4; 1467 scale = 2; 1468 startword = (off & 0xf)/8; 1469 1470 for (i = 0; i < loop; i++) { 1471 if (qla4_82xx_pci_mem_read_2M(ha, off8 + 1472 (i << shift_amount), &word[i * scale], 8)) 1473 return -1; 1474 } 1475 1476 switch (size) { 1477 case 1: 1478 tmpw = *((uint8_t *)data); 1479 break; 1480 case 2: 1481 tmpw = *((uint16_t *)data); 1482 break; 1483 case 4: 1484 tmpw = *((uint32_t *)data); 1485 break; 1486 case 8: 1487 default: 1488 tmpw = *((uint64_t *)data); 1489 break; 1490 } 1491 1492 if (sz[0] == 8) 1493 word[startword] = tmpw; 1494 else { 1495 word[startword] &= 1496 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1497 word[startword] |= tmpw << (off0 * 8); 1498 } 1499 1500 if (sz[1] != 0) { 1501 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1502 word[startword+1] |= tmpw >> (sz[0] * 8); 1503 } 1504 1505 for (i = 0; i < loop; i++) { 1506 temp = off8 + (i << shift_amount); 1507 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1508 temp = 0; 1509 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1510 temp = word[i * scale] & 0xffffffff; 1511 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1512 temp = (word[i * scale] >> 32) & 0xffffffff; 1513 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1514 temp = word[i*scale + 1] & 0xffffffff; 1515 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1516 temp); 1517 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1518 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1519 temp); 1520 1521 temp = MIU_TA_CTL_WRITE_ENABLE; 1522 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1523 temp = MIU_TA_CTL_WRITE_START; 1524 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1525 1526 for (j = 0; j < MAX_CTL_CHECK; j++) { 1527 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1528 if ((temp & MIU_TA_CTL_BUSY) == 0) 1529 break; 1530 } 1531 1532 if (j >= MAX_CTL_CHECK) { 1533 if (printk_ratelimit()) 1534 ql4_printk(KERN_ERR, ha, 1535 "%s: failed to read through agent\n", 1536 __func__); 1537 ret = -1; 1538 break; 1539 } 1540 } 1541 1542 return ret; 1543 } 1544 1545 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1546 { 1547 u32 val = 0; 1548 int retries = 60; 1549 1550 if (!pegtune_val) { 1551 do { 1552 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); 1553 if ((val == PHAN_INITIALIZE_COMPLETE) || 1554 (val == PHAN_INITIALIZE_ACK)) 1555 return 0; 1556 set_current_state(TASK_UNINTERRUPTIBLE); 1557 schedule_timeout(msecs_to_jiffies(500)); 1558 1559 } while (--retries); 1560 1561 if (!retries) { 1562 pegtune_val = qla4_82xx_rd_32(ha, 1563 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1564 printk(KERN_WARNING "%s: init failed, " 1565 "pegtune_val = %x\n", __func__, pegtune_val); 1566 return -1; 1567 } 1568 } 1569 return 0; 1570 } 1571 1572 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha) 1573 { 1574 uint32_t state = 0; 1575 int loops = 0; 1576 1577 /* Window 1 call */ 1578 read_lock(&ha->hw_lock); 1579 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1580 read_unlock(&ha->hw_lock); 1581 1582 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1583 udelay(100); 1584 /* Window 1 call */ 1585 read_lock(&ha->hw_lock); 1586 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1587 read_unlock(&ha->hw_lock); 1588 1589 loops++; 1590 } 1591 1592 if (loops >= 30000) { 1593 DEBUG2(ql4_printk(KERN_INFO, ha, 1594 "Receive Peg initialization not complete: 0x%x.\n", state)); 1595 return QLA_ERROR; 1596 } 1597 1598 return QLA_SUCCESS; 1599 } 1600 1601 void 1602 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1603 { 1604 uint32_t drv_active; 1605 1606 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 1607 1608 /* 1609 * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 1610 * shift 1 by func_num to set a bit for the function. 1611 * For ISP8022, drv_active has 4 bits per function 1612 */ 1613 if (is_qla8032(ha) || is_qla8042(ha)) 1614 drv_active |= (1 << ha->func_num); 1615 else 1616 drv_active |= (1 << (ha->func_num * 4)); 1617 1618 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1619 __func__, ha->host_no, drv_active); 1620 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1621 } 1622 1623 void 1624 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1625 { 1626 uint32_t drv_active; 1627 1628 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 1629 1630 /* 1631 * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 1632 * shift 1 by func_num to set a bit for the function. 1633 * For ISP8022, drv_active has 4 bits per function 1634 */ 1635 if (is_qla8032(ha) || is_qla8042(ha)) 1636 drv_active &= ~(1 << (ha->func_num)); 1637 else 1638 drv_active &= ~(1 << (ha->func_num * 4)); 1639 1640 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1641 __func__, ha->host_no, drv_active); 1642 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1643 } 1644 1645 inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1646 { 1647 uint32_t drv_state, drv_active; 1648 int rval; 1649 1650 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 1651 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 1652 1653 /* 1654 * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 1655 * shift 1 by func_num to set a bit for the function. 1656 * For ISP8022, drv_active has 4 bits per function 1657 */ 1658 if (is_qla8032(ha) || is_qla8042(ha)) 1659 rval = drv_state & (1 << ha->func_num); 1660 else 1661 rval = drv_state & (1 << (ha->func_num * 4)); 1662 1663 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 1664 rval = 1; 1665 1666 return rval; 1667 } 1668 1669 void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1670 { 1671 uint32_t drv_state; 1672 1673 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 1674 1675 /* 1676 * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 1677 * shift 1 by func_num to set a bit for the function. 1678 * For ISP8022, drv_active has 4 bits per function 1679 */ 1680 if (is_qla8032(ha) || is_qla8042(ha)) 1681 drv_state |= (1 << ha->func_num); 1682 else 1683 drv_state |= (1 << (ha->func_num * 4)); 1684 1685 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1686 __func__, ha->host_no, drv_state); 1687 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1688 } 1689 1690 void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1691 { 1692 uint32_t drv_state; 1693 1694 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 1695 1696 /* 1697 * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 1698 * shift 1 by func_num to set a bit for the function. 1699 * For ISP8022, drv_active has 4 bits per function 1700 */ 1701 if (is_qla8032(ha) || is_qla8042(ha)) 1702 drv_state &= ~(1 << ha->func_num); 1703 else 1704 drv_state &= ~(1 << (ha->func_num * 4)); 1705 1706 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1707 __func__, ha->host_no, drv_state); 1708 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1709 } 1710 1711 static inline void 1712 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1713 { 1714 uint32_t qsnt_state; 1715 1716 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 1717 1718 /* 1719 * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 1720 * shift 1 by func_num to set a bit for the function. 1721 * For ISP8022, drv_active has 4 bits per function. 1722 */ 1723 if (is_qla8032(ha) || is_qla8042(ha)) 1724 qsnt_state |= (1 << ha->func_num); 1725 else 1726 qsnt_state |= (2 << (ha->func_num * 4)); 1727 1728 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state); 1729 } 1730 1731 1732 static int 1733 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1734 { 1735 uint16_t lnk; 1736 1737 /* scrub dma mask expansion register */ 1738 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1739 1740 /* Overwrite stale initialization register values */ 1741 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1742 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1743 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1744 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1745 1746 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) { 1747 printk("%s: Error trying to start fw!\n", __func__); 1748 return QLA_ERROR; 1749 } 1750 1751 /* Handshake with the card before we register the devices. */ 1752 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1753 printk("%s: Error during card handshake!\n", __func__); 1754 return QLA_ERROR; 1755 } 1756 1757 /* Negotiated Link width */ 1758 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 1759 ha->link_width = (lnk >> 4) & 0x3f; 1760 1761 /* Synchronize with Receive peg */ 1762 return qla4_82xx_rcvpeg_ready(ha); 1763 } 1764 1765 int qla4_82xx_try_start_fw(struct scsi_qla_host *ha) 1766 { 1767 int rval; 1768 1769 /* 1770 * FW Load priority: 1771 * 1) Operational firmware residing in flash. 1772 * 2) Fail 1773 */ 1774 1775 ql4_printk(KERN_INFO, ha, 1776 "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1777 rval = qla4_8xxx_get_flash_info(ha); 1778 if (rval != QLA_SUCCESS) 1779 return rval; 1780 1781 ql4_printk(KERN_INFO, ha, 1782 "FW: Attempting to load firmware from flash...\n"); 1783 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw); 1784 1785 if (rval != QLA_SUCCESS) { 1786 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1787 " FAILED...\n"); 1788 return rval; 1789 } 1790 1791 return rval; 1792 } 1793 1794 void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) 1795 { 1796 if (qla4_82xx_rom_lock(ha)) { 1797 /* Someone else is holding the lock. */ 1798 dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1799 } 1800 1801 /* 1802 * Either we got the lock, or someone 1803 * else died while holding it. 1804 * In either case, unlock. 1805 */ 1806 qla4_82xx_rom_unlock(ha); 1807 } 1808 1809 static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha, 1810 uint32_t addr1, uint32_t mask) 1811 { 1812 unsigned long timeout; 1813 uint32_t rval = QLA_SUCCESS; 1814 uint32_t temp; 1815 1816 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 1817 do { 1818 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 1819 if ((temp & mask) != 0) 1820 break; 1821 1822 if (time_after_eq(jiffies, timeout)) { 1823 ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n"); 1824 return QLA_ERROR; 1825 } 1826 } while (1); 1827 1828 return rval; 1829 } 1830 1831 static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1, 1832 uint32_t addr3, uint32_t mask, uint32_t addr, 1833 uint32_t *data_ptr) 1834 { 1835 int rval = QLA_SUCCESS; 1836 uint32_t temp; 1837 uint32_t data; 1838 1839 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1840 if (rval) 1841 goto exit_ipmdio_rd_reg; 1842 1843 temp = (0x40000000 | addr); 1844 ha->isp_ops->wr_reg_indirect(ha, addr1, temp); 1845 1846 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1847 if (rval) 1848 goto exit_ipmdio_rd_reg; 1849 1850 ha->isp_ops->rd_reg_indirect(ha, addr3, &data); 1851 *data_ptr = data; 1852 1853 exit_ipmdio_rd_reg: 1854 return rval; 1855 } 1856 1857 1858 static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha, 1859 uint32_t addr1, 1860 uint32_t addr2, 1861 uint32_t addr3, 1862 uint32_t mask) 1863 { 1864 unsigned long timeout; 1865 uint32_t temp; 1866 uint32_t rval = QLA_SUCCESS; 1867 1868 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 1869 do { 1870 ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp); 1871 if ((temp & 0x1) != 1) 1872 break; 1873 if (time_after_eq(jiffies, timeout)) { 1874 ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n"); 1875 return QLA_ERROR; 1876 } 1877 } while (1); 1878 1879 return rval; 1880 } 1881 1882 static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha, 1883 uint32_t addr1, uint32_t addr3, 1884 uint32_t mask, uint32_t addr, 1885 uint32_t value) 1886 { 1887 int rval = QLA_SUCCESS; 1888 1889 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1890 if (rval) 1891 goto exit_ipmdio_wr_reg; 1892 1893 ha->isp_ops->wr_reg_indirect(ha, addr3, value); 1894 ha->isp_ops->wr_reg_indirect(ha, addr1, addr); 1895 1896 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1897 if (rval) 1898 goto exit_ipmdio_wr_reg; 1899 1900 exit_ipmdio_wr_reg: 1901 return rval; 1902 } 1903 1904 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, 1905 struct qla8xxx_minidump_entry_hdr *entry_hdr, 1906 uint32_t **d_ptr) 1907 { 1908 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 1909 struct qla8xxx_minidump_entry_crb *crb_hdr; 1910 uint32_t *data_ptr = *d_ptr; 1911 1912 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1913 crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 1914 r_addr = crb_hdr->addr; 1915 r_stride = crb_hdr->crb_strd.addr_stride; 1916 loop_cnt = crb_hdr->op_count; 1917 1918 for (i = 0; i < loop_cnt; i++) { 1919 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 1920 *data_ptr++ = cpu_to_le32(r_addr); 1921 *data_ptr++ = cpu_to_le32(r_value); 1922 r_addr += r_stride; 1923 } 1924 *d_ptr = data_ptr; 1925 } 1926 1927 static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha) 1928 { 1929 int rval = QLA_SUCCESS; 1930 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 1931 uint64_t dma_base_addr = 0; 1932 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 1933 1934 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 1935 ha->fw_dump_tmplt_hdr; 1936 dma_eng_num = 1937 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 1938 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 1939 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 1940 1941 /* Read the pex-dma's command-status-and-control register. */ 1942 rval = ha->isp_ops->rd_reg_indirect(ha, 1943 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 1944 &cmd_sts_and_cntrl); 1945 1946 if (rval) 1947 return QLA_ERROR; 1948 1949 /* Check if requested pex-dma engine is available. */ 1950 if (cmd_sts_and_cntrl & BIT_31) 1951 return QLA_SUCCESS; 1952 else 1953 return QLA_ERROR; 1954 } 1955 1956 static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha, 1957 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr) 1958 { 1959 int rval = QLA_SUCCESS, wait = 0; 1960 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 1961 uint64_t dma_base_addr = 0; 1962 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 1963 1964 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 1965 ha->fw_dump_tmplt_hdr; 1966 dma_eng_num = 1967 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 1968 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 1969 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 1970 1971 rval = ha->isp_ops->wr_reg_indirect(ha, 1972 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW, 1973 m_hdr->desc_card_addr); 1974 if (rval) 1975 goto error_exit; 1976 1977 rval = ha->isp_ops->wr_reg_indirect(ha, 1978 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0); 1979 if (rval) 1980 goto error_exit; 1981 1982 rval = ha->isp_ops->wr_reg_indirect(ha, 1983 dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL, 1984 m_hdr->start_dma_cmd); 1985 if (rval) 1986 goto error_exit; 1987 1988 /* Wait for dma operation to complete. */ 1989 for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) { 1990 rval = ha->isp_ops->rd_reg_indirect(ha, 1991 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 1992 &cmd_sts_and_cntrl); 1993 if (rval) 1994 goto error_exit; 1995 1996 if ((cmd_sts_and_cntrl & BIT_1) == 0) 1997 break; 1998 else 1999 udelay(10); 2000 } 2001 2002 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ 2003 if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) { 2004 rval = QLA_ERROR; 2005 goto error_exit; 2006 } 2007 2008 error_exit: 2009 return rval; 2010 } 2011 2012 static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha, 2013 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2014 uint32_t **d_ptr) 2015 { 2016 int rval = QLA_SUCCESS; 2017 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL; 2018 uint32_t size, read_size; 2019 uint8_t *data_ptr = (uint8_t *)*d_ptr; 2020 void *rdmem_buffer = NULL; 2021 dma_addr_t rdmem_dma; 2022 struct qla4_83xx_pex_dma_descriptor dma_desc; 2023 2024 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2025 2026 rval = qla4_83xx_check_dma_engine_state(ha); 2027 if (rval != QLA_SUCCESS) { 2028 DEBUG2(ql4_printk(KERN_INFO, ha, 2029 "%s: DMA engine not available. Fallback to rdmem-read.\n", 2030 __func__)); 2031 return QLA_ERROR; 2032 } 2033 2034 m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr; 2035 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, 2036 QLA83XX_PEX_DMA_READ_SIZE, 2037 &rdmem_dma, GFP_KERNEL); 2038 if (!rdmem_buffer) { 2039 DEBUG2(ql4_printk(KERN_INFO, ha, 2040 "%s: Unable to allocate rdmem dma buffer\n", 2041 __func__)); 2042 return QLA_ERROR; 2043 } 2044 2045 /* Prepare pex-dma descriptor to be written to MS memory. */ 2046 /* dma-desc-cmd layout: 2047 * 0-3: dma-desc-cmd 0-3 2048 * 4-7: pcid function number 2049 * 8-15: dma-desc-cmd 8-15 2050 */ 2051 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); 2052 dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); 2053 dma_desc.dma_bus_addr = rdmem_dma; 2054 2055 size = 0; 2056 read_size = 0; 2057 /* 2058 * Perform rdmem operation using pex-dma. 2059 * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE. 2060 */ 2061 while (read_size < m_hdr->read_data_size) { 2062 if (m_hdr->read_data_size - read_size >= 2063 QLA83XX_PEX_DMA_READ_SIZE) 2064 size = QLA83XX_PEX_DMA_READ_SIZE; 2065 else { 2066 size = (m_hdr->read_data_size - read_size); 2067 2068 if (rdmem_buffer) 2069 dma_free_coherent(&ha->pdev->dev, 2070 QLA83XX_PEX_DMA_READ_SIZE, 2071 rdmem_buffer, rdmem_dma); 2072 2073 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size, 2074 &rdmem_dma, 2075 GFP_KERNEL); 2076 if (!rdmem_buffer) { 2077 DEBUG2(ql4_printk(KERN_INFO, ha, 2078 "%s: Unable to allocate rdmem dma buffer\n", 2079 __func__)); 2080 return QLA_ERROR; 2081 } 2082 dma_desc.dma_bus_addr = rdmem_dma; 2083 } 2084 2085 dma_desc.src_addr = m_hdr->read_addr + read_size; 2086 dma_desc.cmd.read_data_size = size; 2087 2088 /* Prepare: Write pex-dma descriptor to MS memory. */ 2089 rval = qla4_8xxx_ms_mem_write_128b(ha, 2090 (uint64_t)m_hdr->desc_card_addr, 2091 (uint32_t *)&dma_desc, 2092 (sizeof(struct qla4_83xx_pex_dma_descriptor)/16)); 2093 if (rval != QLA_SUCCESS) { 2094 ql4_printk(KERN_INFO, ha, 2095 "%s: Error writing rdmem-dma-init to MS !!!\n", 2096 __func__); 2097 goto error_exit; 2098 } 2099 2100 DEBUG2(ql4_printk(KERN_INFO, ha, 2101 "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n", 2102 __func__, size)); 2103 /* Execute: Start pex-dma operation. */ 2104 rval = qla4_83xx_start_pex_dma(ha, m_hdr); 2105 if (rval != QLA_SUCCESS) { 2106 DEBUG2(ql4_printk(KERN_INFO, ha, 2107 "scsi(%ld): start-pex-dma failed rval=0x%x\n", 2108 ha->host_no, rval)); 2109 goto error_exit; 2110 } 2111 2112 memcpy(data_ptr, rdmem_buffer, size); 2113 data_ptr += size; 2114 read_size += size; 2115 } 2116 2117 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 2118 2119 *d_ptr = (uint32_t *)data_ptr; 2120 2121 error_exit: 2122 if (rdmem_buffer) 2123 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer, 2124 rdmem_dma); 2125 2126 return rval; 2127 } 2128 2129 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, 2130 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2131 uint32_t **d_ptr) 2132 { 2133 uint32_t addr, r_addr, c_addr, t_r_addr; 2134 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2135 unsigned long p_wait, w_time, p_mask; 2136 uint32_t c_value_w, c_value_r; 2137 struct qla8xxx_minidump_entry_cache *cache_hdr; 2138 int rval = QLA_ERROR; 2139 uint32_t *data_ptr = *d_ptr; 2140 2141 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2142 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 2143 2144 loop_count = cache_hdr->op_count; 2145 r_addr = cache_hdr->read_addr; 2146 c_addr = cache_hdr->control_addr; 2147 c_value_w = cache_hdr->cache_ctrl.write_value; 2148 2149 t_r_addr = cache_hdr->tag_reg_addr; 2150 t_value = cache_hdr->addr_ctrl.init_tag_value; 2151 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2152 p_wait = cache_hdr->cache_ctrl.poll_wait; 2153 p_mask = cache_hdr->cache_ctrl.poll_mask; 2154 2155 for (i = 0; i < loop_count; i++) { 2156 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 2157 2158 if (c_value_w) 2159 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 2160 2161 if (p_mask) { 2162 w_time = jiffies + p_wait; 2163 do { 2164 ha->isp_ops->rd_reg_indirect(ha, c_addr, 2165 &c_value_r); 2166 if ((c_value_r & p_mask) == 0) { 2167 break; 2168 } else if (time_after_eq(jiffies, w_time)) { 2169 /* capturing dump failed */ 2170 return rval; 2171 } 2172 } while (1); 2173 } 2174 2175 addr = r_addr; 2176 for (k = 0; k < r_cnt; k++) { 2177 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 2178 *data_ptr++ = cpu_to_le32(r_value); 2179 addr += cache_hdr->read_ctrl.read_addr_stride; 2180 } 2181 2182 t_value += cache_hdr->addr_ctrl.tag_value_stride; 2183 } 2184 *d_ptr = data_ptr; 2185 return QLA_SUCCESS; 2186 } 2187 2188 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, 2189 struct qla8xxx_minidump_entry_hdr *entry_hdr) 2190 { 2191 struct qla8xxx_minidump_entry_crb *crb_entry; 2192 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; 2193 uint32_t crb_addr; 2194 unsigned long wtime; 2195 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2196 int i; 2197 2198 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2199 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 2200 ha->fw_dump_tmplt_hdr; 2201 crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 2202 2203 crb_addr = crb_entry->addr; 2204 for (i = 0; i < crb_entry->op_count; i++) { 2205 opcode = crb_entry->crb_ctrl.opcode; 2206 if (opcode & QLA8XXX_DBG_OPCODE_WR) { 2207 ha->isp_ops->wr_reg_indirect(ha, crb_addr, 2208 crb_entry->value_1); 2209 opcode &= ~QLA8XXX_DBG_OPCODE_WR; 2210 } 2211 if (opcode & QLA8XXX_DBG_OPCODE_RW) { 2212 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2213 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2214 opcode &= ~QLA8XXX_DBG_OPCODE_RW; 2215 } 2216 if (opcode & QLA8XXX_DBG_OPCODE_AND) { 2217 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2218 read_value &= crb_entry->value_2; 2219 opcode &= ~QLA8XXX_DBG_OPCODE_AND; 2220 if (opcode & QLA8XXX_DBG_OPCODE_OR) { 2221 read_value |= crb_entry->value_3; 2222 opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2223 } 2224 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2225 } 2226 if (opcode & QLA8XXX_DBG_OPCODE_OR) { 2227 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2228 read_value |= crb_entry->value_3; 2229 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2230 opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2231 } 2232 if (opcode & QLA8XXX_DBG_OPCODE_POLL) { 2233 poll_time = crb_entry->crb_strd.poll_timeout; 2234 wtime = jiffies + poll_time; 2235 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2236 2237 do { 2238 if ((read_value & crb_entry->value_2) == 2239 crb_entry->value_1) { 2240 break; 2241 } else if (time_after_eq(jiffies, wtime)) { 2242 /* capturing dump failed */ 2243 rval = QLA_ERROR; 2244 break; 2245 } else { 2246 ha->isp_ops->rd_reg_indirect(ha, 2247 crb_addr, &read_value); 2248 } 2249 } while (1); 2250 opcode &= ~QLA8XXX_DBG_OPCODE_POLL; 2251 } 2252 2253 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) { 2254 if (crb_entry->crb_strd.state_index_a) { 2255 index = crb_entry->crb_strd.state_index_a; 2256 addr = tmplt_hdr->saved_state_array[index]; 2257 } else { 2258 addr = crb_addr; 2259 } 2260 2261 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value); 2262 index = crb_entry->crb_ctrl.state_index_v; 2263 tmplt_hdr->saved_state_array[index] = read_value; 2264 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; 2265 } 2266 2267 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) { 2268 if (crb_entry->crb_strd.state_index_a) { 2269 index = crb_entry->crb_strd.state_index_a; 2270 addr = tmplt_hdr->saved_state_array[index]; 2271 } else { 2272 addr = crb_addr; 2273 } 2274 2275 if (crb_entry->crb_ctrl.state_index_v) { 2276 index = crb_entry->crb_ctrl.state_index_v; 2277 read_value = 2278 tmplt_hdr->saved_state_array[index]; 2279 } else { 2280 read_value = crb_entry->value_1; 2281 } 2282 2283 ha->isp_ops->wr_reg_indirect(ha, addr, read_value); 2284 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; 2285 } 2286 2287 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) { 2288 index = crb_entry->crb_ctrl.state_index_v; 2289 read_value = tmplt_hdr->saved_state_array[index]; 2290 read_value <<= crb_entry->crb_ctrl.shl; 2291 read_value >>= crb_entry->crb_ctrl.shr; 2292 if (crb_entry->value_2) 2293 read_value &= crb_entry->value_2; 2294 read_value |= crb_entry->value_3; 2295 read_value += crb_entry->value_1; 2296 tmplt_hdr->saved_state_array[index] = read_value; 2297 opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE; 2298 } 2299 crb_addr += crb_entry->crb_strd.addr_stride; 2300 } 2301 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 2302 return rval; 2303 } 2304 2305 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, 2306 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2307 uint32_t **d_ptr) 2308 { 2309 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 2310 struct qla8xxx_minidump_entry_rdocm *ocm_hdr; 2311 uint32_t *data_ptr = *d_ptr; 2312 2313 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2314 ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr; 2315 r_addr = ocm_hdr->read_addr; 2316 r_stride = ocm_hdr->read_addr_stride; 2317 loop_cnt = ocm_hdr->op_count; 2318 2319 DEBUG2(ql4_printk(KERN_INFO, ha, 2320 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 2321 __func__, r_addr, r_stride, loop_cnt)); 2322 2323 for (i = 0; i < loop_cnt; i++) { 2324 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 2325 *data_ptr++ = cpu_to_le32(r_value); 2326 r_addr += r_stride; 2327 } 2328 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", 2329 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); 2330 *d_ptr = data_ptr; 2331 } 2332 2333 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, 2334 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2335 uint32_t **d_ptr) 2336 { 2337 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 2338 struct qla8xxx_minidump_entry_mux *mux_hdr; 2339 uint32_t *data_ptr = *d_ptr; 2340 2341 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2342 mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr; 2343 r_addr = mux_hdr->read_addr; 2344 s_addr = mux_hdr->select_addr; 2345 s_stride = mux_hdr->select_value_stride; 2346 s_value = mux_hdr->select_value; 2347 loop_cnt = mux_hdr->op_count; 2348 2349 for (i = 0; i < loop_cnt; i++) { 2350 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 2351 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2352 *data_ptr++ = cpu_to_le32(s_value); 2353 *data_ptr++ = cpu_to_le32(r_value); 2354 s_value += s_stride; 2355 } 2356 *d_ptr = data_ptr; 2357 } 2358 2359 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, 2360 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2361 uint32_t **d_ptr) 2362 { 2363 uint32_t addr, r_addr, c_addr, t_r_addr; 2364 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2365 uint32_t c_value_w; 2366 struct qla8xxx_minidump_entry_cache *cache_hdr; 2367 uint32_t *data_ptr = *d_ptr; 2368 2369 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 2370 loop_count = cache_hdr->op_count; 2371 r_addr = cache_hdr->read_addr; 2372 c_addr = cache_hdr->control_addr; 2373 c_value_w = cache_hdr->cache_ctrl.write_value; 2374 2375 t_r_addr = cache_hdr->tag_reg_addr; 2376 t_value = cache_hdr->addr_ctrl.init_tag_value; 2377 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2378 2379 for (i = 0; i < loop_count; i++) { 2380 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 2381 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 2382 addr = r_addr; 2383 for (k = 0; k < r_cnt; k++) { 2384 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 2385 *data_ptr++ = cpu_to_le32(r_value); 2386 addr += cache_hdr->read_ctrl.read_addr_stride; 2387 } 2388 t_value += cache_hdr->addr_ctrl.tag_value_stride; 2389 } 2390 *d_ptr = data_ptr; 2391 } 2392 2393 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, 2394 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2395 uint32_t **d_ptr) 2396 { 2397 uint32_t s_addr, r_addr; 2398 uint32_t r_stride, r_value, r_cnt, qid = 0; 2399 uint32_t i, k, loop_cnt; 2400 struct qla8xxx_minidump_entry_queue *q_hdr; 2401 uint32_t *data_ptr = *d_ptr; 2402 2403 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2404 q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr; 2405 s_addr = q_hdr->select_addr; 2406 r_cnt = q_hdr->rd_strd.read_addr_cnt; 2407 r_stride = q_hdr->rd_strd.read_addr_stride; 2408 loop_cnt = q_hdr->op_count; 2409 2410 for (i = 0; i < loop_cnt; i++) { 2411 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid); 2412 r_addr = q_hdr->read_addr; 2413 for (k = 0; k < r_cnt; k++) { 2414 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2415 *data_ptr++ = cpu_to_le32(r_value); 2416 r_addr += r_stride; 2417 } 2418 qid += q_hdr->q_strd.queue_id_stride; 2419 } 2420 *d_ptr = data_ptr; 2421 } 2422 2423 #define MD_DIRECT_ROM_WINDOW 0x42110030 2424 #define MD_DIRECT_ROM_READ_BASE 0x42150000 2425 2426 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha, 2427 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2428 uint32_t **d_ptr) 2429 { 2430 uint32_t r_addr, r_value; 2431 uint32_t i, loop_cnt; 2432 struct qla8xxx_minidump_entry_rdrom *rom_hdr; 2433 uint32_t *data_ptr = *d_ptr; 2434 2435 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2436 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 2437 r_addr = rom_hdr->read_addr; 2438 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 2439 2440 DEBUG2(ql4_printk(KERN_INFO, ha, 2441 "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", 2442 __func__, r_addr, loop_cnt)); 2443 2444 for (i = 0; i < loop_cnt; i++) { 2445 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW, 2446 (r_addr & 0xFFFF0000)); 2447 ha->isp_ops->rd_reg_indirect(ha, 2448 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF), 2449 &r_value); 2450 *data_ptr++ = cpu_to_le32(r_value); 2451 r_addr += sizeof(uint32_t); 2452 } 2453 *d_ptr = data_ptr; 2454 } 2455 2456 #define MD_MIU_TEST_AGT_CTRL 0x41000090 2457 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 2458 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 2459 2460 static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 2461 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2462 uint32_t **d_ptr) 2463 { 2464 uint32_t r_addr, r_value, r_data; 2465 uint32_t i, j, loop_cnt; 2466 struct qla8xxx_minidump_entry_rdmem *m_hdr; 2467 unsigned long flags; 2468 uint32_t *data_ptr = *d_ptr; 2469 2470 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2471 m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr; 2472 r_addr = m_hdr->read_addr; 2473 loop_cnt = m_hdr->read_data_size/16; 2474 2475 DEBUG2(ql4_printk(KERN_INFO, ha, 2476 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2477 __func__, r_addr, m_hdr->read_data_size)); 2478 2479 if (r_addr & 0xf) { 2480 DEBUG2(ql4_printk(KERN_INFO, ha, 2481 "[%s]: Read addr 0x%x not 16 bytes aligned\n", 2482 __func__, r_addr)); 2483 return QLA_ERROR; 2484 } 2485 2486 if (m_hdr->read_data_size % 16) { 2487 DEBUG2(ql4_printk(KERN_INFO, ha, 2488 "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2489 __func__, m_hdr->read_data_size)); 2490 return QLA_ERROR; 2491 } 2492 2493 DEBUG2(ql4_printk(KERN_INFO, ha, 2494 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2495 __func__, r_addr, m_hdr->read_data_size, loop_cnt)); 2496 2497 write_lock_irqsave(&ha->hw_lock, flags); 2498 for (i = 0; i < loop_cnt; i++) { 2499 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, 2500 r_addr); 2501 r_value = 0; 2502 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 2503 r_value); 2504 r_value = MIU_TA_CTL_ENABLE; 2505 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2506 r_value = MIU_TA_CTL_START_ENABLE; 2507 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2508 2509 for (j = 0; j < MAX_CTL_CHECK; j++) { 2510 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 2511 &r_value); 2512 if ((r_value & MIU_TA_CTL_BUSY) == 0) 2513 break; 2514 } 2515 2516 if (j >= MAX_CTL_CHECK) { 2517 printk_ratelimited(KERN_ERR 2518 "%s: failed to read through agent\n", 2519 __func__); 2520 write_unlock_irqrestore(&ha->hw_lock, flags); 2521 return QLA_SUCCESS; 2522 } 2523 2524 for (j = 0; j < 4; j++) { 2525 ha->isp_ops->rd_reg_indirect(ha, 2526 MD_MIU_TEST_AGT_RDDATA[j], 2527 &r_data); 2528 *data_ptr++ = cpu_to_le32(r_data); 2529 } 2530 2531 r_addr += 16; 2532 } 2533 write_unlock_irqrestore(&ha->hw_lock, flags); 2534 2535 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", 2536 __func__, (loop_cnt * 16))); 2537 2538 *d_ptr = data_ptr; 2539 return QLA_SUCCESS; 2540 } 2541 2542 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 2543 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2544 uint32_t **d_ptr) 2545 { 2546 uint32_t *data_ptr = *d_ptr; 2547 int rval = QLA_SUCCESS; 2548 2549 rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr); 2550 if (rval != QLA_SUCCESS) 2551 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 2552 &data_ptr); 2553 *d_ptr = data_ptr; 2554 return rval; 2555 } 2556 2557 static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, 2558 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2559 int index) 2560 { 2561 entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG; 2562 DEBUG2(ql4_printk(KERN_INFO, ha, 2563 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2564 ha->host_no, index, entry_hdr->entry_type, 2565 entry_hdr->d_ctrl.entry_capture_mask)); 2566 /* If driver encounters a new entry type that it cannot process, 2567 * it should just skip the entry and adjust the total buffer size by 2568 * from subtracting the skipped bytes from it 2569 */ 2570 ha->fw_dump_skip_size += entry_hdr->entry_capture_size; 2571 } 2572 2573 /* ISP83xx functions to process new minidump entries... */ 2574 static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha, 2575 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2576 uint32_t **d_ptr) 2577 { 2578 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; 2579 uint16_t s_stride, i; 2580 uint32_t *data_ptr = *d_ptr; 2581 uint32_t rval = QLA_SUCCESS; 2582 struct qla83xx_minidump_entry_pollrd *pollrd_hdr; 2583 2584 pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr; 2585 s_addr = le32_to_cpu(pollrd_hdr->select_addr); 2586 r_addr = le32_to_cpu(pollrd_hdr->read_addr); 2587 s_value = le32_to_cpu(pollrd_hdr->select_value); 2588 s_stride = le32_to_cpu(pollrd_hdr->select_value_stride); 2589 2590 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 2591 poll_mask = le32_to_cpu(pollrd_hdr->poll_mask); 2592 2593 for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) { 2594 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 2595 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 2596 while (1) { 2597 ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value); 2598 2599 if ((r_value & poll_mask) != 0) { 2600 break; 2601 } else { 2602 msleep(1); 2603 if (--poll_wait == 0) { 2604 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 2605 __func__); 2606 rval = QLA_ERROR; 2607 goto exit_process_pollrd; 2608 } 2609 } 2610 } 2611 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2612 *data_ptr++ = cpu_to_le32(s_value); 2613 *data_ptr++ = cpu_to_le32(r_value); 2614 s_value += s_stride; 2615 } 2616 2617 *d_ptr = data_ptr; 2618 2619 exit_process_pollrd: 2620 return rval; 2621 } 2622 2623 static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha, 2624 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2625 uint32_t **d_ptr) 2626 { 2627 int loop_cnt; 2628 uint32_t addr1, addr2, value, data, temp, wrval; 2629 uint8_t stride, stride2; 2630 uint16_t count; 2631 uint32_t poll, mask, modify_mask; 2632 uint32_t wait_count = 0; 2633 uint32_t *data_ptr = *d_ptr; 2634 struct qla8044_minidump_entry_rddfe *rddfe; 2635 uint32_t rval = QLA_SUCCESS; 2636 2637 rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr; 2638 addr1 = le32_to_cpu(rddfe->addr_1); 2639 value = le32_to_cpu(rddfe->value); 2640 stride = le32_to_cpu(rddfe->stride); 2641 stride2 = le32_to_cpu(rddfe->stride2); 2642 count = le32_to_cpu(rddfe->count); 2643 2644 poll = le32_to_cpu(rddfe->poll); 2645 mask = le32_to_cpu(rddfe->mask); 2646 modify_mask = le32_to_cpu(rddfe->modify_mask); 2647 2648 addr2 = addr1 + stride; 2649 2650 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { 2651 ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value)); 2652 2653 wait_count = 0; 2654 while (wait_count < poll) { 2655 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2656 if ((temp & mask) != 0) 2657 break; 2658 wait_count++; 2659 } 2660 2661 if (wait_count == poll) { 2662 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); 2663 rval = QLA_ERROR; 2664 goto exit_process_rddfe; 2665 } else { 2666 ha->isp_ops->rd_reg_indirect(ha, addr2, &temp); 2667 temp = temp & modify_mask; 2668 temp = (temp | ((loop_cnt << 16) | loop_cnt)); 2669 wrval = ((temp << 16) | temp); 2670 2671 ha->isp_ops->wr_reg_indirect(ha, addr2, wrval); 2672 ha->isp_ops->wr_reg_indirect(ha, addr1, value); 2673 2674 wait_count = 0; 2675 while (wait_count < poll) { 2676 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2677 if ((temp & mask) != 0) 2678 break; 2679 wait_count++; 2680 } 2681 if (wait_count == poll) { 2682 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 2683 __func__); 2684 rval = QLA_ERROR; 2685 goto exit_process_rddfe; 2686 } 2687 2688 ha->isp_ops->wr_reg_indirect(ha, addr1, 2689 ((0x40000000 | value) + 2690 stride2)); 2691 wait_count = 0; 2692 while (wait_count < poll) { 2693 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2694 if ((temp & mask) != 0) 2695 break; 2696 wait_count++; 2697 } 2698 2699 if (wait_count == poll) { 2700 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 2701 __func__); 2702 rval = QLA_ERROR; 2703 goto exit_process_rddfe; 2704 } 2705 2706 ha->isp_ops->rd_reg_indirect(ha, addr2, &data); 2707 2708 *data_ptr++ = cpu_to_le32(wrval); 2709 *data_ptr++ = cpu_to_le32(data); 2710 } 2711 } 2712 2713 *d_ptr = data_ptr; 2714 exit_process_rddfe: 2715 return rval; 2716 } 2717 2718 static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha, 2719 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2720 uint32_t **d_ptr) 2721 { 2722 int rval = QLA_SUCCESS; 2723 uint32_t addr1, addr2, value1, value2, data, selval; 2724 uint8_t stride1, stride2; 2725 uint32_t addr3, addr4, addr5, addr6, addr7; 2726 uint16_t count, loop_cnt; 2727 uint32_t mask; 2728 uint32_t *data_ptr = *d_ptr; 2729 struct qla8044_minidump_entry_rdmdio *rdmdio; 2730 2731 rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr; 2732 addr1 = le32_to_cpu(rdmdio->addr_1); 2733 addr2 = le32_to_cpu(rdmdio->addr_2); 2734 value1 = le32_to_cpu(rdmdio->value_1); 2735 stride1 = le32_to_cpu(rdmdio->stride_1); 2736 stride2 = le32_to_cpu(rdmdio->stride_2); 2737 count = le32_to_cpu(rdmdio->count); 2738 2739 mask = le32_to_cpu(rdmdio->mask); 2740 value2 = le32_to_cpu(rdmdio->value_2); 2741 2742 addr3 = addr1 + stride1; 2743 2744 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { 2745 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, 2746 addr3, mask); 2747 if (rval) 2748 goto exit_process_rdmdio; 2749 2750 addr4 = addr2 - stride1; 2751 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4, 2752 value2); 2753 if (rval) 2754 goto exit_process_rdmdio; 2755 2756 addr5 = addr2 - (2 * stride1); 2757 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5, 2758 value1); 2759 if (rval) 2760 goto exit_process_rdmdio; 2761 2762 addr6 = addr2 - (3 * stride1); 2763 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, 2764 addr6, 0x2); 2765 if (rval) 2766 goto exit_process_rdmdio; 2767 2768 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, 2769 addr3, mask); 2770 if (rval) 2771 goto exit_process_rdmdio; 2772 2773 addr7 = addr2 - (4 * stride1); 2774 rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, 2775 mask, addr7, &data); 2776 if (rval) 2777 goto exit_process_rdmdio; 2778 2779 selval = (value2 << 18) | (value1 << 2) | 2; 2780 2781 stride2 = le32_to_cpu(rdmdio->stride_2); 2782 *data_ptr++ = cpu_to_le32(selval); 2783 *data_ptr++ = cpu_to_le32(data); 2784 2785 value1 = value1 + stride2; 2786 *d_ptr = data_ptr; 2787 } 2788 2789 exit_process_rdmdio: 2790 return rval; 2791 } 2792 2793 static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha, 2794 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2795 uint32_t **d_ptr) 2796 { 2797 uint32_t addr1, addr2, value1, value2, poll, r_value; 2798 struct qla8044_minidump_entry_pollwr *pollwr_hdr; 2799 uint32_t wait_count = 0; 2800 uint32_t rval = QLA_SUCCESS; 2801 2802 pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr; 2803 addr1 = le32_to_cpu(pollwr_hdr->addr_1); 2804 addr2 = le32_to_cpu(pollwr_hdr->addr_2); 2805 value1 = le32_to_cpu(pollwr_hdr->value_1); 2806 value2 = le32_to_cpu(pollwr_hdr->value_2); 2807 2808 poll = le32_to_cpu(pollwr_hdr->poll); 2809 2810 while (wait_count < poll) { 2811 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); 2812 2813 if ((r_value & poll) != 0) 2814 break; 2815 2816 wait_count++; 2817 } 2818 2819 if (wait_count == poll) { 2820 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); 2821 rval = QLA_ERROR; 2822 goto exit_process_pollwr; 2823 } 2824 2825 ha->isp_ops->wr_reg_indirect(ha, addr2, value2); 2826 ha->isp_ops->wr_reg_indirect(ha, addr1, value1); 2827 2828 wait_count = 0; 2829 while (wait_count < poll) { 2830 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); 2831 2832 if ((r_value & poll) != 0) 2833 break; 2834 wait_count++; 2835 } 2836 2837 exit_process_pollwr: 2838 return rval; 2839 } 2840 2841 static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha, 2842 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2843 uint32_t **d_ptr) 2844 { 2845 uint32_t sel_val1, sel_val2, t_sel_val, data, i; 2846 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; 2847 struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr; 2848 uint32_t *data_ptr = *d_ptr; 2849 2850 rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr; 2851 sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1); 2852 sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2); 2853 sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1); 2854 sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2); 2855 sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask); 2856 read_addr = le32_to_cpu(rdmux2_hdr->read_addr); 2857 2858 for (i = 0; i < rdmux2_hdr->op_count; i++) { 2859 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1); 2860 t_sel_val = sel_val1 & sel_val_mask; 2861 *data_ptr++ = cpu_to_le32(t_sel_val); 2862 2863 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 2864 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 2865 2866 *data_ptr++ = cpu_to_le32(data); 2867 2868 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2); 2869 t_sel_val = sel_val2 & sel_val_mask; 2870 *data_ptr++ = cpu_to_le32(t_sel_val); 2871 2872 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 2873 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 2874 2875 *data_ptr++ = cpu_to_le32(data); 2876 2877 sel_val1 += rdmux2_hdr->select_value_stride; 2878 sel_val2 += rdmux2_hdr->select_value_stride; 2879 } 2880 2881 *d_ptr = data_ptr; 2882 } 2883 2884 static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha, 2885 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2886 uint32_t **d_ptr) 2887 { 2888 uint32_t poll_wait, poll_mask, r_value, data; 2889 uint32_t addr_1, addr_2, value_1, value_2; 2890 uint32_t *data_ptr = *d_ptr; 2891 uint32_t rval = QLA_SUCCESS; 2892 struct qla83xx_minidump_entry_pollrdmwr *poll_hdr; 2893 2894 poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr; 2895 addr_1 = le32_to_cpu(poll_hdr->addr_1); 2896 addr_2 = le32_to_cpu(poll_hdr->addr_2); 2897 value_1 = le32_to_cpu(poll_hdr->value_1); 2898 value_2 = le32_to_cpu(poll_hdr->value_2); 2899 poll_mask = le32_to_cpu(poll_hdr->poll_mask); 2900 2901 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1); 2902 2903 poll_wait = le32_to_cpu(poll_hdr->poll_wait); 2904 while (1) { 2905 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 2906 2907 if ((r_value & poll_mask) != 0) { 2908 break; 2909 } else { 2910 msleep(1); 2911 if (--poll_wait == 0) { 2912 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n", 2913 __func__); 2914 rval = QLA_ERROR; 2915 goto exit_process_pollrdmwr; 2916 } 2917 } 2918 } 2919 2920 ha->isp_ops->rd_reg_indirect(ha, addr_2, &data); 2921 data &= le32_to_cpu(poll_hdr->modify_mask); 2922 ha->isp_ops->wr_reg_indirect(ha, addr_2, data); 2923 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2); 2924 2925 poll_wait = le32_to_cpu(poll_hdr->poll_wait); 2926 while (1) { 2927 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 2928 2929 if ((r_value & poll_mask) != 0) { 2930 break; 2931 } else { 2932 msleep(1); 2933 if (--poll_wait == 0) { 2934 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n", 2935 __func__); 2936 rval = QLA_ERROR; 2937 goto exit_process_pollrdmwr; 2938 } 2939 } 2940 } 2941 2942 *data_ptr++ = cpu_to_le32(addr_2); 2943 *data_ptr++ = cpu_to_le32(data); 2944 *d_ptr = data_ptr; 2945 2946 exit_process_pollrdmwr: 2947 return rval; 2948 } 2949 2950 static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha, 2951 struct qla8xxx_minidump_entry_hdr *entry_hdr, 2952 uint32_t **d_ptr) 2953 { 2954 uint32_t fl_addr, u32_count, rval; 2955 struct qla8xxx_minidump_entry_rdrom *rom_hdr; 2956 uint32_t *data_ptr = *d_ptr; 2957 2958 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 2959 fl_addr = le32_to_cpu(rom_hdr->read_addr); 2960 u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t); 2961 2962 DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n", 2963 __func__, fl_addr, u32_count)); 2964 2965 rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr, 2966 (u8 *)(data_ptr), u32_count); 2967 2968 if (rval == QLA_ERROR) { 2969 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n", 2970 __func__, u32_count); 2971 goto exit_process_rdrom; 2972 } 2973 2974 data_ptr += u32_count; 2975 *d_ptr = data_ptr; 2976 2977 exit_process_rdrom: 2978 return rval; 2979 } 2980 2981 /** 2982 * qla4_8xxx_collect_md_data - Retrieve firmware minidump data. 2983 * @ha: pointer to adapter structure 2984 **/ 2985 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) 2986 { 2987 int num_entry_hdr = 0; 2988 struct qla8xxx_minidump_entry_hdr *entry_hdr; 2989 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2990 uint32_t *data_ptr; 2991 uint32_t data_collected = 0; 2992 int i, rval = QLA_ERROR; 2993 uint64_t now; 2994 uint32_t timestamp; 2995 2996 ha->fw_dump_skip_size = 0; 2997 if (!ha->fw_dump) { 2998 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", 2999 __func__, ha->host_no); 3000 return rval; 3001 } 3002 3003 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 3004 ha->fw_dump_tmplt_hdr; 3005 data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + 3006 ha->fw_dump_tmplt_size); 3007 data_collected += ha->fw_dump_tmplt_size; 3008 3009 num_entry_hdr = tmplt_hdr->num_of_entries; 3010 ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", 3011 __func__, data_ptr); 3012 ql4_printk(KERN_INFO, ha, 3013 "[%s]: no of entry headers in Template: 0x%x\n", 3014 __func__, num_entry_hdr); 3015 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", 3016 __func__, ha->fw_dump_capture_mask); 3017 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", 3018 __func__, ha->fw_dump_size, ha->fw_dump_size); 3019 3020 /* Update current timestamp before taking dump */ 3021 now = get_jiffies_64(); 3022 timestamp = (u32)(jiffies_to_msecs(now) / 1000); 3023 tmplt_hdr->driver_timestamp = timestamp; 3024 3025 entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 3026 (((uint8_t *)ha->fw_dump_tmplt_hdr) + 3027 tmplt_hdr->first_entry_offset); 3028 3029 if (is_qla8032(ha) || is_qla8042(ha)) 3030 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] = 3031 tmplt_hdr->ocm_window_reg[ha->func_num]; 3032 3033 /* Walk through the entry headers - validate/perform required action */ 3034 for (i = 0; i < num_entry_hdr; i++) { 3035 if (data_collected > ha->fw_dump_size) { 3036 ql4_printk(KERN_INFO, ha, 3037 "Data collected: [0x%x], Total Dump size: [0x%x]\n", 3038 data_collected, ha->fw_dump_size); 3039 return rval; 3040 } 3041 3042 if (!(entry_hdr->d_ctrl.entry_capture_mask & 3043 ha->fw_dump_capture_mask)) { 3044 entry_hdr->d_ctrl.driver_flags |= 3045 QLA8XXX_DBG_SKIPPED_FLAG; 3046 goto skip_nxt_entry; 3047 } 3048 3049 DEBUG2(ql4_printk(KERN_INFO, ha, 3050 "Data collected: [0x%x], Dump size left:[0x%x]\n", 3051 data_collected, 3052 (ha->fw_dump_size - data_collected))); 3053 3054 /* Decode the entry type and take required action to capture 3055 * debug data 3056 */ 3057 switch (entry_hdr->entry_type) { 3058 case QLA8XXX_RDEND: 3059 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3060 break; 3061 case QLA8XXX_CNTRL: 3062 rval = qla4_8xxx_minidump_process_control(ha, 3063 entry_hdr); 3064 if (rval != QLA_SUCCESS) { 3065 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3066 goto md_failed; 3067 } 3068 break; 3069 case QLA8XXX_RDCRB: 3070 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, 3071 &data_ptr); 3072 break; 3073 case QLA8XXX_RDMEM: 3074 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 3075 &data_ptr); 3076 if (rval != QLA_SUCCESS) { 3077 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3078 goto md_failed; 3079 } 3080 break; 3081 case QLA8XXX_BOARD: 3082 case QLA8XXX_RDROM: 3083 if (is_qla8022(ha)) { 3084 qla4_82xx_minidump_process_rdrom(ha, entry_hdr, 3085 &data_ptr); 3086 } else if (is_qla8032(ha) || is_qla8042(ha)) { 3087 rval = qla4_83xx_minidump_process_rdrom(ha, 3088 entry_hdr, 3089 &data_ptr); 3090 if (rval != QLA_SUCCESS) 3091 qla4_8xxx_mark_entry_skipped(ha, 3092 entry_hdr, 3093 i); 3094 } 3095 break; 3096 case QLA8XXX_L2DTG: 3097 case QLA8XXX_L2ITG: 3098 case QLA8XXX_L2DAT: 3099 case QLA8XXX_L2INS: 3100 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, 3101 &data_ptr); 3102 if (rval != QLA_SUCCESS) { 3103 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3104 goto md_failed; 3105 } 3106 break; 3107 case QLA8XXX_L1DTG: 3108 case QLA8XXX_L1ITG: 3109 case QLA8XXX_L1DAT: 3110 case QLA8XXX_L1INS: 3111 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, 3112 &data_ptr); 3113 break; 3114 case QLA8XXX_RDOCM: 3115 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, 3116 &data_ptr); 3117 break; 3118 case QLA8XXX_RDMUX: 3119 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, 3120 &data_ptr); 3121 break; 3122 case QLA8XXX_QUEUE: 3123 qla4_8xxx_minidump_process_queue(ha, entry_hdr, 3124 &data_ptr); 3125 break; 3126 case QLA83XX_POLLRD: 3127 if (is_qla8022(ha)) { 3128 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3129 break; 3130 } 3131 rval = qla83xx_minidump_process_pollrd(ha, entry_hdr, 3132 &data_ptr); 3133 if (rval != QLA_SUCCESS) 3134 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3135 break; 3136 case QLA83XX_RDMUX2: 3137 if (is_qla8022(ha)) { 3138 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3139 break; 3140 } 3141 qla83xx_minidump_process_rdmux2(ha, entry_hdr, 3142 &data_ptr); 3143 break; 3144 case QLA83XX_POLLRDMWR: 3145 if (is_qla8022(ha)) { 3146 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3147 break; 3148 } 3149 rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr, 3150 &data_ptr); 3151 if (rval != QLA_SUCCESS) 3152 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3153 break; 3154 case QLA8044_RDDFE: 3155 rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr, 3156 &data_ptr); 3157 if (rval != QLA_SUCCESS) 3158 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3159 break; 3160 case QLA8044_RDMDIO: 3161 rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr, 3162 &data_ptr); 3163 if (rval != QLA_SUCCESS) 3164 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3165 break; 3166 case QLA8044_POLLWR: 3167 rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr, 3168 &data_ptr); 3169 if (rval != QLA_SUCCESS) 3170 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3171 break; 3172 case QLA8XXX_RDNOP: 3173 default: 3174 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3175 break; 3176 } 3177 3178 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump; 3179 skip_nxt_entry: 3180 /* next entry in the template */ 3181 entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 3182 (((uint8_t *)entry_hdr) + 3183 entry_hdr->entry_size); 3184 } 3185 3186 if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) { 3187 ql4_printk(KERN_INFO, ha, 3188 "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", 3189 data_collected, ha->fw_dump_size); 3190 rval = QLA_ERROR; 3191 goto md_failed; 3192 } 3193 3194 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", 3195 __func__, i)); 3196 md_failed: 3197 return rval; 3198 } 3199 3200 /** 3201 * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. 3202 * @ha: pointer to adapter structure 3203 * @code: uevent code to act upon 3204 **/ 3205 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) 3206 { 3207 char event_string[40]; 3208 char *envp[] = { event_string, NULL }; 3209 3210 switch (code) { 3211 case QL4_UEVENT_CODE_FW_DUMP: 3212 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 3213 ha->host_no); 3214 break; 3215 default: 3216 /*do nothing*/ 3217 break; 3218 } 3219 3220 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); 3221 } 3222 3223 void qla4_8xxx_get_minidump(struct scsi_qla_host *ha) 3224 { 3225 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 3226 !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 3227 if (!qla4_8xxx_collect_md_data(ha)) { 3228 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); 3229 set_bit(AF_82XX_FW_DUMPED, &ha->flags); 3230 } else { 3231 ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n", 3232 __func__); 3233 } 3234 } 3235 } 3236 3237 /** 3238 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 3239 * @ha: pointer to adapter structure 3240 * 3241 * Note: IDC lock must be held upon entry 3242 **/ 3243 int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 3244 { 3245 int rval = QLA_ERROR; 3246 int i; 3247 uint32_t old_count, count; 3248 int need_reset = 0; 3249 3250 need_reset = ha->isp_ops->need_reset(ha); 3251 3252 if (need_reset) { 3253 /* We are trying to perform a recovery here. */ 3254 if (test_bit(AF_FW_RECOVERY, &ha->flags)) 3255 ha->isp_ops->rom_lock_recovery(ha); 3256 } else { 3257 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); 3258 for (i = 0; i < 10; i++) { 3259 msleep(200); 3260 count = qla4_8xxx_rd_direct(ha, 3261 QLA8XXX_PEG_ALIVE_COUNTER); 3262 if (count != old_count) { 3263 rval = QLA_SUCCESS; 3264 goto dev_ready; 3265 } 3266 } 3267 ha->isp_ops->rom_lock_recovery(ha); 3268 } 3269 3270 /* set to DEV_INITIALIZING */ 3271 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 3272 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 3273 QLA8XXX_DEV_INITIALIZING); 3274 3275 ha->isp_ops->idc_unlock(ha); 3276 3277 if (is_qla8022(ha)) 3278 qla4_8xxx_get_minidump(ha); 3279 3280 rval = ha->isp_ops->restart_firmware(ha); 3281 ha->isp_ops->idc_lock(ha); 3282 3283 if (rval != QLA_SUCCESS) { 3284 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 3285 qla4_8xxx_clear_drv_active(ha); 3286 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 3287 QLA8XXX_DEV_FAILED); 3288 return rval; 3289 } 3290 3291 dev_ready: 3292 ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 3293 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 3294 3295 return rval; 3296 } 3297 3298 /** 3299 * qla4_82xx_need_reset_handler - Code to start reset sequence 3300 * @ha: pointer to adapter structure 3301 * 3302 * Note: IDC lock must be held upon entry 3303 **/ 3304 static void 3305 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) 3306 { 3307 uint32_t dev_state, drv_state, drv_active; 3308 uint32_t active_mask = 0xFFFFFFFF; 3309 unsigned long reset_timeout; 3310 3311 ql4_printk(KERN_INFO, ha, 3312 "Performing ISP error recovery\n"); 3313 3314 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 3315 qla4_82xx_idc_unlock(ha); 3316 ha->isp_ops->disable_intrs(ha); 3317 qla4_82xx_idc_lock(ha); 3318 } 3319 3320 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 3321 DEBUG2(ql4_printk(KERN_INFO, ha, 3322 "%s(%ld): reset acknowledged\n", 3323 __func__, ha->host_no)); 3324 qla4_8xxx_set_rst_ready(ha); 3325 } else { 3326 active_mask = (~(1 << (ha->func_num * 4))); 3327 } 3328 3329 /* wait for 10 seconds for reset ack from all functions */ 3330 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3331 3332 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3333 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3334 3335 ql4_printk(KERN_INFO, ha, 3336 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 3337 __func__, ha->host_no, drv_state, drv_active); 3338 3339 while (drv_state != (drv_active & active_mask)) { 3340 if (time_after_eq(jiffies, reset_timeout)) { 3341 ql4_printk(KERN_INFO, ha, 3342 "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", 3343 DRIVER_NAME, drv_state, drv_active); 3344 break; 3345 } 3346 3347 /* 3348 * When reset_owner times out, check which functions 3349 * acked/did not ack 3350 */ 3351 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 3352 ql4_printk(KERN_INFO, ha, 3353 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 3354 __func__, ha->host_no, drv_state, 3355 drv_active); 3356 } 3357 qla4_82xx_idc_unlock(ha); 3358 msleep(1000); 3359 qla4_82xx_idc_lock(ha); 3360 3361 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3362 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3363 } 3364 3365 /* Clear RESET OWNER as we are not going to use it any further */ 3366 clear_bit(AF_8XXX_RST_OWNER, &ha->flags); 3367 3368 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3369 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, 3370 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3371 3372 /* Force to DEV_COLD unless someone else is starting a reset */ 3373 if (dev_state != QLA8XXX_DEV_INITIALIZING) { 3374 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 3375 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3376 qla4_8xxx_set_rst_ready(ha); 3377 } 3378 } 3379 3380 /** 3381 * qla4_8xxx_need_qsnt_handler - Code to start qsnt 3382 * @ha: pointer to adapter structure 3383 **/ 3384 void 3385 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 3386 { 3387 ha->isp_ops->idc_lock(ha); 3388 qla4_8xxx_set_qsnt_ready(ha); 3389 ha->isp_ops->idc_unlock(ha); 3390 } 3391 3392 static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha) 3393 { 3394 int idc_ver; 3395 uint32_t drv_active; 3396 3397 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 3398 if (drv_active == (1 << (ha->func_num * 4))) { 3399 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, 3400 QLA82XX_IDC_VERSION); 3401 ql4_printk(KERN_INFO, ha, 3402 "%s: IDC version updated to %d\n", __func__, 3403 QLA82XX_IDC_VERSION); 3404 } else { 3405 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 3406 if (QLA82XX_IDC_VERSION != idc_ver) { 3407 ql4_printk(KERN_INFO, ha, 3408 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 3409 __func__, QLA82XX_IDC_VERSION, idc_ver); 3410 } 3411 } 3412 } 3413 3414 static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha) 3415 { 3416 int idc_ver; 3417 uint32_t drv_active; 3418 int rval = QLA_SUCCESS; 3419 3420 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 3421 if (drv_active == (1 << ha->func_num)) { 3422 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 3423 idc_ver &= (~0xFF); 3424 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE; 3425 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver); 3426 ql4_printk(KERN_INFO, ha, 3427 "%s: IDC version updated to %d\n", __func__, 3428 idc_ver); 3429 } else { 3430 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 3431 idc_ver &= 0xFF; 3432 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) { 3433 ql4_printk(KERN_INFO, ha, 3434 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 3435 __func__, QLA83XX_IDC_VER_MAJ_VALUE, 3436 idc_ver); 3437 rval = QLA_ERROR; 3438 goto exit_set_idc_ver; 3439 } 3440 } 3441 3442 /* Update IDC_MINOR_VERSION */ 3443 idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR); 3444 idc_ver &= ~(0x03 << (ha->func_num * 2)); 3445 idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2)); 3446 qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver); 3447 3448 exit_set_idc_ver: 3449 return rval; 3450 } 3451 3452 int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha) 3453 { 3454 uint32_t drv_active; 3455 int rval = QLA_SUCCESS; 3456 3457 if (test_bit(AF_INIT_DONE, &ha->flags)) 3458 goto exit_update_idc_reg; 3459 3460 ha->isp_ops->idc_lock(ha); 3461 qla4_8xxx_set_drv_active(ha); 3462 3463 /* 3464 * If we are the first driver to load and 3465 * ql4xdontresethba is not set, clear IDC_CTRL BIT0. 3466 */ 3467 if (is_qla8032(ha) || is_qla8042(ha)) { 3468 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 3469 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba) 3470 qla4_83xx_clear_idc_dontreset(ha); 3471 } 3472 3473 if (is_qla8022(ha)) { 3474 qla4_82xx_set_idc_ver(ha); 3475 } else if (is_qla8032(ha) || is_qla8042(ha)) { 3476 rval = qla4_83xx_set_idc_ver(ha); 3477 if (rval == QLA_ERROR) 3478 qla4_8xxx_clear_drv_active(ha); 3479 } 3480 3481 ha->isp_ops->idc_unlock(ha); 3482 3483 exit_update_idc_reg: 3484 return rval; 3485 } 3486 3487 /** 3488 * qla4_8xxx_device_state_handler - Adapter state machine 3489 * @ha: pointer to host adapter structure. 3490 * 3491 * Note: IDC lock must be UNLOCKED upon entry 3492 **/ 3493 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 3494 { 3495 uint32_t dev_state; 3496 int rval = QLA_SUCCESS; 3497 unsigned long dev_init_timeout; 3498 3499 rval = qla4_8xxx_update_idc_reg(ha); 3500 if (rval == QLA_ERROR) 3501 goto exit_state_handler; 3502 3503 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3504 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3505 dev_state, dev_state < MAX_STATES ? 3506 qdev_state[dev_state] : "Unknown")); 3507 3508 /* wait for 30 seconds for device to go ready */ 3509 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3510 3511 ha->isp_ops->idc_lock(ha); 3512 while (1) { 3513 3514 if (time_after_eq(jiffies, dev_init_timeout)) { 3515 ql4_printk(KERN_WARNING, ha, 3516 "%s: Device Init Failed 0x%x = %s\n", 3517 DRIVER_NAME, 3518 dev_state, dev_state < MAX_STATES ? 3519 qdev_state[dev_state] : "Unknown"); 3520 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 3521 QLA8XXX_DEV_FAILED); 3522 } 3523 3524 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3525 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3526 dev_state, dev_state < MAX_STATES ? 3527 qdev_state[dev_state] : "Unknown"); 3528 3529 /* NOTE: Make sure idc unlocked upon exit of switch statement */ 3530 switch (dev_state) { 3531 case QLA8XXX_DEV_READY: 3532 goto exit; 3533 case QLA8XXX_DEV_COLD: 3534 rval = qla4_8xxx_device_bootstrap(ha); 3535 goto exit; 3536 case QLA8XXX_DEV_INITIALIZING: 3537 ha->isp_ops->idc_unlock(ha); 3538 msleep(1000); 3539 ha->isp_ops->idc_lock(ha); 3540 break; 3541 case QLA8XXX_DEV_NEED_RESET: 3542 /* 3543 * For ISP8324 and ISP8042, if NEED_RESET is set by any 3544 * driver, it should be honored, irrespective of 3545 * IDC_CTRL DONTRESET_BIT0 3546 */ 3547 if (is_qla8032(ha) || is_qla8042(ha)) { 3548 qla4_83xx_need_reset_handler(ha); 3549 } else if (is_qla8022(ha)) { 3550 if (!ql4xdontresethba) { 3551 qla4_82xx_need_reset_handler(ha); 3552 /* Update timeout value after need 3553 * reset handler */ 3554 dev_init_timeout = jiffies + 3555 (ha->nx_dev_init_timeout * HZ); 3556 } else { 3557 ha->isp_ops->idc_unlock(ha); 3558 msleep(1000); 3559 ha->isp_ops->idc_lock(ha); 3560 } 3561 } 3562 break; 3563 case QLA8XXX_DEV_NEED_QUIESCENT: 3564 /* idc locked/unlocked in handler */ 3565 qla4_8xxx_need_qsnt_handler(ha); 3566 break; 3567 case QLA8XXX_DEV_QUIESCENT: 3568 ha->isp_ops->idc_unlock(ha); 3569 msleep(1000); 3570 ha->isp_ops->idc_lock(ha); 3571 break; 3572 case QLA8XXX_DEV_FAILED: 3573 ha->isp_ops->idc_unlock(ha); 3574 qla4xxx_dead_adapter_cleanup(ha); 3575 rval = QLA_ERROR; 3576 ha->isp_ops->idc_lock(ha); 3577 goto exit; 3578 default: 3579 ha->isp_ops->idc_unlock(ha); 3580 qla4xxx_dead_adapter_cleanup(ha); 3581 rval = QLA_ERROR; 3582 ha->isp_ops->idc_lock(ha); 3583 goto exit; 3584 } 3585 } 3586 exit: 3587 ha->isp_ops->idc_unlock(ha); 3588 exit_state_handler: 3589 return rval; 3590 } 3591 3592 int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 3593 { 3594 int retval; 3595 3596 /* clear the interrupt */ 3597 if (is_qla8032(ha) || is_qla8042(ha)) { 3598 writel(0, &ha->qla4_83xx_reg->risc_intr); 3599 readl(&ha->qla4_83xx_reg->risc_intr); 3600 } else if (is_qla8022(ha)) { 3601 writel(0, &ha->qla4_82xx_reg->host_int); 3602 readl(&ha->qla4_82xx_reg->host_int); 3603 } 3604 3605 retval = qla4_8xxx_device_state_handler(ha); 3606 3607 /* Initialize request and response queues. */ 3608 if (retval == QLA_SUCCESS) 3609 qla4xxx_init_rings(ha); 3610 3611 if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags)) 3612 retval = qla4xxx_request_irqs(ha); 3613 3614 return retval; 3615 } 3616 3617 /*****************************************************************************/ 3618 /* Flash Manipulation Routines */ 3619 /*****************************************************************************/ 3620 3621 #define OPTROM_BURST_SIZE 0x1000 3622 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3623 3624 #define FARX_DATA_FLAG BIT_31 3625 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 3626 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 3627 3628 static inline uint32_t 3629 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 3630 { 3631 return hw->flash_conf_off | faddr; 3632 } 3633 3634 static uint32_t * 3635 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 3636 uint32_t faddr, uint32_t length) 3637 { 3638 uint32_t i; 3639 uint32_t val; 3640 int loops = 0; 3641 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 3642 udelay(100); 3643 cond_resched(); 3644 loops++; 3645 } 3646 if (loops >= 50000) { 3647 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 3648 return dwptr; 3649 } 3650 3651 /* Dword reads to flash. */ 3652 for (i = 0; i < length/4; i++, faddr += 4) { 3653 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { 3654 ql4_printk(KERN_WARNING, ha, 3655 "Do ROM fast read failed\n"); 3656 goto done_read; 3657 } 3658 dwptr[i] = cpu_to_le32(val); 3659 } 3660 3661 done_read: 3662 qla4_82xx_rom_unlock(ha); 3663 return dwptr; 3664 } 3665 3666 /* 3667 * Address and length are byte address 3668 */ 3669 static uint8_t * 3670 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 3671 uint32_t offset, uint32_t length) 3672 { 3673 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); 3674 return buf; 3675 } 3676 3677 static int 3678 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 3679 { 3680 const char *loc, *locations[] = { "DEF", "PCI" }; 3681 3682 /* 3683 * FLT-location structure resides after the last PCI region. 3684 */ 3685 3686 /* Begin with sane defaults. */ 3687 loc = locations[0]; 3688 *start = FA_FLASH_LAYOUT_ADDR_82; 3689 3690 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 3691 return QLA_SUCCESS; 3692 } 3693 3694 static void 3695 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 3696 { 3697 const char *loc, *locations[] = { "DEF", "FLT" }; 3698 uint16_t *wptr; 3699 uint16_t cnt, chksum; 3700 uint32_t start, status; 3701 struct qla_flt_header *flt; 3702 struct qla_flt_region *region; 3703 struct ql82xx_hw_data *hw = &ha->hw; 3704 3705 hw->flt_region_flt = flt_addr; 3706 wptr = (uint16_t *)ha->request_ring; 3707 flt = (struct qla_flt_header *)ha->request_ring; 3708 region = (struct qla_flt_region *)&flt[1]; 3709 3710 if (is_qla8022(ha)) { 3711 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3712 flt_addr << 2, OPTROM_BURST_SIZE); 3713 } else if (is_qla8032(ha) || is_qla8042(ha)) { 3714 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2, 3715 (uint8_t *)ha->request_ring, 3716 0x400); 3717 if (status != QLA_SUCCESS) 3718 goto no_flash_data; 3719 } 3720 3721 if (*wptr == cpu_to_le16(0xffff)) 3722 goto no_flash_data; 3723 if (flt->version != cpu_to_le16(1)) { 3724 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 3725 "version=0x%x length=0x%x checksum=0x%x.\n", 3726 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3727 le16_to_cpu(flt->checksum))); 3728 goto no_flash_data; 3729 } 3730 3731 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 3732 for (chksum = 0; cnt; cnt--) 3733 chksum += le16_to_cpu(*wptr++); 3734 if (chksum) { 3735 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 3736 "version=0x%x length=0x%x checksum=0x%x.\n", 3737 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3738 chksum)); 3739 goto no_flash_data; 3740 } 3741 3742 loc = locations[1]; 3743 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 3744 for ( ; cnt; cnt--, region++) { 3745 /* Store addresses as DWORD offsets. */ 3746 start = le32_to_cpu(region->start) >> 2; 3747 3748 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 3749 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 3750 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 3751 3752 switch (le32_to_cpu(region->code) & 0xff) { 3753 case FLT_REG_FDT: 3754 hw->flt_region_fdt = start; 3755 break; 3756 case FLT_REG_BOOT_CODE_82: 3757 hw->flt_region_boot = start; 3758 break; 3759 case FLT_REG_FW_82: 3760 case FLT_REG_FW_82_1: 3761 hw->flt_region_fw = start; 3762 break; 3763 case FLT_REG_BOOTLOAD_82: 3764 hw->flt_region_bootload = start; 3765 break; 3766 case FLT_REG_ISCSI_PARAM: 3767 hw->flt_iscsi_param = start; 3768 break; 3769 case FLT_REG_ISCSI_CHAP: 3770 hw->flt_region_chap = start; 3771 hw->flt_chap_size = le32_to_cpu(region->size); 3772 break; 3773 case FLT_REG_ISCSI_DDB: 3774 hw->flt_region_ddb = start; 3775 hw->flt_ddb_size = le32_to_cpu(region->size); 3776 break; 3777 } 3778 } 3779 goto done; 3780 3781 no_flash_data: 3782 /* Use hardcoded defaults. */ 3783 loc = locations[0]; 3784 3785 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 3786 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 3787 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 3788 hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 3789 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2; 3790 hw->flt_chap_size = FA_FLASH_CHAP_SIZE; 3791 hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2; 3792 hw->flt_ddb_size = FA_FLASH_DDB_SIZE; 3793 3794 done: 3795 DEBUG2(ql4_printk(KERN_INFO, ha, 3796 "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n", 3797 loc, hw->flt_region_flt, hw->flt_region_fdt, 3798 hw->flt_region_boot, hw->flt_region_bootload, 3799 hw->flt_region_fw, hw->flt_region_chap, 3800 hw->flt_chap_size, hw->flt_region_ddb, 3801 hw->flt_ddb_size)); 3802 } 3803 3804 static void 3805 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha) 3806 { 3807 #define FLASH_BLK_SIZE_4K 0x1000 3808 #define FLASH_BLK_SIZE_32K 0x8000 3809 #define FLASH_BLK_SIZE_64K 0x10000 3810 const char *loc, *locations[] = { "MID", "FDT" }; 3811 uint16_t cnt, chksum; 3812 uint16_t *wptr; 3813 struct qla_fdt_layout *fdt; 3814 uint16_t mid = 0; 3815 uint16_t fid = 0; 3816 struct ql82xx_hw_data *hw = &ha->hw; 3817 3818 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3819 hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 3820 3821 wptr = (uint16_t *)ha->request_ring; 3822 fdt = (struct qla_fdt_layout *)ha->request_ring; 3823 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3824 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 3825 3826 if (*wptr == cpu_to_le16(0xffff)) 3827 goto no_flash_data; 3828 3829 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 3830 fdt->sig[3] != 'D') 3831 goto no_flash_data; 3832 3833 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 3834 cnt++) 3835 chksum += le16_to_cpu(*wptr++); 3836 3837 if (chksum) { 3838 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 3839 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 3840 le16_to_cpu(fdt->version))); 3841 goto no_flash_data; 3842 } 3843 3844 loc = locations[1]; 3845 mid = le16_to_cpu(fdt->man_id); 3846 fid = le16_to_cpu(fdt->id); 3847 hw->fdt_wrt_disable = fdt->wrt_disable_bits; 3848 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 3849 hw->fdt_block_size = le32_to_cpu(fdt->block_size); 3850 3851 if (fdt->unprotect_sec_cmd) { 3852 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 3853 fdt->unprotect_sec_cmd); 3854 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 3855 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 3856 flash_conf_addr(hw, 0x0336); 3857 } 3858 goto done; 3859 3860 no_flash_data: 3861 loc = locations[0]; 3862 hw->fdt_block_size = FLASH_BLK_SIZE_64K; 3863 done: 3864 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 3865 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 3866 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 3867 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 3868 hw->fdt_block_size)); 3869 } 3870 3871 static void 3872 qla4_82xx_get_idc_param(struct scsi_qla_host *ha) 3873 { 3874 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 3875 uint32_t *wptr; 3876 3877 if (!is_qla8022(ha)) 3878 return; 3879 wptr = (uint32_t *)ha->request_ring; 3880 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3881 QLA82XX_IDC_PARAM_ADDR , 8); 3882 3883 if (*wptr == cpu_to_le32(0xffffffff)) { 3884 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 3885 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 3886 } else { 3887 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 3888 ha->nx_reset_timeout = le32_to_cpu(*wptr); 3889 } 3890 3891 DEBUG2(ql4_printk(KERN_DEBUG, ha, 3892 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 3893 DEBUG2(ql4_printk(KERN_DEBUG, ha, 3894 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 3895 return; 3896 } 3897 3898 void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, 3899 int in_count) 3900 { 3901 int i; 3902 3903 /* Load all mailbox registers, except mailbox 0. */ 3904 for (i = 1; i < in_count; i++) 3905 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]); 3906 3907 /* Wakeup firmware */ 3908 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]); 3909 readl(&ha->qla4_82xx_reg->mailbox_in[0]); 3910 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint); 3911 readl(&ha->qla4_82xx_reg->hint); 3912 } 3913 3914 void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count) 3915 { 3916 int intr_status; 3917 3918 intr_status = readl(&ha->qla4_82xx_reg->host_int); 3919 if (intr_status & ISRX_82XX_RISC_INT) { 3920 ha->mbox_status_count = out_count; 3921 intr_status = readl(&ha->qla4_82xx_reg->host_status); 3922 ha->isp_ops->interrupt_service_routine(ha, intr_status); 3923 3924 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) && 3925 (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled)) 3926 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 3927 0xfbff); 3928 } 3929 } 3930 3931 int 3932 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 3933 { 3934 int ret; 3935 uint32_t flt_addr; 3936 3937 ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 3938 if (ret != QLA_SUCCESS) 3939 return ret; 3940 3941 qla4_8xxx_get_flt_info(ha, flt_addr); 3942 if (is_qla8022(ha)) { 3943 qla4_82xx_get_fdt_info(ha); 3944 qla4_82xx_get_idc_param(ha); 3945 } else if (is_qla8032(ha) || is_qla8042(ha)) { 3946 qla4_83xx_get_idc_param(ha); 3947 } 3948 3949 return QLA_SUCCESS; 3950 } 3951 3952 /** 3953 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 3954 * @ha: pointer to host adapter structure. 3955 * 3956 * Remarks: 3957 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 3958 * not be available after successful return. Driver must cleanup potential 3959 * outstanding I/O's after calling this funcion. 3960 **/ 3961 int 3962 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 3963 { 3964 int status; 3965 uint32_t mbox_cmd[MBOX_REG_COUNT]; 3966 uint32_t mbox_sts[MBOX_REG_COUNT]; 3967 3968 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3969 memset(&mbox_sts, 0, sizeof(mbox_sts)); 3970 3971 mbox_cmd[0] = MBOX_CMD_STOP_FW; 3972 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 3973 &mbox_cmd[0], &mbox_sts[0]); 3974 3975 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 3976 __func__, status)); 3977 return status; 3978 } 3979 3980 /** 3981 * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands. 3982 * @ha: pointer to host adapter structure. 3983 **/ 3984 int 3985 qla4_82xx_isp_reset(struct scsi_qla_host *ha) 3986 { 3987 int rval; 3988 uint32_t dev_state; 3989 3990 qla4_82xx_idc_lock(ha); 3991 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3992 3993 if (dev_state == QLA8XXX_DEV_READY) { 3994 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 3995 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3996 QLA8XXX_DEV_NEED_RESET); 3997 set_bit(AF_8XXX_RST_OWNER, &ha->flags); 3998 } else 3999 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 4000 4001 qla4_82xx_idc_unlock(ha); 4002 4003 rval = qla4_8xxx_device_state_handler(ha); 4004 4005 qla4_82xx_idc_lock(ha); 4006 qla4_8xxx_clear_rst_ready(ha); 4007 qla4_82xx_idc_unlock(ha); 4008 4009 if (rval == QLA_SUCCESS) { 4010 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n"); 4011 clear_bit(AF_FW_RECOVERY, &ha->flags); 4012 } 4013 4014 return rval; 4015 } 4016 4017 /** 4018 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 4019 * @ha: pointer to host adapter structure. 4020 * 4021 **/ 4022 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 4023 { 4024 uint32_t mbox_cmd[MBOX_REG_COUNT]; 4025 uint32_t mbox_sts[MBOX_REG_COUNT]; 4026 struct mbx_sys_info *sys_info; 4027 dma_addr_t sys_info_dma; 4028 int status = QLA_ERROR; 4029 4030 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 4031 &sys_info_dma, GFP_KERNEL); 4032 if (sys_info == NULL) { 4033 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 4034 ha->host_no, __func__)); 4035 return status; 4036 } 4037 4038 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4039 memset(&mbox_sts, 0, sizeof(mbox_sts)); 4040 4041 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 4042 mbox_cmd[1] = LSDW(sys_info_dma); 4043 mbox_cmd[2] = MSDW(sys_info_dma); 4044 mbox_cmd[4] = sizeof(*sys_info); 4045 4046 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 4047 &mbox_sts[0]) != QLA_SUCCESS) { 4048 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 4049 ha->host_no, __func__)); 4050 goto exit_validate_mac82; 4051 } 4052 4053 /* Make sure we receive the minimum required data to cache internally */ 4054 if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) < 4055 offsetof(struct mbx_sys_info, reserved)) { 4056 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 4057 " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 4058 goto exit_validate_mac82; 4059 } 4060 4061 /* Save M.A.C. address & serial_number */ 4062 ha->port_num = sys_info->port_num; 4063 memcpy(ha->my_mac, &sys_info->mac_addr[0], 4064 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 4065 memcpy(ha->serial_number, &sys_info->serial_number, 4066 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 4067 memcpy(ha->model_name, &sys_info->board_id_str, 4068 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); 4069 ha->phy_port_cnt = sys_info->phys_port_cnt; 4070 ha->phy_port_num = sys_info->port_num; 4071 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; 4072 4073 DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n", 4074 ha->host_no, __func__, ha->my_mac, ha->serial_number)); 4075 4076 status = QLA_SUCCESS; 4077 4078 exit_validate_mac82: 4079 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 4080 sys_info_dma); 4081 return status; 4082 } 4083 4084 /* Interrupt handling helpers. */ 4085 4086 int qla4_8xxx_intr_enable(struct scsi_qla_host *ha) 4087 { 4088 uint32_t mbox_cmd[MBOX_REG_COUNT]; 4089 uint32_t mbox_sts[MBOX_REG_COUNT]; 4090 4091 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 4092 4093 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4094 memset(&mbox_sts, 0, sizeof(mbox_sts)); 4095 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 4096 mbox_cmd[1] = INTR_ENABLE; 4097 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 4098 &mbox_sts[0]) != QLA_SUCCESS) { 4099 DEBUG2(ql4_printk(KERN_INFO, ha, 4100 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 4101 __func__, mbox_sts[0])); 4102 return QLA_ERROR; 4103 } 4104 return QLA_SUCCESS; 4105 } 4106 4107 int qla4_8xxx_intr_disable(struct scsi_qla_host *ha) 4108 { 4109 uint32_t mbox_cmd[MBOX_REG_COUNT]; 4110 uint32_t mbox_sts[MBOX_REG_COUNT]; 4111 4112 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 4113 4114 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4115 memset(&mbox_sts, 0, sizeof(mbox_sts)); 4116 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 4117 mbox_cmd[1] = INTR_DISABLE; 4118 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 4119 &mbox_sts[0]) != QLA_SUCCESS) { 4120 DEBUG2(ql4_printk(KERN_INFO, ha, 4121 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 4122 __func__, mbox_sts[0])); 4123 return QLA_ERROR; 4124 } 4125 4126 return QLA_SUCCESS; 4127 } 4128 4129 void 4130 qla4_82xx_enable_intrs(struct scsi_qla_host *ha) 4131 { 4132 qla4_8xxx_intr_enable(ha); 4133 4134 spin_lock_irq(&ha->hardware_lock); 4135 /* BIT 10 - reset */ 4136 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 4137 spin_unlock_irq(&ha->hardware_lock); 4138 set_bit(AF_INTERRUPTS_ON, &ha->flags); 4139 } 4140 4141 void 4142 qla4_82xx_disable_intrs(struct scsi_qla_host *ha) 4143 { 4144 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 4145 qla4_8xxx_intr_disable(ha); 4146 4147 spin_lock_irq(&ha->hardware_lock); 4148 /* BIT 10 - set */ 4149 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 4150 spin_unlock_irq(&ha->hardware_lock); 4151 } 4152 4153 int 4154 qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 4155 { 4156 int ret; 4157 4158 ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES, 4159 QLA_MSIX_ENTRIES, PCI_IRQ_MSIX); 4160 if (ret < 0) { 4161 ql4_printk(KERN_WARNING, ha, 4162 "MSI-X: Failed to enable support -- %d/%d\n", 4163 QLA_MSIX_ENTRIES, ret); 4164 return ret; 4165 } 4166 4167 ret = request_irq(pci_irq_vector(ha->pdev, 0), 4168 qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)", 4169 ha); 4170 if (ret) 4171 goto out_free_vectors; 4172 4173 ret = request_irq(pci_irq_vector(ha->pdev, 1), 4174 qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha); 4175 if (ret) 4176 goto out_free_default_irq; 4177 4178 return 0; 4179 4180 out_free_default_irq: 4181 free_irq(pci_irq_vector(ha->pdev, 0), ha); 4182 out_free_vectors: 4183 pci_free_irq_vectors(ha->pdev); 4184 return ret; 4185 } 4186 4187 int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha) 4188 { 4189 int status = QLA_SUCCESS; 4190 4191 /* Dont retry adapter initialization if IRQ allocation failed */ 4192 if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) { 4193 ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n", 4194 __func__); 4195 status = QLA_ERROR; 4196 goto exit_init_adapter_failure; 4197 } 4198 4199 /* Since interrupts are registered in start_firmware for 4200 * 8xxx, release them here if initialize_adapter fails 4201 * and retry adapter initialization */ 4202 qla4xxx_free_irqs(ha); 4203 4204 exit_init_adapter_failure: 4205 return status; 4206 } 4207