1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip AXI PCIe Bridge host controller driver
4 *
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
6 *
7 * Author: Daire McNamara <daire.mcnamara@microchip.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/module.h>
15 #include <linux/msi.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci-ecam.h>
19 #include <linux/platform_device.h>
20
21 #include "../../pci.h"
22 #include "pcie-plda.h"
23
24 /* PCIe Bridge Phy and Controller Phy offsets */
25 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u
26 #define MC_PCIE1_CTRL_ADDR 0x0000a000u
27
28 #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
29 #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
30
31 /* PCIe Controller Phy Regs */
32 #define SEC_ERROR_EVENT_CNT 0x20
33 #define DED_ERROR_EVENT_CNT 0x24
34 #define SEC_ERROR_INT 0x28
35 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
36 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
37 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
38 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
39 #define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0)
40 #define NUM_SEC_ERROR_INTS (4)
41 #define SEC_ERROR_INT_MASK 0x2c
42 #define DED_ERROR_INT 0x30
43 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
44 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
45 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
46 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
47 #define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0)
48 #define NUM_DED_ERROR_INTS (4)
49 #define DED_ERROR_INT_MASK 0x34
50 #define ECC_CONTROL 0x38
51 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
52 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
53 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
54 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
55 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
56 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
57 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
58 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
59 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
60 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
61 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
62 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
63 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
64 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
65 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
66 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
67 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
68 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
69 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
70 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
71 #define PCIE_EVENT_INT 0x14c
72 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
73 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
74 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
75 #define PCIE_EVENT_INT_MASK GENMASK(2, 0)
76 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
77 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
78 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
79 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
80 #define PCIE_EVENT_INT_ENB_SHIFT 16
81 #define NUM_PCIE_EVENTS (3)
82
83 /* PCIe Config space MSI capability structure */
84 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u
85
86 /* Events */
87 #define EVENT_PCIE_L2_EXIT 0
88 #define EVENT_PCIE_HOTRST_EXIT 1
89 #define EVENT_PCIE_DLUP_EXIT 2
90 #define EVENT_SEC_TX_RAM_SEC_ERR 3
91 #define EVENT_SEC_RX_RAM_SEC_ERR 4
92 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5
93 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6
94 #define EVENT_DED_TX_RAM_DED_ERR 7
95 #define EVENT_DED_RX_RAM_DED_ERR 8
96 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9
97 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10
98 #define EVENT_LOCAL_DMA_END_ENGINE_0 11
99 #define EVENT_LOCAL_DMA_END_ENGINE_1 12
100 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
101 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14
102 #define NUM_MC_EVENTS 15
103 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR)
104 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR)
105 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR)
106 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL)
107 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR)
108 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR)
109 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR)
110 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL)
111 #define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX)
112 #define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI)
113 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT)
114 #define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS)
115 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR)
116 #define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM)
117
118 #define PCIE_EVENT_CAUSE(x, s) \
119 [EVENT_PCIE_ ## x] = { __stringify(x), s }
120
121 #define SEC_ERROR_CAUSE(x, s) \
122 [EVENT_SEC_ ## x] = { __stringify(x), s }
123
124 #define DED_ERROR_CAUSE(x, s) \
125 [EVENT_DED_ ## x] = { __stringify(x), s }
126
127 #define LOCAL_EVENT_CAUSE(x, s) \
128 [EVENT_LOCAL_ ## x] = { __stringify(x), s }
129
130 #define PCIE_EVENT(x) \
131 .base = MC_PCIE_CTRL_ADDR, \
132 .offset = PCIE_EVENT_INT, \
133 .mask_offset = PCIE_EVENT_INT, \
134 .mask_high = 1, \
135 .mask = PCIE_EVENT_INT_ ## x ## _INT, \
136 .enb_mask = PCIE_EVENT_INT_ENB_MASK
137
138 #define SEC_EVENT(x) \
139 .base = MC_PCIE_CTRL_ADDR, \
140 .offset = SEC_ERROR_INT, \
141 .mask_offset = SEC_ERROR_INT_MASK, \
142 .mask = SEC_ERROR_INT_ ## x ## _INT, \
143 .mask_high = 1, \
144 .enb_mask = 0
145
146 #define DED_EVENT(x) \
147 .base = MC_PCIE_CTRL_ADDR, \
148 .offset = DED_ERROR_INT, \
149 .mask_offset = DED_ERROR_INT_MASK, \
150 .mask_high = 1, \
151 .mask = DED_ERROR_INT_ ## x ## _INT, \
152 .enb_mask = 0
153
154 #define LOCAL_EVENT(x) \
155 .base = MC_PCIE_BRIDGE_ADDR, \
156 .offset = ISTATUS_LOCAL, \
157 .mask_offset = IMASK_LOCAL, \
158 .mask_high = 0, \
159 .mask = x ## _MASK, \
160 .enb_mask = 0
161
162 #define PCIE_EVENT_TO_EVENT_MAP(x) \
163 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x }
164
165 #define SEC_ERROR_TO_EVENT_MAP(x) \
166 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x }
167
168 #define DED_ERROR_TO_EVENT_MAP(x) \
169 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x }
170
171 #define LOCAL_STATUS_TO_EVENT_MAP(x) \
172 { x ## _MASK, EVENT_LOCAL_ ## x }
173
174 struct event_map {
175 u32 reg_mask;
176 u32 event_bit;
177 };
178
179
180 struct mc_pcie {
181 struct plda_pcie_rp plda;
182 void __iomem *axi_base_addr;
183 };
184
185 struct cause {
186 const char *sym;
187 const char *str;
188 };
189
190 static const struct cause event_cause[NUM_EVENTS] = {
191 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"),
192 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"),
193 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"),
194 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"),
195 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"),
196 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"),
197 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"),
198 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"),
199 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"),
200 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"),
201 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"),
202 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"),
203 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
204 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"),
205 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"),
206 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"),
207 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"),
208 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"),
209 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"),
210 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"),
211 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"),
212 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"),
213 };
214
215 static struct event_map pcie_event_to_event[] = {
216 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT),
217 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT),
218 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT),
219 };
220
221 static struct event_map sec_error_to_event[] = {
222 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR),
223 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR),
224 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR),
225 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR),
226 };
227
228 static struct event_map ded_error_to_event[] = {
229 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR),
230 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR),
231 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR),
232 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR),
233 };
234
235 static struct event_map local_status_to_event[] = {
236 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0),
237 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1),
238 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0),
239 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1),
240 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR),
241 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR),
242 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR),
243 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL),
244 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR),
245 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR),
246 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR),
247 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL),
248 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX),
249 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI),
250 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT),
251 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS),
252 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR),
253 };
254
255 static struct {
256 u32 base;
257 u32 offset;
258 u32 mask;
259 u32 shift;
260 u32 enb_mask;
261 u32 mask_high;
262 u32 mask_offset;
263 } event_descs[] = {
264 { PCIE_EVENT(L2_EXIT) },
265 { PCIE_EVENT(HOTRST_EXIT) },
266 { PCIE_EVENT(DLUP_EXIT) },
267 { SEC_EVENT(TX_RAM_SEC_ERR) },
268 { SEC_EVENT(RX_RAM_SEC_ERR) },
269 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) },
270 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) },
271 { DED_EVENT(TX_RAM_DED_ERR) },
272 { DED_EVENT(RX_RAM_DED_ERR) },
273 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) },
274 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) },
275 { LOCAL_EVENT(DMA_END_ENGINE_0) },
276 { LOCAL_EVENT(DMA_END_ENGINE_1) },
277 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) },
278 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) },
279 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) },
280 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) },
281 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) },
282 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) },
283 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) },
284 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) },
285 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) },
286 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) },
287 { LOCAL_EVENT(PM_MSI_INT_INTX) },
288 { LOCAL_EVENT(PM_MSI_INT_MSI) },
289 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) },
290 { LOCAL_EVENT(PM_MSI_INT_EVENTS) },
291 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) },
292 };
293
294 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };
295
296 static struct mc_pcie *port;
297
mc_pcie_enable_msi(struct mc_pcie * port,void __iomem * ecam)298 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam)
299 {
300 struct plda_msi *msi = &port->plda.msi;
301 u16 reg;
302 u8 queue_size;
303
304 /* Fixup MSI enable flag */
305 reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
306 reg |= PCI_MSI_FLAGS_ENABLE;
307 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
308
309 /* Fixup PCI MSI queue flags */
310 queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg);
311 reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size);
312 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
313
314 /* Fixup MSI addr fields */
315 writel_relaxed(lower_32_bits(msi->vector_phy),
316 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO);
317 writel_relaxed(upper_32_bits(msi->vector_phy),
318 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI);
319 }
320
reg_to_event(u32 reg,struct event_map field)321 static inline u32 reg_to_event(u32 reg, struct event_map field)
322 {
323 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;
324 }
325
pcie_events(struct mc_pcie * port)326 static u32 pcie_events(struct mc_pcie *port)
327 {
328 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
329 u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT);
330 u32 val = 0;
331 int i;
332
333 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++)
334 val |= reg_to_event(reg, pcie_event_to_event[i]);
335
336 return val;
337 }
338
sec_errors(struct mc_pcie * port)339 static u32 sec_errors(struct mc_pcie *port)
340 {
341 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
342 u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT);
343 u32 val = 0;
344 int i;
345
346 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++)
347 val |= reg_to_event(reg, sec_error_to_event[i]);
348
349 return val;
350 }
351
ded_errors(struct mc_pcie * port)352 static u32 ded_errors(struct mc_pcie *port)
353 {
354 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
355 u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT);
356 u32 val = 0;
357 int i;
358
359 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++)
360 val |= reg_to_event(reg, ded_error_to_event[i]);
361
362 return val;
363 }
364
local_events(struct mc_pcie * port)365 static u32 local_events(struct mc_pcie *port)
366 {
367 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
368 u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
369 u32 val = 0;
370 int i;
371
372 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++)
373 val |= reg_to_event(reg, local_status_to_event[i]);
374
375 return val;
376 }
377
mc_get_events(struct plda_pcie_rp * port)378 static u32 mc_get_events(struct plda_pcie_rp *port)
379 {
380 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
381 u32 events = 0;
382
383 events |= pcie_events(mc_port);
384 events |= sec_errors(mc_port);
385 events |= ded_errors(mc_port);
386 events |= local_events(mc_port);
387
388 return events;
389 }
390
mc_event_handler(int irq,void * dev_id)391 static irqreturn_t mc_event_handler(int irq, void *dev_id)
392 {
393 struct plda_pcie_rp *port = dev_id;
394 struct device *dev = port->dev;
395 struct irq_data *data;
396
397 data = irq_domain_get_irq_data(port->event_domain, irq);
398
399 if (event_cause[data->hwirq].str)
400 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str);
401 else
402 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq);
403
404 return IRQ_HANDLED;
405 }
406
mc_ack_event_irq(struct irq_data * data)407 static void mc_ack_event_irq(struct irq_data *data)
408 {
409 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
410 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
411 u32 event = data->hwirq;
412 void __iomem *addr;
413 u32 mask;
414
415 addr = mc_port->axi_base_addr + event_descs[event].base +
416 event_descs[event].offset;
417 mask = event_descs[event].mask;
418 mask |= event_descs[event].enb_mask;
419
420 writel_relaxed(mask, addr);
421 }
422
mc_mask_event_irq(struct irq_data * data)423 static void mc_mask_event_irq(struct irq_data *data)
424 {
425 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
426 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
427 u32 event = data->hwirq;
428 void __iomem *addr;
429 u32 mask;
430 u32 val;
431
432 addr = mc_port->axi_base_addr + event_descs[event].base +
433 event_descs[event].mask_offset;
434 mask = event_descs[event].mask;
435 if (event_descs[event].enb_mask) {
436 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
437 mask &= PCIE_EVENT_INT_ENB_MASK;
438 }
439
440 if (!event_descs[event].mask_high)
441 mask = ~mask;
442
443 raw_spin_lock(&port->lock);
444 val = readl_relaxed(addr);
445 if (event_descs[event].mask_high)
446 val |= mask;
447 else
448 val &= mask;
449
450 writel_relaxed(val, addr);
451 raw_spin_unlock(&port->lock);
452 }
453
mc_unmask_event_irq(struct irq_data * data)454 static void mc_unmask_event_irq(struct irq_data *data)
455 {
456 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
457 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
458 u32 event = data->hwirq;
459 void __iomem *addr;
460 u32 mask;
461 u32 val;
462
463 addr = mc_port->axi_base_addr + event_descs[event].base +
464 event_descs[event].mask_offset;
465 mask = event_descs[event].mask;
466
467 if (event_descs[event].enb_mask)
468 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
469
470 if (event_descs[event].mask_high)
471 mask = ~mask;
472
473 if (event_descs[event].enb_mask)
474 mask &= PCIE_EVENT_INT_ENB_MASK;
475
476 raw_spin_lock(&port->lock);
477 val = readl_relaxed(addr);
478 if (event_descs[event].mask_high)
479 val &= mask;
480 else
481 val |= mask;
482 writel_relaxed(val, addr);
483 raw_spin_unlock(&port->lock);
484 }
485
486 static struct irq_chip mc_event_irq_chip = {
487 .name = "Microchip PCIe EVENT",
488 .irq_ack = mc_ack_event_irq,
489 .irq_mask = mc_mask_event_irq,
490 .irq_unmask = mc_unmask_event_irq,
491 };
492
mc_pcie_deinit_clk(void * data)493 static inline void mc_pcie_deinit_clk(void *data)
494 {
495 struct clk *clk = data;
496
497 clk_disable_unprepare(clk);
498 }
499
mc_pcie_init_clk(struct device * dev,const char * id)500 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id)
501 {
502 struct clk *clk;
503 int ret;
504
505 clk = devm_clk_get_optional(dev, id);
506 if (IS_ERR(clk))
507 return clk;
508 if (!clk)
509 return clk;
510
511 ret = clk_prepare_enable(clk);
512 if (ret)
513 return ERR_PTR(ret);
514
515 devm_add_action_or_reset(dev, mc_pcie_deinit_clk, clk);
516
517 return clk;
518 }
519
mc_pcie_init_clks(struct device * dev)520 static int mc_pcie_init_clks(struct device *dev)
521 {
522 int i;
523 struct clk *fic;
524
525 /*
526 * PCIe may be clocked via Fabric Interface using between 1 and 4
527 * clocks. Scan DT for clocks and enable them if present
528 */
529 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) {
530 fic = mc_pcie_init_clk(dev, poss_clks[i]);
531 if (IS_ERR(fic))
532 return PTR_ERR(fic);
533 }
534
535 return 0;
536 }
537
mc_request_event_irq(struct plda_pcie_rp * plda,int event_irq,int event)538 static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq,
539 int event)
540 {
541 return devm_request_irq(plda->dev, event_irq, mc_event_handler,
542 0, event_cause[event].sym, plda);
543 }
544
545 static const struct plda_event_ops mc_event_ops = {
546 .get_events = mc_get_events,
547 };
548
549 static const struct plda_event mc_event = {
550 .request_event_irq = mc_request_event_irq,
551 .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX,
552 .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI,
553 };
554
mc_clear_secs(struct mc_pcie * port)555 static inline void mc_clear_secs(struct mc_pcie *port)
556 {
557 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
558
559 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
560 SEC_ERROR_INT);
561 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT);
562 }
563
mc_clear_deds(struct mc_pcie * port)564 static inline void mc_clear_deds(struct mc_pcie *port)
565 {
566 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
567
568 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
569 DED_ERROR_INT);
570 writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT);
571 }
572
mc_disable_interrupts(struct mc_pcie * port)573 static void mc_disable_interrupts(struct mc_pcie *port)
574 {
575 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
576 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
577 u32 val;
578
579 /* Ensure ECC bypass is enabled */
580 val = ECC_CONTROL_TX_RAM_ECC_BYPASS |
581 ECC_CONTROL_RX_RAM_ECC_BYPASS |
582 ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS |
583 ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS;
584 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
585
586 /* Disable SEC errors and clear any outstanding */
587 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
588 SEC_ERROR_INT_MASK);
589 mc_clear_secs(port);
590
591 /* Disable DED errors and clear any outstanding */
592 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
593 DED_ERROR_INT_MASK);
594 mc_clear_deds(port);
595
596 /* Disable local interrupts and clear any outstanding */
597 writel_relaxed(0, bridge_base_addr + IMASK_LOCAL);
598 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL);
599 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI);
600
601 /* Disable PCIe events and clear any outstanding */
602 val = PCIE_EVENT_INT_L2_EXIT_INT |
603 PCIE_EVENT_INT_HOTRST_EXIT_INT |
604 PCIE_EVENT_INT_DLUP_EXIT_INT |
605 PCIE_EVENT_INT_L2_EXIT_INT_MASK |
606 PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK |
607 PCIE_EVENT_INT_DLUP_EXIT_INT_MASK;
608 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
609
610 /* Disable host interrupts and clear any outstanding */
611 writel_relaxed(0, bridge_base_addr + IMASK_HOST);
612 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
613 }
614
mc_platform_init(struct pci_config_window * cfg)615 static int mc_platform_init(struct pci_config_window *cfg)
616 {
617 struct device *dev = cfg->parent;
618 struct platform_device *pdev = to_platform_device(dev);
619 struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
620 void __iomem *bridge_base_addr =
621 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
622 int ret;
623
624 /* Configure address translation table 0 for PCIe config space */
625 plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,
626 cfg->res.start,
627 resource_size(&cfg->res));
628
629 /* Need some fixups in config space */
630 mc_pcie_enable_msi(port, cfg->win);
631
632 /* Configure non-config space outbound ranges */
633 ret = plda_pcie_setup_iomems(bridge, &port->plda);
634 if (ret)
635 return ret;
636
637 port->plda.event_ops = &mc_event_ops;
638 port->plda.event_irq_chip = &mc_event_irq_chip;
639 port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0);
640
641 /* Address translation is up; safe to enable interrupts */
642 ret = plda_init_interrupts(pdev, &port->plda, &mc_event);
643 if (ret)
644 return ret;
645
646 return 0;
647 }
648
mc_host_probe(struct platform_device * pdev)649 static int mc_host_probe(struct platform_device *pdev)
650 {
651 struct device *dev = &pdev->dev;
652 void __iomem *bridge_base_addr;
653 struct plda_pcie_rp *plda;
654 int ret;
655 u32 val;
656
657 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
658 if (!port)
659 return -ENOMEM;
660
661 plda = &port->plda;
662 plda->dev = dev;
663
664 port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);
665 if (IS_ERR(port->axi_base_addr))
666 return PTR_ERR(port->axi_base_addr);
667
668 mc_disable_interrupts(port);
669
670 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
671 plda->bridge_addr = bridge_base_addr;
672 plda->num_events = NUM_EVENTS;
673
674 /* Allow enabling MSI by disabling MSI-X */
675 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
676 val &= ~MSIX_CAP_MASK;
677 writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);
678
679 /* Pick num vectors from bitfile programmed onto FPGA fabric */
680 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
681 val &= NUM_MSI_MSGS_MASK;
682 val >>= NUM_MSI_MSGS_SHIFT;
683
684 plda->msi.num_vectors = 1 << val;
685
686 /* Pick vector address from design */
687 plda->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);
688
689 ret = mc_pcie_init_clks(dev);
690 if (ret) {
691 dev_err(dev, "failed to get clock resources, error %d\n", ret);
692 return -ENODEV;
693 }
694
695 return pci_host_common_probe(pdev);
696 }
697
698 static const struct pci_ecam_ops mc_ecam_ops = {
699 .init = mc_platform_init,
700 .pci_ops = {
701 .map_bus = pci_ecam_map_bus,
702 .read = pci_generic_config_read,
703 .write = pci_generic_config_write,
704 }
705 };
706
707 static const struct of_device_id mc_pcie_of_match[] = {
708 {
709 .compatible = "microchip,pcie-host-1.0",
710 .data = &mc_ecam_ops,
711 },
712 {},
713 };
714
715 MODULE_DEVICE_TABLE(of, mc_pcie_of_match);
716
717 static struct platform_driver mc_pcie_driver = {
718 .probe = mc_host_probe,
719 .driver = {
720 .name = "microchip-pcie",
721 .of_match_table = mc_pcie_of_match,
722 .suppress_bind_attrs = true,
723 },
724 };
725
726 builtin_platform_driver(mc_pcie_driver);
727 MODULE_LICENSE("GPL");
728 MODULE_DESCRIPTION("Microchip PCIe host controller driver");
729 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
730