1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
4 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/firmware.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/iommu.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/remoteproc.h>
24 #include <linux/reset.h>
25 #include <linux/soc/qcom/mdt_loader.h>
26 #include <linux/soc/qcom/smem.h>
27 #include <linux/soc/qcom/smem_state.h>
28
29 #include "qcom_common.h"
30 #include "qcom_pil_info.h"
31 #include "qcom_q6v5.h"
32 #include "remoteproc_internal.h"
33
34 /* time out value */
35 #define ACK_TIMEOUT 1000
36 #define ACK_TIMEOUT_US 1000000
37 #define BOOT_FSM_TIMEOUT 10000
38 /* mask values */
39 #define EVB_MASK GENMASK(27, 4)
40 /*QDSP6SS register offsets*/
41 #define RST_EVB_REG 0x10
42 #define CORE_START_REG 0x400
43 #define BOOT_CMD_REG 0x404
44 #define BOOT_STATUS_REG 0x408
45 #define RET_CFG_REG 0x1C
46 /*TCSR register offsets*/
47 #define LPASS_MASTER_IDLE_REG 0x8
48 #define LPASS_HALTACK_REG 0x4
49 #define LPASS_PWR_ON_REG 0x10
50 #define LPASS_HALTREQ_REG 0x0
51
52 #define SID_MASK_DEFAULT 0xF
53
54 #define QDSP6SS_XO_CBCR 0x38
55 #define QDSP6SS_CORE_CBCR 0x20
56 #define QDSP6SS_SLEEP_CBCR 0x3c
57
58 #define LPASS_BOOT_CORE_START BIT(0)
59 #define LPASS_BOOT_CMD_START BIT(0)
60 #define LPASS_EFUSE_Q6SS_EVB_SEL 0x0
61
62 struct adsp_pil_data {
63 int crash_reason_smem;
64 const char *firmware_name;
65
66 const char *ssr_name;
67 const char *sysmon_name;
68 int ssctl_id;
69 bool is_wpss;
70 bool has_iommu;
71 bool auto_boot;
72
73 const char **clk_ids;
74 int num_clks;
75 const char **pd_names;
76 unsigned int num_pds;
77 const char *load_state;
78 };
79
80 struct qcom_adsp {
81 struct device *dev;
82 struct rproc *rproc;
83
84 struct qcom_q6v5 q6v5;
85
86 struct clk *xo;
87
88 int num_clks;
89 struct clk_bulk_data *clks;
90
91 void __iomem *qdsp6ss_base;
92 void __iomem *lpass_efuse;
93
94 struct reset_control *pdc_sync_reset;
95 struct reset_control *restart;
96
97 struct regmap *halt_map;
98 unsigned int halt_lpass;
99
100 int crash_reason_smem;
101 const char *info_name;
102
103 struct completion start_done;
104 struct completion stop_done;
105
106 phys_addr_t mem_phys;
107 unsigned long iova;
108 phys_addr_t mem_reloc;
109 void __iomem *mem_region;
110 size_t mem_size;
111 bool has_iommu;
112
113 struct dev_pm_domain_list *pd_list;
114
115 struct qcom_rproc_glink glink_subdev;
116 struct qcom_rproc_pdm pdm_subdev;
117 struct qcom_rproc_ssr ssr_subdev;
118 struct qcom_sysmon *sysmon;
119
120 int (*shutdown)(struct qcom_adsp *adsp);
121 };
122
qcom_rproc_pds_attach(struct qcom_adsp * adsp,const char ** pd_names,unsigned int num_pds)123 static int qcom_rproc_pds_attach(struct qcom_adsp *adsp, const char **pd_names,
124 unsigned int num_pds)
125 {
126 struct device *dev = adsp->dev;
127 struct dev_pm_domain_attach_data pd_data = {
128 .pd_names = pd_names,
129 .num_pd_names = num_pds,
130 };
131 int ret;
132
133 /* Handle single power domain */
134 if (dev->pm_domain)
135 goto out;
136
137 if (!pd_names)
138 return 0;
139
140 ret = dev_pm_domain_attach_list(dev, &pd_data, &adsp->pd_list);
141 if (ret < 0)
142 return ret;
143
144 out:
145 pm_runtime_enable(dev);
146 return 0;
147 }
148
qcom_rproc_pds_detach(struct qcom_adsp * adsp)149 static void qcom_rproc_pds_detach(struct qcom_adsp *adsp)
150 {
151 struct device *dev = adsp->dev;
152 struct dev_pm_domain_list *pds = adsp->pd_list;
153
154 dev_pm_domain_detach_list(pds);
155
156 if (dev->pm_domain || pds)
157 pm_runtime_disable(adsp->dev);
158 }
159
qcom_rproc_pds_enable(struct qcom_adsp * adsp)160 static int qcom_rproc_pds_enable(struct qcom_adsp *adsp)
161 {
162 struct device *dev = adsp->dev;
163 struct dev_pm_domain_list *pds = adsp->pd_list;
164 int ret, i = 0;
165
166 if (!dev->pm_domain && !pds)
167 return 0;
168
169 if (dev->pm_domain)
170 dev_pm_genpd_set_performance_state(dev, INT_MAX);
171
172 while (pds && i < pds->num_pds) {
173 dev_pm_genpd_set_performance_state(pds->pd_devs[i], INT_MAX);
174 i++;
175 }
176
177 ret = pm_runtime_resume_and_get(dev);
178 if (ret < 0) {
179 while (pds && i > 0) {
180 i--;
181 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0);
182 }
183
184 if (dev->pm_domain)
185 dev_pm_genpd_set_performance_state(dev, 0);
186 }
187
188 return ret;
189 }
190
qcom_rproc_pds_disable(struct qcom_adsp * adsp)191 static void qcom_rproc_pds_disable(struct qcom_adsp *adsp)
192 {
193 struct device *dev = adsp->dev;
194 struct dev_pm_domain_list *pds = adsp->pd_list;
195 int i = 0;
196
197 if (!dev->pm_domain && !pds)
198 return;
199
200 if (dev->pm_domain)
201 dev_pm_genpd_set_performance_state(dev, 0);
202
203 while (pds && i < pds->num_pds) {
204 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0);
205 i++;
206 }
207
208 pm_runtime_put(dev);
209 }
210
qcom_wpss_shutdown(struct qcom_adsp * adsp)211 static int qcom_wpss_shutdown(struct qcom_adsp *adsp)
212 {
213 unsigned int val;
214
215 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
216
217 /* Wait for halt ACK from QDSP6 */
218 regmap_read_poll_timeout(adsp->halt_map,
219 adsp->halt_lpass + LPASS_HALTACK_REG, val,
220 val, 1000, ACK_TIMEOUT_US);
221
222 /* Assert the WPSS PDC Reset */
223 reset_control_assert(adsp->pdc_sync_reset);
224
225 /* Place the WPSS processor into reset */
226 reset_control_assert(adsp->restart);
227
228 /* wait after asserting subsystem restart from AOSS */
229 usleep_range(200, 205);
230
231 /* Remove the WPSS reset */
232 reset_control_deassert(adsp->restart);
233
234 /* De-assert the WPSS PDC Reset */
235 reset_control_deassert(adsp->pdc_sync_reset);
236
237 usleep_range(100, 105);
238
239 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
240
241 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
242
243 /* Wait for halt ACK from QDSP6 */
244 regmap_read_poll_timeout(adsp->halt_map,
245 adsp->halt_lpass + LPASS_HALTACK_REG, val,
246 !val, 1000, ACK_TIMEOUT_US);
247
248 return 0;
249 }
250
qcom_adsp_shutdown(struct qcom_adsp * adsp)251 static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
252 {
253 unsigned long timeout;
254 unsigned int val;
255 int ret;
256
257 /* Reset the retention logic */
258 val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
259 val |= 0x1;
260 writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
261
262 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
263
264 /* QDSP6 master port needs to be explicitly halted */
265 ret = regmap_read(adsp->halt_map,
266 adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
267 if (ret || !val)
268 goto reset;
269
270 ret = regmap_read(adsp->halt_map,
271 adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
272 &val);
273 if (ret || val)
274 goto reset;
275
276 regmap_write(adsp->halt_map,
277 adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
278
279 /* Wait for halt ACK from QDSP6 */
280 timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
281 for (;;) {
282 ret = regmap_read(adsp->halt_map,
283 adsp->halt_lpass + LPASS_HALTACK_REG, &val);
284 if (ret || val || time_after(jiffies, timeout))
285 break;
286
287 usleep_range(1000, 1100);
288 }
289
290 ret = regmap_read(adsp->halt_map,
291 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
292 if (ret || !val)
293 dev_err(adsp->dev, "port failed halt\n");
294
295 reset:
296 /* Assert the LPASS PDC Reset */
297 reset_control_assert(adsp->pdc_sync_reset);
298 /* Place the LPASS processor into reset */
299 reset_control_assert(adsp->restart);
300 /* wait after asserting subsystem restart from AOSS */
301 usleep_range(200, 300);
302
303 /* Clear the halt request for the AXIM and AHBM for Q6 */
304 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
305
306 /* De-assert the LPASS PDC Reset */
307 reset_control_deassert(adsp->pdc_sync_reset);
308 /* Remove the LPASS reset */
309 reset_control_deassert(adsp->restart);
310 /* wait after de-asserting subsystem restart from AOSS */
311 usleep_range(200, 300);
312
313 return 0;
314 }
315
adsp_load(struct rproc * rproc,const struct firmware * fw)316 static int adsp_load(struct rproc *rproc, const struct firmware *fw)
317 {
318 struct qcom_adsp *adsp = rproc->priv;
319 int ret;
320
321 ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware,
322 (__force void *)adsp->mem_region, adsp->mem_phys,
323 adsp->mem_size, &adsp->mem_reloc);
324 if (ret)
325 return ret;
326
327 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
328
329 return 0;
330 }
331
adsp_unmap_carveout(struct rproc * rproc)332 static void adsp_unmap_carveout(struct rproc *rproc)
333 {
334 struct qcom_adsp *adsp = rproc->priv;
335
336 if (adsp->has_iommu)
337 iommu_unmap(rproc->domain, adsp->iova, adsp->mem_size);
338 }
339
adsp_map_carveout(struct rproc * rproc)340 static int adsp_map_carveout(struct rproc *rproc)
341 {
342 struct qcom_adsp *adsp = rproc->priv;
343 struct of_phandle_args args;
344 long long sid;
345 int ret;
346
347 if (!adsp->has_iommu)
348 return 0;
349
350 if (!rproc->domain)
351 return -EINVAL;
352
353 ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args);
354 if (ret < 0)
355 return ret;
356
357 sid = args.args[0] & SID_MASK_DEFAULT;
358 of_node_put(args.np);
359
360 /* Add SID configuration for ADSP Firmware to SMMU */
361 adsp->iova = adsp->mem_phys | (sid << 32);
362
363 ret = iommu_map(rproc->domain, adsp->iova, adsp->mem_phys,
364 adsp->mem_size, IOMMU_READ | IOMMU_WRITE,
365 GFP_KERNEL);
366 if (ret) {
367 dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");
368 return ret;
369 }
370
371 return 0;
372 }
373
adsp_start(struct rproc * rproc)374 static int adsp_start(struct rproc *rproc)
375 {
376 struct qcom_adsp *adsp = rproc->priv;
377 int ret;
378 unsigned int val;
379
380 ret = qcom_q6v5_prepare(&adsp->q6v5);
381 if (ret)
382 return ret;
383
384 ret = adsp_map_carveout(rproc);
385 if (ret) {
386 dev_err(adsp->dev, "ADSP smmu mapping failed\n");
387 goto disable_irqs;
388 }
389
390 ret = clk_prepare_enable(adsp->xo);
391 if (ret)
392 goto adsp_smmu_unmap;
393
394 ret = qcom_rproc_pds_enable(adsp);
395 if (ret < 0)
396 goto disable_xo_clk;
397
398 ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
399 if (ret) {
400 dev_err(adsp->dev, "adsp clk_enable failed\n");
401 goto disable_power_domain;
402 }
403
404 /* Enable the XO clock */
405 writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
406
407 /* Enable the QDSP6SS sleep clock */
408 writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
409
410 /* Enable the QDSP6 core clock */
411 writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
412
413 /* Program boot address */
414 writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
415
416 if (adsp->lpass_efuse)
417 writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);
418
419 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
420 writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);
421
422 /* Trigger boot FSM to start QDSP6 */
423 writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);
424
425 /* Wait for core to come out of reset */
426 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
427 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
428 if (ret) {
429 dev_err(adsp->dev, "failed to bootup adsp\n");
430 goto disable_adsp_clks;
431 }
432
433 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
434 if (ret == -ETIMEDOUT) {
435 dev_err(adsp->dev, "start timed out\n");
436 goto disable_adsp_clks;
437 }
438
439 return 0;
440
441 disable_adsp_clks:
442 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
443 disable_power_domain:
444 qcom_rproc_pds_disable(adsp);
445 disable_xo_clk:
446 clk_disable_unprepare(adsp->xo);
447 adsp_smmu_unmap:
448 adsp_unmap_carveout(rproc);
449 disable_irqs:
450 qcom_q6v5_unprepare(&adsp->q6v5);
451
452 return ret;
453 }
454
qcom_adsp_pil_handover(struct qcom_q6v5 * q6v5)455 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
456 {
457 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
458
459 clk_disable_unprepare(adsp->xo);
460 qcom_rproc_pds_disable(adsp);
461 }
462
adsp_stop(struct rproc * rproc)463 static int adsp_stop(struct rproc *rproc)
464 {
465 struct qcom_adsp *adsp = rproc->priv;
466 int handover;
467 int ret;
468
469 ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);
470 if (ret == -ETIMEDOUT)
471 dev_err(adsp->dev, "timed out on wait\n");
472
473 ret = adsp->shutdown(adsp);
474 if (ret)
475 dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
476
477 adsp_unmap_carveout(rproc);
478
479 handover = qcom_q6v5_unprepare(&adsp->q6v5);
480 if (handover)
481 qcom_adsp_pil_handover(&adsp->q6v5);
482
483 return ret;
484 }
485
adsp_da_to_va(struct rproc * rproc,u64 da,size_t len,bool * is_iomem)486 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
487 {
488 struct qcom_adsp *adsp = rproc->priv;
489 int offset;
490
491 offset = da - adsp->mem_reloc;
492 if (offset < 0 || offset + len > adsp->mem_size)
493 return NULL;
494
495 return (__force void *)adsp->mem_region + offset;
496 }
497
adsp_parse_firmware(struct rproc * rproc,const struct firmware * fw)498 static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw)
499 {
500 struct qcom_adsp *adsp = rproc->priv;
501 int ret;
502
503 ret = qcom_register_dump_segments(rproc, fw);
504 if (ret) {
505 dev_err(&rproc->dev, "Error in registering dump segments\n");
506 return ret;
507 }
508
509 if (adsp->has_iommu) {
510 ret = rproc_elf_load_rsc_table(rproc, fw);
511 if (ret) {
512 dev_err(&rproc->dev, "Error in loading resource table\n");
513 return ret;
514 }
515 }
516 return 0;
517 }
518
adsp_panic(struct rproc * rproc)519 static unsigned long adsp_panic(struct rproc *rproc)
520 {
521 struct qcom_adsp *adsp = rproc->priv;
522
523 return qcom_q6v5_panic(&adsp->q6v5);
524 }
525
526 static const struct rproc_ops adsp_ops = {
527 .start = adsp_start,
528 .stop = adsp_stop,
529 .da_to_va = adsp_da_to_va,
530 .parse_fw = adsp_parse_firmware,
531 .load = adsp_load,
532 .panic = adsp_panic,
533 };
534
adsp_init_clock(struct qcom_adsp * adsp,const char ** clk_ids)535 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
536 {
537 int num_clks = 0;
538 int i;
539
540 adsp->xo = devm_clk_get(adsp->dev, "xo");
541 if (IS_ERR(adsp->xo))
542 return dev_err_probe(adsp->dev, PTR_ERR(adsp->xo), "failed to get xo clock");
543
544 for (i = 0; clk_ids[i]; i++)
545 num_clks++;
546
547 adsp->num_clks = num_clks;
548 adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
549 sizeof(*adsp->clks), GFP_KERNEL);
550 if (!adsp->clks)
551 return -ENOMEM;
552
553 for (i = 0; i < adsp->num_clks; i++)
554 adsp->clks[i].id = clk_ids[i];
555
556 return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
557 }
558
adsp_init_reset(struct qcom_adsp * adsp)559 static int adsp_init_reset(struct qcom_adsp *adsp)
560 {
561 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
562 "pdc_sync");
563 if (IS_ERR(adsp->pdc_sync_reset)) {
564 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
565 return PTR_ERR(adsp->pdc_sync_reset);
566 }
567
568 adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
569
570 /* Fall back to the old "cc_lpass" if "restart" is absent */
571 if (!adsp->restart)
572 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
573
574 if (IS_ERR(adsp->restart)) {
575 dev_err(adsp->dev, "failed to acquire restart\n");
576 return PTR_ERR(adsp->restart);
577 }
578
579 return 0;
580 }
581
adsp_init_mmio(struct qcom_adsp * adsp,struct platform_device * pdev)582 static int adsp_init_mmio(struct qcom_adsp *adsp,
583 struct platform_device *pdev)
584 {
585 struct resource *efuse_region;
586 struct device_node *syscon;
587 int ret;
588
589 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0);
590 if (IS_ERR(adsp->qdsp6ss_base)) {
591 dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
592 return PTR_ERR(adsp->qdsp6ss_base);
593 }
594
595 efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1);
596 if (!efuse_region) {
597 adsp->lpass_efuse = NULL;
598 dev_dbg(adsp->dev, "failed to get efuse memory region\n");
599 } else {
600 adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region);
601 if (IS_ERR(adsp->lpass_efuse)) {
602 dev_err(adsp->dev, "failed to map efuse registers\n");
603 return PTR_ERR(adsp->lpass_efuse);
604 }
605 }
606 syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
607 if (!syscon) {
608 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
609 return -EINVAL;
610 }
611
612 adsp->halt_map = syscon_node_to_regmap(syscon);
613 of_node_put(syscon);
614 if (IS_ERR(adsp->halt_map))
615 return PTR_ERR(adsp->halt_map);
616
617 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
618 1, &adsp->halt_lpass);
619 if (ret < 0) {
620 dev_err(&pdev->dev, "no offset in syscon\n");
621 return ret;
622 }
623
624 return 0;
625 }
626
adsp_alloc_memory_region(struct qcom_adsp * adsp)627 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
628 {
629 int ret;
630 struct resource res;
631
632 ret = of_reserved_mem_region_to_resource(adsp->dev->of_node, 0, &res);
633 if (ret) {
634 dev_err(adsp->dev, "unable to resolve memory-region\n");
635 return ret;
636 }
637
638 adsp->mem_phys = adsp->mem_reloc = res.start;
639 adsp->mem_size = resource_size(&res);
640 adsp->mem_region = devm_ioremap_resource_wc(adsp->dev, &res);
641 if (IS_ERR(adsp->mem_region)) {
642 dev_err(adsp->dev, "unable to map memory region: %pR\n", &res);
643 return PTR_ERR(adsp->mem_region);
644
645 }
646
647 return 0;
648 }
649
adsp_probe(struct platform_device * pdev)650 static int adsp_probe(struct platform_device *pdev)
651 {
652 const struct adsp_pil_data *desc;
653 const char *firmware_name;
654 struct qcom_adsp *adsp;
655 struct rproc *rproc;
656 int ret;
657
658 desc = of_device_get_match_data(&pdev->dev);
659 if (!desc)
660 return -EINVAL;
661
662 firmware_name = desc->firmware_name;
663 ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
664 &firmware_name);
665 if (ret < 0 && ret != -EINVAL) {
666 dev_err(&pdev->dev, "unable to read firmware-name\n");
667 return ret;
668 }
669
670 rproc = devm_rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
671 firmware_name, sizeof(*adsp));
672 if (!rproc) {
673 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
674 return -ENOMEM;
675 }
676
677 rproc->auto_boot = desc->auto_boot;
678 rproc->has_iommu = desc->has_iommu;
679 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
680
681 adsp = rproc->priv;
682 adsp->dev = &pdev->dev;
683 adsp->rproc = rproc;
684 adsp->info_name = desc->sysmon_name;
685 adsp->has_iommu = desc->has_iommu;
686
687 platform_set_drvdata(pdev, adsp);
688
689 if (desc->is_wpss)
690 adsp->shutdown = qcom_wpss_shutdown;
691 else
692 adsp->shutdown = qcom_adsp_shutdown;
693
694 ret = adsp_alloc_memory_region(adsp);
695 if (ret)
696 return ret;
697
698 ret = adsp_init_clock(adsp, desc->clk_ids);
699 if (ret)
700 return ret;
701
702 ret = qcom_rproc_pds_attach(adsp, desc->pd_names, desc->num_pds);
703 if (ret < 0)
704 return dev_err_probe(&pdev->dev, ret,
705 "Failed to attach proxy power domains\n");
706
707 ret = adsp_init_reset(adsp);
708 if (ret)
709 goto disable_pm;
710
711 ret = adsp_init_mmio(adsp, pdev);
712 if (ret)
713 goto disable_pm;
714
715 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
716 desc->load_state, qcom_adsp_pil_handover);
717 if (ret)
718 goto disable_pm;
719
720 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
721 qcom_add_pdm_subdev(rproc, &adsp->pdm_subdev);
722 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
723 adsp->sysmon = qcom_add_sysmon_subdev(rproc,
724 desc->sysmon_name,
725 desc->ssctl_id);
726 if (IS_ERR(adsp->sysmon)) {
727 ret = PTR_ERR(adsp->sysmon);
728 goto deinit_remove_glink_pdm_ssr;
729 }
730
731 ret = rproc_add(rproc);
732 if (ret)
733 goto remove_sysmon;
734
735 return 0;
736
737 remove_sysmon:
738 qcom_remove_sysmon_subdev(adsp->sysmon);
739 deinit_remove_glink_pdm_ssr:
740 qcom_q6v5_deinit(&adsp->q6v5);
741 qcom_remove_glink_subdev(rproc, &adsp->glink_subdev);
742 qcom_remove_pdm_subdev(rproc, &adsp->pdm_subdev);
743 qcom_remove_ssr_subdev(rproc, &adsp->ssr_subdev);
744 disable_pm:
745 qcom_rproc_pds_detach(adsp);
746
747 return ret;
748 }
749
adsp_remove(struct platform_device * pdev)750 static void adsp_remove(struct platform_device *pdev)
751 {
752 struct qcom_adsp *adsp = platform_get_drvdata(pdev);
753
754 rproc_del(adsp->rproc);
755
756 qcom_q6v5_deinit(&adsp->q6v5);
757 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
758 qcom_remove_pdm_subdev(adsp->rproc, &adsp->pdm_subdev);
759 qcom_remove_sysmon_subdev(adsp->sysmon);
760 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
761 qcom_rproc_pds_detach(adsp);
762 }
763
764 static const struct adsp_pil_data adsp_resource_init = {
765 .crash_reason_smem = 423,
766 .firmware_name = "adsp.mdt",
767 .ssr_name = "lpass",
768 .sysmon_name = "adsp",
769 .ssctl_id = 0x14,
770 .is_wpss = false,
771 .auto_boot = true,
772 .clk_ids = (const char*[]) {
773 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
774 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
775 },
776 .num_clks = 7,
777 .pd_names = (const char*[]) { "cx" },
778 .num_pds = 1,
779 };
780
781 static const struct adsp_pil_data adsp_sc7280_resource_init = {
782 .crash_reason_smem = 423,
783 .firmware_name = "adsp.pbn",
784 .load_state = "adsp",
785 .ssr_name = "lpass",
786 .sysmon_name = "adsp",
787 .ssctl_id = 0x14,
788 .has_iommu = true,
789 .auto_boot = true,
790 .clk_ids = (const char*[]) {
791 "gcc_cfg_noc_lpass", NULL
792 },
793 .num_clks = 1,
794 };
795
796 static const struct adsp_pil_data cdsp_resource_init = {
797 .crash_reason_smem = 601,
798 .firmware_name = "cdsp.mdt",
799 .ssr_name = "cdsp",
800 .sysmon_name = "cdsp",
801 .ssctl_id = 0x17,
802 .is_wpss = false,
803 .auto_boot = true,
804 .clk_ids = (const char*[]) {
805 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
806 "q6_axim", NULL
807 },
808 .num_clks = 7,
809 .pd_names = (const char*[]) { "cx" },
810 .num_pds = 1,
811 };
812
813 static const struct adsp_pil_data wpss_resource_init = {
814 .crash_reason_smem = 626,
815 .firmware_name = "wpss.mdt",
816 .ssr_name = "wpss",
817 .sysmon_name = "wpss",
818 .ssctl_id = 0x19,
819 .is_wpss = true,
820 .auto_boot = false,
821 .load_state = "wpss",
822 .clk_ids = (const char*[]) {
823 "ahb_bdg", "ahb", "rscp", NULL
824 },
825 .num_clks = 3,
826 .pd_names = (const char*[]) { "cx", "mx" },
827 .num_pds = 2,
828 };
829
830 static const struct of_device_id adsp_of_match[] = {
831 { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
832 { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },
833 { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init },
834 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
835 { },
836 };
837 MODULE_DEVICE_TABLE(of, adsp_of_match);
838
839 static struct platform_driver adsp_pil_driver = {
840 .probe = adsp_probe,
841 .remove = adsp_remove,
842 .driver = {
843 .name = "qcom_q6v5_adsp",
844 .of_match_table = adsp_of_match,
845 },
846 };
847
848 module_platform_driver(adsp_pil_driver);
849 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
850 MODULE_LICENSE("GPL v2");
851