1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_CORESIGHT_ETM_H 7 #define _CORESIGHT_CORESIGHT_ETM_H 8 9 #include <asm/local.h> 10 #include <linux/spinlock.h> 11 #include "coresight-priv.h" 12 13 /* 14 * Device registers: 15 * 0x000 - 0x2FC: Trace registers 16 * 0x300 - 0x314: Management registers 17 * 0x318 - 0xEFC: Trace registers 18 * 19 * Coresight registers 20 * 0xF00 - 0xF9C: Management registers 21 * 0xFA0 - 0xFA4: Management registers in PFTv1.0 22 * Trace registers in PFTv1.1 23 * 0xFA8 - 0xFFC: Management registers 24 */ 25 26 /* Trace registers (0x000-0x2FC) */ 27 #define ETMCR 0x000 28 #define ETMCCR 0x004 29 #define ETMTRIGGER 0x008 30 #define ETMSR 0x010 31 #define ETMSCR 0x014 32 #define ETMTSSCR 0x018 33 #define ETMTECR2 0x01c 34 #define ETMTEEVR 0x020 35 #define ETMTECR1 0x024 36 #define ETMFFLR 0x02c 37 #define ETMACVRn(n) (0x040 + (n * 4)) 38 #define ETMACTRn(n) (0x080 + (n * 4)) 39 #define ETMCNTRLDVRn(n) (0x140 + (n * 4)) 40 #define ETMCNTENRn(n) (0x150 + (n * 4)) 41 #define ETMCNTRLDEVRn(n) (0x160 + (n * 4)) 42 #define ETMCNTVRn(n) (0x170 + (n * 4)) 43 #define ETMSQ12EVR 0x180 44 #define ETMSQ21EVR 0x184 45 #define ETMSQ23EVR 0x188 46 #define ETMSQ31EVR 0x18c 47 #define ETMSQ32EVR 0x190 48 #define ETMSQ13EVR 0x194 49 #define ETMSQR 0x19c 50 #define ETMEXTOUTEVRn(n) (0x1a0 + (n * 4)) 51 #define ETMCIDCVRn(n) (0x1b0 + (n * 4)) 52 #define ETMCIDCMR 0x1bc 53 #define ETMIMPSPEC0 0x1c0 54 #define ETMIMPSPEC1 0x1c4 55 #define ETMIMPSPEC2 0x1c8 56 #define ETMIMPSPEC3 0x1cc 57 #define ETMIMPSPEC4 0x1d0 58 #define ETMIMPSPEC5 0x1d4 59 #define ETMIMPSPEC6 0x1d8 60 #define ETMIMPSPEC7 0x1dc 61 #define ETMSYNCFR 0x1e0 62 #define ETMIDR 0x1e4 63 #define ETMCCER 0x1e8 64 #define ETMEXTINSELR 0x1ec 65 #define ETMTESSEICR 0x1f0 66 #define ETMEIBCR 0x1f4 67 #define ETMTSEVR 0x1f8 68 #define ETMAUXCR 0x1fc 69 #define ETMTRACEIDR 0x200 70 #define ETMVMIDCVR 0x240 71 /* Management registers (0x300-0x314) */ 72 #define ETMOSLAR 0x300 73 #define ETMOSLSR 0x304 74 #define ETMOSSRR 0x308 75 #define ETMPDCR 0x310 76 #define ETMPDSR 0x314 77 #define ETM_MAX_ADDR_CMP 16 78 #define ETM_MAX_CNTR 4 79 #define ETM_MAX_CTXID_CMP 3 80 81 /* Register definition */ 82 /* ETMCR - 0x00 */ 83 #define ETMCR_PWD_DWN BIT(0) 84 #define ETMCR_STALL_MODE BIT(7) 85 #define ETMCR_BRANCH_BROADCAST BIT(8) 86 #define ETMCR_ETM_PRG BIT(10) 87 #define ETMCR_ETM_EN BIT(11) 88 #define ETMCR_CYC_ACC BIT(12) 89 #define ETMCR_CTXID_SIZE (BIT(14)|BIT(15)) 90 #define ETMCR_TIMESTAMP_EN BIT(28) 91 #define ETMCR_RETURN_STACK BIT(29) 92 /* ETMCCR - 0x04 */ 93 #define ETMCCR_FIFOFULL BIT(23) 94 /* ETMPDCR - 0x310 */ 95 #define ETMPDCR_PWD_UP BIT(3) 96 /* ETMTECR1 - 0x024 */ 97 #define ETMTECR1_ADDR_COMP_1 BIT(0) 98 #define ETMTECR1_INC_EXC BIT(24) 99 #define ETMTECR1_START_STOP BIT(25) 100 /* ETMCCER - 0x1E8 */ 101 #define ETMCCER_TIMESTAMP BIT(22) 102 #define ETMCCER_RETSTACK BIT(23) 103 104 #define ETM_MODE_EXCLUDE BIT(0) 105 #define ETM_MODE_CYCACC BIT(1) 106 #define ETM_MODE_STALL BIT(2) 107 #define ETM_MODE_TIMESTAMP BIT(3) 108 #define ETM_MODE_CTXID BIT(4) 109 #define ETM_MODE_BBROAD BIT(5) 110 #define ETM_MODE_RET_STACK BIT(6) 111 #define ETM_MODE_ALL (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \ 112 ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \ 113 ETM_MODE_BBROAD | ETM_MODE_RET_STACK | \ 114 ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \ 115 ETM_MODE_EXCL_USER) 116 117 #define ETM_SQR_MASK 0x3 118 #define ETM_TRACEID_MASK 0x3f 119 #define ETM_EVENT_MASK 0x1ffff 120 #define ETM_SYNC_MASK 0xfff 121 #define ETM_ALL_MASK 0xffffffff 122 123 #define ETMSR_PROG_BIT 1 124 #define ETM_SEQ_STATE_MAX_VAL (0x2) 125 #define PORT_SIZE_MASK (GENMASK(21, 21) | GENMASK(6, 4)) 126 127 #define ETM_HARD_WIRE_RES_A /* Hard wired, always true */ \ 128 ((0x0f << 0) | \ 129 /* Resource index A */ \ 130 (0x06 << 4)) 131 132 #define ETM_ADD_COMP_0 /* Single addr comparator 1 */ \ 133 ((0x00 << 7) | \ 134 /* Resource index B */ \ 135 (0x00 << 11)) 136 137 #define ETM_EVENT_NOT_A BIT(14) /* NOT(A) */ 138 139 #define ETM_DEFAULT_EVENT_VAL (ETM_HARD_WIRE_RES_A | \ 140 ETM_ADD_COMP_0 | \ 141 ETM_EVENT_NOT_A) 142 143 /** 144 * struct etm_caps - specifics ETM capabilities 145 * @port_size: port size as reported by ETMCR bit 4-6 and 21. 146 * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. 147 * @nr_cntr: Number of counters as found in ETMCCR bit 13-15. 148 * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19. 149 * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22. 150 * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25. 151 * @fifofull: FIFOFULL logic is present. 152 * @timestamp: Timestamping is implemented. 153 * @retstack: Return stack is implemented. 154 */ 155 struct etm_caps { 156 int port_size; 157 u8 nr_addr_cmp; 158 u8 nr_cntr; 159 u8 nr_ext_inp; 160 u8 nr_ext_out; 161 u8 nr_ctxid_cmp; 162 bool fifofull : 1; 163 bool timestamp : 1; 164 bool retstack : 1; 165 }; 166 167 /** 168 * struct etm_config - configuration information related to an ETM 169 * @mode: controls various modes supported by this ETM/PTM. 170 * @ctrl: used in conjunction with @mode. 171 * @trigger_event: setting for register ETMTRIGGER. 172 * @startstop_ctrl: setting for register ETMTSSCR. 173 * @enable_event: setting for register ETMTEEVR. 174 * @enable_ctrl1: setting for register ETMTECR1. 175 * @enable_ctrl2: setting for register ETMTECR2. 176 * @fifofull_level: setting for register ETMFFLR. 177 * @addr_idx: index for the address comparator selection. 178 * @addr_val: value for address comparator register. 179 * @addr_acctype: access type for address comparator register. 180 * @addr_type: current status of the comparator register. 181 * @cntr_idx: index for the counter register selection. 182 * @cntr_rld_val: reload value of a counter register. 183 * @cntr_event: control for counter enable register. 184 * @cntr_rld_event: value for counter reload event register. 185 * @cntr_val: counter value register. 186 * @seq_12_event: event causing the transition from 1 to 2. 187 * @seq_21_event: event causing the transition from 2 to 1. 188 * @seq_23_event: event causing the transition from 2 to 3. 189 * @seq_31_event: event causing the transition from 3 to 1. 190 * @seq_32_event: event causing the transition from 3 to 2. 191 * @seq_13_event: event causing the transition from 1 to 3. 192 * @seq_curr_state: current value of the sequencer register. 193 * @ctxid_idx: index for the context ID registers. 194 * @ctxid_pid: value for the context ID to trigger on. 195 * @ctxid_mask: mask applicable to all the context IDs. 196 * @sync_freq: Synchronisation frequency. 197 * @timestamp_event: Defines an event that requests the insertion 198 * of a timestamp into the trace stream. 199 */ 200 struct etm_config { 201 u32 mode; 202 u32 ctrl; 203 u32 trigger_event; 204 u32 startstop_ctrl; 205 u32 enable_event; 206 u32 enable_ctrl1; 207 u32 enable_ctrl2; 208 u32 fifofull_level; 209 u8 addr_idx; 210 u32 addr_val[ETM_MAX_ADDR_CMP]; 211 u32 addr_acctype[ETM_MAX_ADDR_CMP]; 212 u32 addr_type[ETM_MAX_ADDR_CMP]; 213 u8 cntr_idx; 214 u32 cntr_rld_val[ETM_MAX_CNTR]; 215 u32 cntr_event[ETM_MAX_CNTR]; 216 u32 cntr_rld_event[ETM_MAX_CNTR]; 217 u32 cntr_val[ETM_MAX_CNTR]; 218 u32 seq_12_event; 219 u32 seq_21_event; 220 u32 seq_23_event; 221 u32 seq_31_event; 222 u32 seq_32_event; 223 u32 seq_13_event; 224 u32 seq_curr_state; 225 u8 ctxid_idx; 226 u32 ctxid_pid[ETM_MAX_CTXID_CMP]; 227 u32 ctxid_mask; 228 u32 sync_freq; 229 u32 timestamp_event; 230 }; 231 232 /** 233 * struct etm_drvdata - specifics associated to an ETM component 234 * @base: memory mapped base address for this component. 235 * @atclk: optional clock for the core parts of the ETM. 236 * @csdev: component vitals needed by the framework. 237 * @spinlock: only one at a time pls. 238 * @cpu: the cpu this component is affined to. 239 * @arch: ETM/PTM version number. 240 * @caps: ETM capabilities. 241 * @use_cpu14: true if management registers need to be accessed via CP14. 242 * @sticky_enable: true if ETM base configuration has been done. 243 * @boot_enable:true if we should start tracing at boot time. 244 * @os_unlock: true if access to management registers is allowed. 245 * @traceid: value of the current ID for this component. 246 * @curr_config: structure holding current running configuration. 247 * @sysfs_config: structure holding sysfs mode configuration. 248 */ 249 struct etm_drvdata { 250 struct csdev_access csa; 251 struct clk *atclk; 252 struct coresight_device *csdev; 253 spinlock_t spinlock; 254 int cpu; 255 u8 arch; 256 struct etm_caps caps; 257 bool use_cp14; 258 bool sticky_enable; 259 bool boot_enable; 260 bool os_unlock; 261 u32 traceid; 262 struct etm_config curr_config; 263 struct etm_config sysfs_config; 264 }; 265 266 static inline void etm_writel(struct etm_drvdata *drvdata, 267 u32 val, u32 off) 268 { 269 if (drvdata->use_cp14) { 270 if (etm_writel_cp14(off, val)) { 271 dev_err(&drvdata->csdev->dev, 272 "invalid CP14 access to ETM reg: %#x", off); 273 } 274 } else { 275 writel_relaxed(val, drvdata->csa.base + off); 276 } 277 } 278 279 static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) 280 { 281 u32 val; 282 283 if (drvdata->use_cp14) { 284 if (etm_readl_cp14(off, &val)) { 285 dev_err(&drvdata->csdev->dev, 286 "invalid CP14 access to ETM reg: %#x", off); 287 } 288 } else { 289 val = readl_relaxed(drvdata->csa.base + off); 290 } 291 292 return val; 293 } 294 295 extern const struct attribute_group *coresight_etm_groups[]; 296 void etm_set_default(struct etm_config *config); 297 void etm_config_trace_mode(struct etm_config *config); 298 struct etm_config *get_etm_config(struct etm_drvdata *drvdata); 299 void etm_release_trace_id(struct etm_drvdata *drvdata); 300 #endif 301