1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ASM_ESR_H
8 #define __ASM_ESR_H
9
10 #include <asm/memory.h>
11 #include <asm/sysreg.h>
12
13 #define ESR_ELx_EC_UNKNOWN UL(0x00)
14 #define ESR_ELx_EC_WFx UL(0x01)
15 /* Unallocated EC: 0x02 */
16 #define ESR_ELx_EC_CP15_32 UL(0x03)
17 #define ESR_ELx_EC_CP15_64 UL(0x04)
18 #define ESR_ELx_EC_CP14_MR UL(0x05)
19 #define ESR_ELx_EC_CP14_LS UL(0x06)
20 #define ESR_ELx_EC_FP_ASIMD UL(0x07)
21 #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
22 #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */
23 #define ESR_ELx_EC_OTHER UL(0x0A)
24 /* Unallocated EC: 0x0B */
25 #define ESR_ELx_EC_CP14_64 UL(0x0C)
26 #define ESR_ELx_EC_BTI UL(0x0D)
27 #define ESR_ELx_EC_ILL UL(0x0E)
28 /* Unallocated EC: 0x0F - 0x10 */
29 #define ESR_ELx_EC_SVC32 UL(0x11)
30 #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */
31 #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */
32 /* Unallocated EC: 0x14 */
33 #define ESR_ELx_EC_SVC64 UL(0x15)
34 #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */
35 #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */
36 #define ESR_ELx_EC_SYS64 UL(0x18)
37 #define ESR_ELx_EC_SVE UL(0x19)
38 #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */
39 /* Unallocated EC: 0x1B */
40 #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */
41 #define ESR_ELx_EC_SME UL(0x1D)
42 /* Unallocated EC: 0x1E */
43 #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
44 #define ESR_ELx_EC_IABT_LOW UL(0x20)
45 #define ESR_ELx_EC_IABT_CUR UL(0x21)
46 #define ESR_ELx_EC_PC_ALIGN UL(0x22)
47 /* Unallocated EC: 0x23 */
48 #define ESR_ELx_EC_DABT_LOW UL(0x24)
49 #define ESR_ELx_EC_DABT_CUR UL(0x25)
50 #define ESR_ELx_EC_SP_ALIGN UL(0x26)
51 #define ESR_ELx_EC_MOPS UL(0x27)
52 #define ESR_ELx_EC_FP_EXC32 UL(0x28)
53 /* Unallocated EC: 0x29 - 0x2B */
54 #define ESR_ELx_EC_FP_EXC64 UL(0x2C)
55 #define ESR_ELx_EC_GCS UL(0x2D)
56 /* Unallocated EC: 0x2E */
57 #define ESR_ELx_EC_SERROR UL(0x2F)
58 #define ESR_ELx_EC_BREAKPT_LOW UL(0x30)
59 #define ESR_ELx_EC_BREAKPT_CUR UL(0x31)
60 #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32)
61 #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33)
62 #define ESR_ELx_EC_WATCHPT_LOW UL(0x34)
63 #define ESR_ELx_EC_WATCHPT_CUR UL(0x35)
64 /* Unallocated EC: 0x36 - 0x37 */
65 #define ESR_ELx_EC_BKPT32 UL(0x38)
66 /* Unallocated EC: 0x39 */
67 #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */
68 /* Unallocated EC: 0x3B */
69 #define ESR_ELx_EC_BRK64 UL(0x3C)
70 /* Unallocated EC: 0x3D - 0x3F */
71 #define ESR_ELx_EC_MAX UL(0x3F)
72
73 #define ESR_ELx_EC_SHIFT (26)
74 #define ESR_ELx_EC_WIDTH (6)
75 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
76 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
77
78 #define ESR_ELx_IL_SHIFT (25)
79 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
80 #define ESR_ELx_ISS_MASK (GENMASK(24, 0))
81 #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK)
82 #define ESR_ELx_ISS2_SHIFT (32)
83 #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))
84 #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
85
86 /* ISS field definitions shared by different classes */
87 #define ESR_ELx_WNR_SHIFT (6)
88 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
89
90 /* Asynchronous Error Type */
91 #define ESR_ELx_IDS_SHIFT (24)
92 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
93 #define ESR_ELx_AET_SHIFT (10)
94 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
95
96 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
98 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
99 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
100 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
101
102 /* Shared ISS field definitions for Data/Instruction aborts */
103 #define ESR_ELx_VNCR_SHIFT (13)
104 #define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT)
105 #define ESR_ELx_SET_SHIFT (11)
106 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
107 #define ESR_ELx_FnV_SHIFT (10)
108 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
109 #define ESR_ELx_EA_SHIFT (9)
110 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
111 #define ESR_ELx_S1PTW_SHIFT (7)
112 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
113
114 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
115 #define ESR_ELx_FSC (0x3F)
116 #define ESR_ELx_FSC_TYPE (0x3C)
117 #define ESR_ELx_FSC_LEVEL (0x03)
118 #define ESR_ELx_FSC_EXTABT (0x10)
119 #define ESR_ELx_FSC_MTE (0x11)
120 #define ESR_ELx_FSC_SERROR (0x11)
121 #define ESR_ELx_FSC_ACCESS (0x08)
122 #define ESR_ELx_FSC_FAULT (0x04)
123 #define ESR_ELx_FSC_PERM (0x0C)
124 #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n))
125 #define ESR_ELx_FSC_SECC (0x18)
126 #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n))
127 #define ESR_ELx_FSC_EXCL_ATOMIC (0x35)
128 #define ESR_ELx_FSC_ADDRSZ (0x00)
129
130 /*
131 * Annoyingly, the negative levels for Address size faults aren't laid out
132 * contiguously (or in the desired order)
133 */
134 #define ESR_ELx_FSC_ADDRSZ_nL(n) ((n) == -1 ? 0x29 : 0x2C)
135 #define ESR_ELx_FSC_ADDRSZ_L(n) ((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \
136 (ESR_ELx_FSC_ADDRSZ + (n)))
137
138 /* Status codes for individual page table levels */
139 #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n))
140 #define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + (n))
141
142 #define ESR_ELx_FSC_FAULT_nL (0x2C)
143 #define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
144 ESR_ELx_FSC_FAULT) + (n))
145
146 /* ISS field definitions for Data Aborts */
147 #define ESR_ELx_ISV_SHIFT (24)
148 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
149 #define ESR_ELx_SAS_SHIFT (22)
150 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
151 #define ESR_ELx_SSE_SHIFT (21)
152 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
153 #define ESR_ELx_SRT_SHIFT (16)
154 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
155 #define ESR_ELx_SF_SHIFT (15)
156 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
157 #define ESR_ELx_AR_SHIFT (14)
158 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
159 #define ESR_ELx_CM_SHIFT (8)
160 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
161
162 /* ISS2 field definitions for Data Aborts */
163 #define ESR_ELx_HDBSSF_SHIFT (11)
164 #define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT)
165 #define ESR_ELx_TnD_SHIFT (10)
166 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
167 #define ESR_ELx_TagAccess_SHIFT (9)
168 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
169 #define ESR_ELx_GCS_SHIFT (8)
170 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
171 #define ESR_ELx_Overlay_SHIFT (6)
172 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
173 #define ESR_ELx_DirtyBit_SHIFT (5)
174 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
175 #define ESR_ELx_Xs_SHIFT (0)
176 #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))
177
178 /* ISS field definitions for exceptions taken in to Hyp */
179 #define ESR_ELx_CV (UL(1) << 24)
180 #define ESR_ELx_COND_SHIFT (20)
181 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
182 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
183 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
184 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
185 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
186 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
187 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
188 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
189
190 /* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */
191 #define ESR_ELx_ISS_OTHER_ST64BV (0)
192 #define ESR_ELx_ISS_OTHER_ST64BV0 (1)
193 #define ESR_ELx_ISS_OTHER_LDST64B (2)
194 #define ESR_ELx_ISS_OTHER_TSBCSYNC (3)
195 #define ESR_ELx_ISS_OTHER_PSBCSYNC (4)
196
197 #define DISR_EL1_IDS (UL(1) << 24)
198 /*
199 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
200 * different things in the future...
201 */
202 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
203
204 /* ESR value templates for specific events */
205 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \
206 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
207 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
208 ESR_ELx_WFx_ISS_WFI)
209
210 /* BRK instruction trap from AArch64 state */
211 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
212
213 /* ISS field definitions for System instruction traps */
214 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
215 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
216 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
217 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1
218 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
219
220 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5
221 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
222 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
223 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
224 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
225 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
226 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
227 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
228 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
229 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
230 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
231 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
232 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
233 ESR_ELx_SYS64_ISS_OP1_MASK | \
234 ESR_ELx_SYS64_ISS_OP2_MASK | \
235 ESR_ELx_SYS64_ISS_CRN_MASK | \
236 ESR_ELx_SYS64_ISS_CRM_MASK)
237 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
238 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
239 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
240 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
241 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
242 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
243
244 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
245 ESR_ELx_SYS64_ISS_DIR_MASK)
246 #define ESR_ELx_SYS64_ISS_RT(esr) \
247 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
248 /*
249 * User space cache operations have the following sysreg encoding
250 * in System instructions.
251 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
252 */
253 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
254 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
255 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
256 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
257 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
258 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
259
260 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
261 ESR_ELx_SYS64_ISS_OP1_MASK | \
262 ESR_ELx_SYS64_ISS_OP2_MASK | \
263 ESR_ELx_SYS64_ISS_CRN_MASK | \
264 ESR_ELx_SYS64_ISS_DIR_MASK)
265 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
266 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
267 ESR_ELx_SYS64_ISS_DIR_WRITE)
268 /*
269 * User space MRS operations which are supported for emulation
270 * have the following sysreg encoding in System instructions.
271 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
272 */
273 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
274 ESR_ELx_SYS64_ISS_OP1_MASK | \
275 ESR_ELx_SYS64_ISS_CRN_MASK | \
276 ESR_ELx_SYS64_ISS_DIR_MASK)
277 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
278 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
279 ESR_ELx_SYS64_ISS_DIR_READ)
280
281 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
282 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
283 ESR_ELx_SYS64_ISS_DIR_READ)
284
285 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
286 ESR_ELx_SYS64_ISS_DIR_READ)
287
288 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
289 ESR_ELx_SYS64_ISS_DIR_READ)
290
291 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
292 ESR_ELx_SYS64_ISS_DIR_READ)
293
294 #define esr_sys64_to_sysreg(e) \
295 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
296 ESR_ELx_SYS64_ISS_OP0_SHIFT), \
297 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
298 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
299 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
300 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
301 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
302 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
303 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
304 ESR_ELx_SYS64_ISS_OP2_SHIFT))
305
306 #define esr_cp15_to_sysreg(e) \
307 sys_reg(3, \
308 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
309 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
310 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
311 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
312 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
313 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
314 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
315 ESR_ELx_SYS64_ISS_OP2_SHIFT))
316
317 /* ISS field definitions for ERET/ERETAA/ERETAB trapping */
318 #define ESR_ELx_ERET_ISS_ERET 0x2
319 #define ESR_ELx_ERET_ISS_ERETA 0x1
320
321 /*
322 * ISS field definitions for floating-point exception traps
323 * (FP_EXC_32/FP_EXC_64).
324 *
325 * (The FPEXC_* constants are used instead for common bits.)
326 */
327
328 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
329
330 /*
331 * ISS field definitions for CP15 accesses
332 */
333 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
334 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
335 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
336
337 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
338 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
339 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
340 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
341 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
342 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
343 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
344 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
345 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
346 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
347
348 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
349 ESR_ELx_CP15_32_ISS_OP2_MASK | \
350 ESR_ELx_CP15_32_ISS_CRN_MASK | \
351 ESR_ELx_CP15_32_ISS_CRM_MASK | \
352 ESR_ELx_CP15_32_ISS_DIR_MASK)
353 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
354 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
355 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
356 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
357 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
358
359 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
360 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
361 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
362
363 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
364 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
365
366 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
367 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
368
369 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
370 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
371 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
372 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
373
374 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
375 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
376 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
377
378 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
379 ESR_ELx_CP15_64_ISS_CRM_MASK | \
380 ESR_ELx_CP15_64_ISS_DIR_MASK)
381
382 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
383 ESR_ELx_CP15_64_ISS_DIR_READ)
384
385 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
386 ESR_ELx_CP15_64_ISS_DIR_READ)
387
388 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
389 ESR_ELx_CP15_32_ISS_DIR_READ)
390
391 /*
392 * ISS values for SME traps
393 */
394 #define ESR_ELx_SME_ISS_SMTC_MASK GENMASK(2, 0)
395 #define ESR_ELx_SME_ISS_SMTC(esr) ((esr) & ESR_ELx_SME_ISS_SMTC_MASK)
396
397 #define ESR_ELx_SME_ISS_SMTC_SME_DISABLED 0
398 #define ESR_ELx_SME_ISS_SMTC_ILL 1
399 #define ESR_ELx_SME_ISS_SMTC_SM_DISABLED 2
400 #define ESR_ELx_SME_ISS_SMTC_ZA_DISABLED 3
401 #define ESR_ELx_SME_ISS_SMTC_ZT_DISABLED 4
402
403 /* ISS field definitions for MOPS exceptions */
404 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
405 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
406 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
407 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
408 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
409 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
410 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
411
412 /* ISS field definitions for GCS */
413 #define ESR_ELx_ExType_SHIFT (20)
414 #define ESR_ELx_ExType_MASK GENMASK(23, 20)
415 #define ESR_ELx_Raddr_SHIFT (10)
416 #define ESR_ELx_Raddr_MASK GENMASK(14, 10)
417 #define ESR_ELx_Rn_SHIFT (5)
418 #define ESR_ELx_Rn_MASK GENMASK(9, 5)
419 #define ESR_ELx_Rvalue_SHIFT 5
420 #define ESR_ELx_Rvalue_MASK GENMASK(9, 5)
421 #define ESR_ELx_IT_SHIFT (0)
422 #define ESR_ELx_IT_MASK GENMASK(4, 0)
423
424 #define ESR_ELx_ExType_DATA_CHECK 0
425 #define ESR_ELx_ExType_EXLOCK 1
426 #define ESR_ELx_ExType_STR 2
427
428 #define ESR_ELx_IT_RET 0
429 #define ESR_ELx_IT_GCSPOPM 1
430 #define ESR_ELx_IT_RET_KEYA 2
431 #define ESR_ELx_IT_RET_KEYB 3
432 #define ESR_ELx_IT_GCSSS1 4
433 #define ESR_ELx_IT_GCSSS2 5
434 #define ESR_ELx_IT_GCSPOPCX 6
435 #define ESR_ELx_IT_GCSPOPX 7
436
437 #ifndef __ASSEMBLER__
438 #include <asm/types.h>
439
esr_brk_comment(unsigned long esr)440 static inline unsigned long esr_brk_comment(unsigned long esr)
441 {
442 return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
443 }
444
esr_is_data_abort(unsigned long esr)445 static inline bool esr_is_data_abort(unsigned long esr)
446 {
447 const unsigned long ec = ESR_ELx_EC(esr);
448
449 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
450 }
451
esr_is_cfi_brk(unsigned long esr)452 static inline bool esr_is_cfi_brk(unsigned long esr)
453 {
454 return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
455 (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE;
456 }
457
esr_is_ubsan_brk(unsigned long esr)458 static inline bool esr_is_ubsan_brk(unsigned long esr)
459 {
460 return (esr_brk_comment(esr) & ~UBSAN_BRK_MASK) == UBSAN_BRK_IMM;
461 }
462
esr_fsc_is_translation_fault(unsigned long esr)463 static inline bool esr_fsc_is_translation_fault(unsigned long esr)
464 {
465 esr = esr & ESR_ELx_FSC;
466
467 return (esr == ESR_ELx_FSC_FAULT_L(3)) ||
468 (esr == ESR_ELx_FSC_FAULT_L(2)) ||
469 (esr == ESR_ELx_FSC_FAULT_L(1)) ||
470 (esr == ESR_ELx_FSC_FAULT_L(0)) ||
471 (esr == ESR_ELx_FSC_FAULT_L(-1));
472 }
473
esr_fsc_is_permission_fault(unsigned long esr)474 static inline bool esr_fsc_is_permission_fault(unsigned long esr)
475 {
476 esr = esr & ESR_ELx_FSC;
477
478 return (esr == ESR_ELx_FSC_PERM_L(3)) ||
479 (esr == ESR_ELx_FSC_PERM_L(2)) ||
480 (esr == ESR_ELx_FSC_PERM_L(1)) ||
481 (esr == ESR_ELx_FSC_PERM_L(0));
482 }
483
esr_fsc_is_access_flag_fault(unsigned long esr)484 static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
485 {
486 esr = esr & ESR_ELx_FSC;
487
488 return (esr == ESR_ELx_FSC_ACCESS_L(3)) ||
489 (esr == ESR_ELx_FSC_ACCESS_L(2)) ||
490 (esr == ESR_ELx_FSC_ACCESS_L(1)) ||
491 (esr == ESR_ELx_FSC_ACCESS_L(0));
492 }
493
esr_fsc_is_excl_atomic_fault(unsigned long esr)494 static inline bool esr_fsc_is_excl_atomic_fault(unsigned long esr)
495 {
496 esr = esr & ESR_ELx_FSC;
497
498 return esr == ESR_ELx_FSC_EXCL_ATOMIC;
499 }
500
esr_fsc_is_addr_sz_fault(unsigned long esr)501 static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr)
502 {
503 esr &= ESR_ELx_FSC;
504
505 return (esr == ESR_ELx_FSC_ADDRSZ_L(3)) ||
506 (esr == ESR_ELx_FSC_ADDRSZ_L(2)) ||
507 (esr == ESR_ELx_FSC_ADDRSZ_L(1)) ||
508 (esr == ESR_ELx_FSC_ADDRSZ_L(0)) ||
509 (esr == ESR_ELx_FSC_ADDRSZ_L(-1));
510 }
511
esr_fsc_is_sea_ttw(unsigned long esr)512 static inline bool esr_fsc_is_sea_ttw(unsigned long esr)
513 {
514 esr = esr & ESR_ELx_FSC;
515
516 return (esr == ESR_ELx_FSC_SEA_TTW(3)) ||
517 (esr == ESR_ELx_FSC_SEA_TTW(2)) ||
518 (esr == ESR_ELx_FSC_SEA_TTW(1)) ||
519 (esr == ESR_ELx_FSC_SEA_TTW(0)) ||
520 (esr == ESR_ELx_FSC_SEA_TTW(-1));
521 }
522
esr_fsc_is_secc_ttw(unsigned long esr)523 static inline bool esr_fsc_is_secc_ttw(unsigned long esr)
524 {
525 esr = esr & ESR_ELx_FSC;
526
527 return (esr == ESR_ELx_FSC_SECC_TTW(3)) ||
528 (esr == ESR_ELx_FSC_SECC_TTW(2)) ||
529 (esr == ESR_ELx_FSC_SECC_TTW(1)) ||
530 (esr == ESR_ELx_FSC_SECC_TTW(0)) ||
531 (esr == ESR_ELx_FSC_SECC_TTW(-1));
532 }
533
534 /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */
esr_iss_is_eretax(unsigned long esr)535 static inline bool esr_iss_is_eretax(unsigned long esr)
536 {
537 return esr & ESR_ELx_ERET_ISS_ERET;
538 }
539
540 /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */
esr_iss_is_eretab(unsigned long esr)541 static inline bool esr_iss_is_eretab(unsigned long esr)
542 {
543 return esr & ESR_ELx_ERET_ISS_ERETA;
544 }
545
546 const char *esr_get_class_string(unsigned long esr);
547 #endif /* __ASSEMBLER__ */
548
549 #endif /* __ASM_ESR_H */
550