1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * This header file defines the register offsets and bit fields 4 * of ENETC4 PF and VFs. Note that the same registers as ENETC 5 * version 1.0 are defined in the enetc_hw.h file. 6 * 7 * Copyright 2024 NXP 8 */ 9 #ifndef __ENETC4_HW_H_ 10 #define __ENETC4_HW_H_ 11 12 #define NXP_ENETC_VENDOR_ID 0x1131 13 #define NXP_ENETC_PF_DEV_ID 0xe101 14 #define NXP_ENETC_PPM_DEV_ID 0xe110 15 16 /**********************Station interface registers************************/ 17 /* Station interface LSO segmentation flag mask register 0/1 */ 18 #define ENETC4_SILSOSFMR0 0x1300 19 #define SILSOSFMR0_TCP_MID_SEG GENMASK(27, 16) 20 #define SILSOSFMR0_TCP_1ST_SEG GENMASK(11, 0) 21 #define SILSOSFMR0_VAL_SET(first, mid) (FIELD_PREP(SILSOSFMR0_TCP_MID_SEG, mid) | \ 22 FIELD_PREP(SILSOSFMR0_TCP_1ST_SEG, first)) 23 24 #define ENETC4_SILSOSFMR1 0x1304 25 #define SILSOSFMR1_TCP_LAST_SEG GENMASK(11, 0) 26 #define ENETC4_TCP_FLAGS_FIN BIT(0) 27 #define ENETC4_TCP_FLAGS_SYN BIT(1) 28 #define ENETC4_TCP_FLAGS_RST BIT(2) 29 #define ENETC4_TCP_FLAGS_PSH BIT(3) 30 #define ENETC4_TCP_FLAGS_ACK BIT(4) 31 #define ENETC4_TCP_FLAGS_URG BIT(5) 32 #define ENETC4_TCP_FLAGS_ECE BIT(6) 33 #define ENETC4_TCP_FLAGS_CWR BIT(7) 34 #define ENETC4_TCP_FLAGS_NS BIT(8) 35 /* According to tso_build_hdr(), clear all special flags for not last packet. */ 36 #define ENETC4_TCP_NL_SEG_FLAGS_DMASK (ENETC4_TCP_FLAGS_FIN | \ 37 ENETC4_TCP_FLAGS_RST | ENETC4_TCP_FLAGS_PSH) 38 39 /***************************ENETC port registers**************************/ 40 #define ENETC4_ECAPR0 0x0 41 #define ECAPR0_RFS BIT(2) 42 #define ECAPR0_TSD BIT(5) 43 #define ECAPR0_RSS BIT(8) 44 #define ECAPR0_RSC BIT(9) 45 #define ECAPR0_LSO BIT(10) 46 #define ECAPR0_WO BIT(13) 47 48 #define ENETC4_ECAPR1 0x4 49 #define ECAPR1_NUM_TCS GENMASK(6, 4) 50 #define ECAPR1_NUM_MCH GENMASK(9, 8) 51 #define ECAPR1_NUM_UCH GENMASK(11, 10) 52 #define ECAPR1_NUM_MSIX GENMASK(22, 12) 53 #define ECAPR1_NUM_VSI GENMASK(27, 24) 54 #define ECAPR1_NUM_IPV BIT(31) 55 56 #define ENETC4_ECAPR2 0x8 57 #define ECAPR2_NUM_TX_BDR GENMASK(9, 0) 58 #define ECAPR2_NUM_RX_BDR GENMASK(25, 16) 59 60 #define ENETC4_PMR 0x10 61 #define PMR_SI_EN(a) BIT((16 + (a))) 62 63 /* Port Pause ON/OFF threshold register */ 64 #define ENETC4_PPAUONTR 0x108 65 #define ENETC4_PPAUOFFTR 0x10c 66 67 /* Port ingress congestion DRa (a=0,1,2,3) discard count register */ 68 #define ENETC4_PICDRDCR(a) ((a) * 0x10 + 0x140) 69 70 /* Port Station interface promiscuous MAC mode register */ 71 #define ENETC4_PSIPMMR 0x200 72 73 /* Port Station interface promiscuous VLAN mode register */ 74 #define ENETC4_PSIPVMR 0x204 75 76 /* Port broadcast frames dropped due to MAC filtering register */ 77 #define ENETC4_PBFDSIR 0x208 78 79 /* Port frame drop MAC source address pruning register */ 80 #define ENETC4_PFDMSAPR 0x20c 81 82 /* Port RSS key register n. n = 0,1,2,...,9 */ 83 #define ENETC4_PRSSKR(n) ((n) * 0x4 + 0x250) 84 85 /* Port station interface MAC address filtering capability register */ 86 #define ENETC4_PSIMAFCAPR 0x280 87 #define PSIMAFCAPR_NUM_MAC_AFTE GENMASK(11, 0) 88 89 /* Port unicast frames dropped due to MAC filtering register */ 90 #define ENETC4_PUFDMFR 0x284 91 92 /* Port multicast frames dropped due to MAC filtering register */ 93 #define ENETC4_PMFDMFR 0x288 94 95 /* Port station interface VLAN filtering capability register */ 96 #define ENETC4_PSIVLANFCAPR 0x2c0 97 #define PSIVLANFCAPR_NUM_VLAN_FTE GENMASK(11, 0) 98 99 /* Port station interface VLAN filtering mode register */ 100 #define ENETC4_PSIVLANFMR 0x2c4 101 #define PSIVLANFMR_VS BIT(0) 102 103 /* Port unicast frames dropped VLAN filtering register */ 104 #define ENETC4_PUFDVFR 0x2d0 105 106 /* Port multicast frames dropped VLAN filtering register */ 107 #define ENETC4_PMFDVFR 0x2d4 108 109 /* Port broadcast frames dropped VLAN filtering register */ 110 #define ENETC4_PBFDVFR 0x2d8 111 112 /* Port Station interface a primary MAC address registers */ 113 #define ENETC4_PSIPMAR0(a) ((a) * 0x80 + 0x2000) 114 #define ENETC4_PSIPMAR1(a) ((a) * 0x80 + 0x2004) 115 116 /* Port station interface a configuration register 0/2 */ 117 #define ENETC4_PSICFGR0(a) ((a) * 0x80 + 0x2010) 118 #define PSICFGR0_VASE BIT(13) 119 #define PSICFGR0_ASE BIT(15) 120 #define PSICFGR0_ANTI_SPOOFING (PSICFGR0_VASE | PSICFGR0_ASE) 121 122 #define ENETC4_PSICFGR2(a) ((a) * 0x80 + 0x2018) 123 #define PSICFGR2_NUM_MSIX GENMASK(5, 0) 124 125 /* Port station interface a unicast MAC hash filter register 0/1 */ 126 #define ENETC4_PSIUMHFR0(a) ((a) * 0x80 + 0x2050) 127 #define ENETC4_PSIUMHFR1(a) ((a) * 0x80 + 0x2054) 128 129 /* Port station interface a multicast MAC hash filter register 0/1 */ 130 #define ENETC4_PSIMMHFR0(a) ((a) * 0x80 + 0x2058) 131 #define ENETC4_PSIMMHFR1(a) ((a) * 0x80 + 0x205c) 132 133 /* Port station interface a VLAN hash filter register 0/1 */ 134 #define ENETC4_PSIVHFR0(a) ((a) * 0x80 + 0x2060) 135 #define ENETC4_PSIVHFR1(a) ((a) * 0x80 + 0x2064) 136 137 #define ENETC4_PMCAPR 0x4004 138 #define PMCAPR_FP GENMASK(10, 9) 139 140 /* Port capability register */ 141 #define ENETC4_PCAPR 0x4000 142 #define PCAPR_LINK_TYPE BIT(4) 143 144 /* Port configuration register */ 145 #define ENETC4_PCR 0x4010 146 #define PCR_HDR_FMT BIT(0) 147 #define PCR_L2DOSE BIT(4) 148 #define PCR_TIMER_CS BIT(8) 149 #define PCR_PSPEED GENMASK(29, 16) 150 #define PCR_PSPEED_VAL(s) FIELD_PREP(PCR_PSPEED, ((s) / 10 - 1)) 151 152 /* Port MAC address register 0/1 */ 153 #define ENETC4_PMAR0 0x4020 154 #define ENETC4_PMAR1 0x4024 155 156 /* Port operational register */ 157 #define ENETC4_POR 0x4100 158 #define POR_TXDIS BIT(0) 159 #define POR_RXDIS BIT(1) 160 161 /* Port status register */ 162 #define ENETC4_PSR 0x4104 163 #define PSR_RX_BUSY BIT(1) 164 165 /* Port Rx discard count register */ 166 #define ENETC4_PRXDCR 0x41c0 167 168 /* Port Rx discard count read-reset register */ 169 #define ENETC4_PRXDCRRR 0x41c4 170 171 /* Port Rx discard count reason register 0 */ 172 #define ENETC4_PRXDCRR0 0x41c8 173 174 /* Port Rx discard count reason register 1 */ 175 #define ENETC4_PRXDCRR1 0x41cc 176 177 /* Port traffic class a transmit maximum SDU register */ 178 #define ENETC4_PTCTMSDUR(a) ((a) * 0x20 + 0x4208) 179 #define PTCTMSDUR_MAXSDU GENMASK(15, 0) 180 #define PTCTMSDUR_SDU_TYPE GENMASK(17, 16) 181 #define SDU_TYPE_PPDU 0 182 #define SDU_TYPE_MPDU 1 183 #define SDU_TYPE_MSDU 2 184 185 #define ENETC4_PMAC_OFFSET 0x400 186 #define ENETC4_PM_CMD_CFG(mac) (0x5008 + (mac) * 0x400) 187 #define PM_CMD_CFG_TX_EN BIT(0) 188 #define PM_CMD_CFG_RX_EN BIT(1) 189 #define PM_CMD_CFG_PAUSE_FWD BIT(7) 190 #define PM_CMD_CFG_PAUSE_IGN BIT(8) 191 #define PM_CMD_CFG_TX_ADDR_INS BIT(9) 192 #define PM_CMD_CFG_LOOP_EN BIT(10) 193 #define PM_CMD_CFG_LPBK_MODE GENMASK(12, 11) 194 #define LPBCK_MODE_EXT_TX_CLK 0 195 #define LPBCK_MODE_MAC_LEVEL 1 196 #define LPBCK_MODE_INT_TX_CLK 2 197 #define PM_CMD_CFG_CNT_FRM_EN BIT(13) 198 #define PM_CMD_CFG_TXP BIT(15) 199 #define PM_CMD_CFG_SEND_IDLE BIT(16) 200 #define PM_CMD_CFG_SFD BIT(21) 201 #define PM_CMD_CFG_TX_FLUSH BIT(22) 202 #define PM_CMD_CFG_TX_LOWP_EN BIT(23) 203 #define PM_CMD_CFG_RX_LOWP_EMPTY BIT(24) 204 #define PM_CMD_CFG_SWR BIT(26) 205 #define PM_CMD_CFG_TS_MODE BIT(30) 206 #define PM_CMD_CFG_MG BIT(31) 207 208 /* Port MAC 0/1 Maximum Frame Length Register */ 209 #define ENETC4_PM_MAXFRM(mac) (0x5014 + (mac) * 0x400) 210 211 /* Port internal MDIO base address, use to access PCS */ 212 #define ENETC4_PM_IMDIO_BASE 0x5030 213 214 /* Port MAC 0/1 Interrupt Event Register */ 215 #define ENETC4_PM_IEVENT(mac) (0x5040 + (mac) * 0x400) 216 #define PM_IEVENT_TX_EMPTY BIT(5) 217 #define PM_IEVENT_RX_EMPTY BIT(6) 218 219 /* Port MAC 0/1 Pause Quanta Register */ 220 #define ENETC4_PM_PAUSE_QUANTA(mac) (0x5054 + (mac) * 0x400) 221 222 /* Port MAC 0/1 Pause Quanta Threshold Register */ 223 #define ENETC4_PM_PAUSE_THRESH(mac) (0x5064 + (mac) * 0x400) 224 225 #define ENETC4_PM_SINGLE_STEP(mac) (0x50c0 + (mac) * 0x400) 226 #define PM_SINGLE_STEP_CH BIT(6) 227 #define PM_SINGLE_STEP_OFFSET GENMASK(15, 7) 228 #define PM_SINGLE_STEP_OFFSET_SET(o) FIELD_PREP(PM_SINGLE_STEP_OFFSET, o) 229 #define PM_SINGLE_STEP_EN BIT(31) 230 231 /* Port MAC 0/1 Receive Ethernet Octets Counter */ 232 #define ENETC4_PM_REOCT(mac) (0x5100 + (mac) * 0x400) 233 234 /* Port MAC 0/1 Receive Octets Counter */ 235 #define ENETC4_PM_ROCT(mac) (0x5108 + (mac) * 0x400) 236 237 /* Port MAC 0/1 Receive Alignment Error Counter Register */ 238 #define ENETC4_PM_RALN(mac) (0x5110 + (mac) * 0x400) 239 240 /* Port MAC 0/1 Receive Valid Pause Frame Counter */ 241 #define ENETC4_PM_RXPF(mac) (0x5118 + (mac) * 0x400) 242 243 /* Port MAC 0/1 Receive Frame Counter */ 244 #define ENETC4_PM_RFRM(mac) (0x5120 + (mac) * 0x400) 245 246 /* Port MAC 0/1 Receive Frame Check Sequence Error Counter */ 247 #define ENETC4_PM_RFCS(mac) (0x5128 + (mac) * 0x400) 248 249 /* Port MAC 0/1 Receive VLAN Frame Counter */ 250 #define ENETC4_PM_RVLAN(mac) (0x5130 + (mac) * 0x400) 251 252 /* Port MAC 0/1 Receive Frame Error Counter */ 253 #define ENETC4_PM_RERR(mac) (0x5138 + (mac) * 0x400) 254 255 /* Port MAC 0/1 Receive Unicast Frame Counter */ 256 #define ENETC4_PM_RUCA(mac) (0x5140 + (mac) * 0x400) 257 258 /* Port MAC 0/1 Receive Multicast Frame Counter */ 259 #define ENETC4_PM_RMCA(mac) (0x5148 + (mac) * 0x400) 260 261 /* Port MAC 0/1 Receive Broadcast Frame Counter */ 262 #define ENETC4_PM_RBCA(mac) (0x5150 + (mac) * 0x400) 263 264 /* Port MAC 0/1 Receive Dropped Packets Counter */ 265 #define ENETC4_PM_RDRP(mac) (0x5158 + (mac) * 0x400) 266 267 /* Port MAC 0/1 Receive Packets Counter */ 268 #define ENETC4_PM_RPKT(mac) (0x5160 + (mac) * 0x400) 269 270 /* Port MAC 0/1 Receive Undersized Packet Counter */ 271 #define ENETC4_PM_RUND(mac) (0x5168 + (mac) * 0x400) 272 273 /* Port MAC 0/1 Receive 64-Octet Packet Counter */ 274 #define ENETC4_PM_R64(mac) (0x5170 + (mac) * 0x400) 275 276 /* Port MAC 0/1 Receive 65 to 127-Octet Packet Counter */ 277 #define ENETC4_PM_R127(mac) (0x5178 + (mac) * 0x400) 278 279 /* Port MAC 0/1 Receive 128 to 255-Octet Packet Counter */ 280 #define ENETC4_PM_R255(mac) (0x5180 + (mac) * 0x400) 281 282 /* Port MAC 0/1 Receive 256 to 511-Octet Packet Counter */ 283 #define ENETC4_PM_R511(mac) (0x5188 + (mac) * 0x400) 284 285 /* Port MAC 0/1 Receive 512 to 1023-Octet Packet Counter */ 286 #define ENETC4_PM_R1023(mac) (0x5190 + (mac) * 0x400) 287 288 /* Port MAC 0/1 Receive 1024 to 1522-Octet Packet Counter */ 289 #define ENETC4_PM_R1522(mac) (0x5198 + (mac) * 0x400) 290 291 /* Port MAC 0/1 Receive 1523 to Max-Octet Packet Counter */ 292 #define ENETC4_PM_R1523X(mac) (0x51a0 + (mac) * 0x400) 293 294 /* Port MAC 0/1 Receive Oversized Packet Counter */ 295 #define ENETC4_PM_ROVR(mac) (0x51a8 + (mac) * 0x400) 296 297 /* Port MAC 0/1 Receive Jabber Packet Counter */ 298 #define ENETC4_PM_RJBR(mac) (0x51b0 + (mac) * 0x400) 299 300 /* Port MAC 0/1 Receive Fragment Packet Counter */ 301 #define ENETC4_PM_RFRG(mac) (0x51b8 + (mac) * 0x400) 302 303 /* Port MAC 0/1 Receive Control Packet Counter */ 304 #define ENETC4_PM_RCNP(mac) (0x51c0 + (mac) * 0x400) 305 306 /* Port MAC 0/1 Receive Dropped Not Truncated Packets Counter */ 307 #define ENETC4_PM_RDRNTP(mac) (0x51c8 + (mac) * 0x400) 308 309 /* Port MAC 0/1 Transmit Ethernet Octets Counter */ 310 #define ENETC4_PM_TEOCT(mac) (0x5200 + (mac) * 0x400) 311 312 /* Port MAC 0/1 Transmit Octets Counter */ 313 #define ENETC4_PM_TOCT(mac) (0x5208 + (mac) * 0x400) 314 315 /* Port MAC 0/1 Transmit Valid Pause Frame Counter */ 316 #define ENETC4_PM_TXPF(mac) (0x5218 + (mac) * 0x400) 317 318 /* Port MAC 0/1 Transmit Frame Counter */ 319 #define ENETC4_PM_TFRM(mac) (0x5220 + (mac) * 0x400) 320 321 /* Port MAC 0/1 Transmit Frame Check Sequence Error Counter */ 322 #define ENETC4_PM_TFCS(mac) (0x5228 + (mac) * 0x400) 323 324 /* Port MAC 0/1 Transmit VLAN Frame Counter */ 325 #define ENETC4_PM_TVLAN(mac) (0x5230 + (mac) * 0x400) 326 327 /* Port MAC 0/1 Transmit Frame Error Counter */ 328 #define ENETC4_PM_TERR(mac) (0x5238 + (mac) * 0x400) 329 330 /* Port MAC 0/1 Transmit Unicast Frame Counter */ 331 #define ENETC4_PM_TUCA(mac) (0x5240 + (mac) * 0x400) 332 333 /* Port MAC 0/1 Transmit Multicast Frame Counter */ 334 #define ENETC4_PM_TMCA(mac) (0x5248 + (mac) * 0x400) 335 336 /* Port MAC 0/1 Transmit Broadcast Frame Counter */ 337 #define ENETC4_PM_TBCA(mac) (0x5250 + (mac) * 0x400) 338 339 /* Port MAC 0/1 Transmit Packets Counter */ 340 #define ENETC4_PM_TPKT(mac) (0x5260 + (mac) * 0x400) 341 342 /* Port MAC 0/1 Transmit Undersized Packet Counter */ 343 #define ENETC4_PM_TUND(mac) (0x5268 + (mac) * 0x400) 344 345 /* Port MAC 0/1 Transmit 64-Octet Packet Counter */ 346 #define ENETC4_PM_T64(mac) (0x5270 + (mac) * 0x400) 347 348 /* Port MAC 0/1 Transmit 65 to 127-Octet Packet Counter */ 349 #define ENETC4_PM_T127(mac) (0x5278 + (mac) * 0x400) 350 351 /* Port MAC 0/1 Transmit 128 to 255-Octet Packet Counter */ 352 #define ENETC4_PM_T255(mac) (0x5280 + (mac) * 0x400) 353 354 /* Port MAC 0/1 Transmit 256 to 511-Octet Packet Counter */ 355 #define ENETC4_PM_T511(mac) (0x5288 + (mac) * 0x400) 356 357 /* Port MAC 0/1 Transmit 512 to 1023-Octet Packet Counter */ 358 #define ENETC4_PM_T1023(mac) (0x5290 + (mac) * 0x400) 359 360 /* Port MAC 0/1 Transmit 1024 to 1522-Octet Packet Counter */ 361 #define ENETC4_PM_T1522(mac) (0x5298 + (mac) * 0x400) 362 363 /* Port MAC 0/1 Transmit 1523 to TX_MTU-Octet Packet Counter */ 364 #define ENETC4_PM_T1523X(mac) (0x52a0 + (mac) * 0x400) 365 366 /* Port MAC 0/1 Transmit Control Packet Counter */ 367 #define ENETC4_PM_TCNP(mac) (0x52c0 + (mac) * 0x400) 368 369 /* Port MAC 0/1 Transmit Deferred Packet Counter */ 370 #define ENETC4_PM_TDFR(mac) (0x52d0 + (mac) * 0x400) 371 372 /* Port MAC 0/1 Transmit Multiple Collisions Counter */ 373 #define ENETC4_PM_TMCOL(mac) (0x52d8 + (mac) * 0x400) 374 375 /* Port MAC 0/1 Transmit Single Collision */ 376 #define ENETC4_PM_TSCOL(mac) (0x52e0 + (mac) * 0x400) 377 378 /* Port MAC 0/1 Transmit Late Collision Counter */ 379 #define ENETC4_PM_TLCOL(mac) (0x52e8 + (mac) * 0x400) 380 381 /* Port MAC 0/1 Transmit Excessive Collisions Counter */ 382 #define ENETC4_PM_TECOL(mac) (0x52f0 + (mac) * 0x400) 383 384 /* Port MAC 0/1 Transmit Invalid Octets Counter */ 385 #define ENETC4_PM_TIOCT(mac) (0x52f8 + (mac) * 0x400) 386 387 /* Port MAC 0 Interface Mode Control Register */ 388 #define ENETC4_PM_IF_MODE(mac) (0x5300 + (mac) * 0x400) 389 #define PM_IF_MODE_IFMODE GENMASK(2, 0) 390 #define IFMODE_XGMII 0 391 #define IFMODE_RMII 3 392 #define IFMODE_RGMII 4 393 #define IFMODE_SGMII 5 394 #define PM_IF_MODE_REVMII BIT(3) 395 #define PM_IF_MODE_M10 BIT(4) 396 #define PM_IF_MODE_HD BIT(6) 397 #define PM_IF_MODE_SSP GENMASK(14, 13) 398 #define SSP_100M 0 399 #define SSP_10M 1 400 #define SSP_1G 2 401 #define PM_IF_MODE_ENA BIT(15) 402 403 /* Port external MDIO Base address, use to access off-chip PHY */ 404 #define ENETC4_EMDIO_BASE 0x5c00 405 406 /**********************ENETC Pseudo MAC port registers************************/ 407 /* Port pseudo MAC receive octets counter (64-bit) */ 408 #define ENETC4_PPMROCR 0x5080 409 410 /* Port pseudo MAC receive unicast frame counter register (64-bit) */ 411 #define ENETC4_PPMRUFCR 0x5088 412 413 /* Port pseudo MAC receive multicast frame counter register (64-bit) */ 414 #define ENETC4_PPMRMFCR 0x5090 415 416 /* Port pseudo MAC receive broadcast frame counter register (64-bit) */ 417 #define ENETC4_PPMRBFCR 0x5098 418 419 /* Port pseudo MAC transmit octets counter (64-bit) */ 420 #define ENETC4_PPMTOCR 0x50c0 421 422 /* Port pseudo MAC transmit unicast frame counter register (64-bit) */ 423 #define ENETC4_PPMTUFCR 0x50c8 424 425 /* Port pseudo MAC transmit multicast frame counter register (64-bit) */ 426 #define ENETC4_PPMTMFCR 0x50d0 427 428 /* Port pseudo MAC transmit broadcast frame counter register (64-bit) */ 429 #define ENETC4_PPMTBFCR 0x50d8 430 431 #endif 432