1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/module.h> 4 #include <linux/bitfield.h> 5 #include <linux/delay.h> 6 #include <linux/interrupt.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/mutex.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/thermal.h> 14 15 /* SCU regs */ 16 #define EN7581_PLLRG_PROTECT 0x268 17 #define EN7581_PWD_TADC 0x2ec 18 #define EN7581_MUX_TADC GENMASK(3, 1) 19 #define EN7581_DOUT_TADC 0x2f8 20 #define EN7581_DOUT_TADC_MASK GENMASK(15, 0) 21 22 #define AN7583_MUX_TADC 0x2a0 23 #define AN7583_LOAD_ADJ GENMASK(3, 2) 24 #define AN7583_MUX_SENSOR 0x2e4 25 #define AN7583_MUX_SENSOR_MASK GENMASK(3, 1) 26 #define AN7583_DOUT_TADC 0x2f0 27 28 /* PTP_THERMAL regs */ 29 #define EN7581_TEMPMONCTL0 0x800 30 #define EN7581_SENSE3_EN BIT(3) 31 #define EN7581_SENSE2_EN BIT(2) 32 #define EN7581_SENSE1_EN BIT(1) 33 #define EN7581_SENSE0_EN BIT(0) 34 #define EN7581_TEMPMONCTL1 0x804 35 /* period unit calculated in BUS clock * 256 scaling-up */ 36 #define EN7581_PERIOD_UNIT GENMASK(9, 0) 37 #define EN7581_TEMPMONCTL2 0x808 38 #define EN7581_FILT_INTERVAL GENMASK(25, 16) 39 #define EN7581_SEN_INTERVAL GENMASK(9, 0) 40 #define EN7581_TEMPMONINT 0x80C 41 #define EN7581_STAGE3_INT_EN BIT(31) 42 #define EN7581_STAGE2_INT_EN BIT(30) 43 #define EN7581_STAGE1_INT_EN BIT(29) 44 #define EN7581_FILTER_INT_EN_3 BIT(28) 45 #define EN7581_IMMD_INT_EN3 BIT(27) 46 #define EN7581_NOHOTINTEN3 BIT(26) 47 #define EN7581_HOFSINTEN3 BIT(25) 48 #define EN7581_LOFSINTEN3 BIT(24) 49 #define EN7581_HINTEN3 BIT(23) 50 #define EN7581_CINTEN3 BIT(22) 51 #define EN7581_FILTER_INT_EN_2 BIT(21) 52 #define EN7581_FILTER_INT_EN_1 BIT(20) 53 #define EN7581_FILTER_INT_EN_0 BIT(19) 54 #define EN7581_IMMD_INT_EN2 BIT(18) 55 #define EN7581_IMMD_INT_EN1 BIT(17) 56 #define EN7581_IMMD_INT_EN0 BIT(16) 57 #define EN7581_TIME_OUT_INT_EN BIT(15) 58 #define EN7581_NOHOTINTEN2 BIT(14) 59 #define EN7581_HOFSINTEN2 BIT(13) 60 #define EN7581_LOFSINTEN2 BIT(12) 61 #define EN7581_HINTEN2 BIT(11) 62 #define EN7581_CINTEN2 BIT(10) 63 #define EN7581_NOHOTINTEN1 BIT(9) 64 #define EN7581_HOFSINTEN1 BIT(8) 65 #define EN7581_LOFSINTEN1 BIT(7) 66 #define EN7581_HINTEN1 BIT(6) 67 #define EN7581_CINTEN1 BIT(5) 68 #define EN7581_NOHOTINTEN0 BIT(4) 69 /* Similar to COLD and HOT also these seems to be swapped in documentation */ 70 #define EN7581_LOFSINTEN0 BIT(3) /* In documentation: BIT(2) */ 71 #define EN7581_HOFSINTEN0 BIT(2) /* In documentation: BIT(3) */ 72 /* It seems documentation have these swapped as the HW 73 * - Fire BIT(1) when lower than EN7581_COLD_THRE 74 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or 75 * EN7581_HOT_THRE 76 */ 77 #define EN7581_CINTEN0 BIT(1) /* In documentation: BIT(0) */ 78 #define EN7581_HINTEN0 BIT(0) /* In documentation: BIT(1) */ 79 #define EN7581_TEMPMONINTSTS 0x810 80 #define EN7581_STAGE3_INT_STAT BIT(31) 81 #define EN7581_STAGE2_INT_STAT BIT(30) 82 #define EN7581_STAGE1_INT_STAT BIT(29) 83 #define EN7581_FILTER_INT_STAT_3 BIT(28) 84 #define EN7581_IMMD_INT_STS3 BIT(27) 85 #define EN7581_NOHOTINTSTS3 BIT(26) 86 #define EN7581_HOFSINTSTS3 BIT(25) 87 #define EN7581_LOFSINTSTS3 BIT(24) 88 #define EN7581_HINTSTS3 BIT(23) 89 #define EN7581_CINTSTS3 BIT(22) 90 #define EN7581_FILTER_INT_STAT_2 BIT(21) 91 #define EN7581_FILTER_INT_STAT_1 BIT(20) 92 #define EN7581_FILTER_INT_STAT_0 BIT(19) 93 #define EN7581_IMMD_INT_STS2 BIT(18) 94 #define EN7581_IMMD_INT_STS1 BIT(17) 95 #define EN7581_IMMD_INT_STS0 BIT(16) 96 #define EN7581_TIME_OUT_INT_STAT BIT(15) 97 #define EN7581_NOHOTINTSTS2 BIT(14) 98 #define EN7581_HOFSINTSTS2 BIT(13) 99 #define EN7581_LOFSINTSTS2 BIT(12) 100 #define EN7581_HINTSTS2 BIT(11) 101 #define EN7581_CINTSTS2 BIT(10) 102 #define EN7581_NOHOTINTSTS1 BIT(9) 103 #define EN7581_HOFSINTSTS1 BIT(8) 104 #define EN7581_LOFSINTSTS1 BIT(7) 105 #define EN7581_HINTSTS1 BIT(6) 106 #define EN7581_CINTSTS1 BIT(5) 107 #define EN7581_NOHOTINTSTS0 BIT(4) 108 /* Similar to COLD and HOT also these seems to be swapped in documentation */ 109 #define EN7581_LOFSINTSTS0 BIT(3) /* In documentation: BIT(2) */ 110 #define EN7581_HOFSINTSTS0 BIT(2) /* In documentation: BIT(3) */ 111 /* It seems documentation have these swapped as the HW 112 * - Fire BIT(1) when lower than EN7581_COLD_THRE 113 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or 114 * EN7581_HOT_THRE 115 * 116 * To clear things, we swap the define but we keep them documented here. 117 */ 118 #define EN7581_CINTSTS0 BIT(1) /* In documentation: BIT(0) */ 119 #define EN7581_HINTSTS0 BIT(0) /* In documentation: BIT(1)*/ 120 /* Monitor will take the bigger threshold between HOT2NORMAL and HOT 121 * and will fire both HOT2NORMAL and HOT interrupt when higher than the 2 122 * 123 * It has also been observed that not setting HOT2NORMAL makes the monitor 124 * treat COLD threshold as HOT2NORMAL. 125 */ 126 #define EN7581_TEMPH2NTHRE 0x824 127 /* It seems HOT2NORMAL is actually NORMAL2HOT */ 128 #define EN7581_HOT2NORMAL_THRE GENMASK(11, 0) 129 #define EN7581_TEMPHTHRE 0x828 130 #define EN7581_HOT_THRE GENMASK(11, 0) 131 /* Monitor will use this as HOT2NORMAL (fire interrupt when lower than...)*/ 132 #define EN7581_TEMPCTHRE 0x82c 133 #define EN7581_COLD_THRE GENMASK(11, 0) 134 /* Also LOW and HIGH offset register are swapped */ 135 #define EN7581_TEMPOFFSETL 0x830 /* In documentation: 0x834 */ 136 #define EN7581_LOW_OFFSET GENMASK(11, 0) 137 #define EN7581_TEMPOFFSETH 0x834 /* In documentation: 0x830 */ 138 #define EN7581_HIGH_OFFSET GENMASK(11, 0) 139 #define EN7581_TEMPMSRCTL0 0x838 140 #define EN7581_MSRCTL3 GENMASK(11, 9) 141 #define EN7581_MSRCTL2 GENMASK(8, 6) 142 #define EN7581_MSRCTL1 GENMASK(5, 3) 143 #define EN7581_MSRCTL0 GENMASK(2, 0) 144 #define EN7581_TEMPADCVALIDADDR 0x878 145 #define EN7581_ADC_VALID_ADDR GENMASK(31, 0) 146 #define EN7581_TEMPADCVOLTADDR 0x87c 147 #define EN7581_ADC_VOLT_ADDR GENMASK(31, 0) 148 #define EN7581_TEMPRDCTRL 0x880 149 /* 150 * NOTICE: AHB have this set to 0 by default. Means that 151 * the same addr is used for ADC volt and valid reading. 152 * In such case, VALID ADDR is used and volt addr is ignored. 153 */ 154 #define EN7581_RD_CTRL_DIFF BIT(0) 155 #define EN7581_TEMPADCVALIDMASK 0x884 156 #define EN7581_ADV_RD_VALID_POLARITY BIT(5) 157 #define EN7581_ADV_RD_VALID_POS GENMASK(4, 0) 158 #define EN7581_TEMPADCVOLTAGESHIFT 0x888 159 #define EN7581_ADC_VOLTAGE_SHIFT GENMASK(4, 0) 160 /* 161 * Same values for each CTL. 162 * Can operate in: 163 * - 1 sample 164 * - 2 sample and make average of them 165 * - 4,6,10,16 sample, drop max and min and make average of them 166 */ 167 #define EN7581_MSRCTL_1SAMPLE 0x0 168 #define EN7581_MSRCTL_AVG2SAMPLE 0x1 169 #define EN7581_MSRCTL_4SAMPLE_MAX_MIX_AVG2 0x2 170 #define EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4 0x3 171 #define EN7581_MSRCTL_10SAMPLE_MAX_MIX_AVG8 0x4 172 #define EN7581_MSRCTL_18SAMPLE_MAX_MIX_AVG16 0x5 173 #define EN7581_TEMPAHBPOLL 0x840 174 #define EN7581_ADC_POLL_INTVL GENMASK(31, 0) 175 /* PTPSPARE0,2 reg are used to store efuse info for calibrated temp offset */ 176 #define EN7581_EFUSE_TEMP_OFFSET_REG 0xf20 /* PTPSPARE0 */ 177 #define EN7581_EFUSE_TEMP_OFFSET GENMASK(31, 16) 178 #define EN7581_PTPSPARE1 0xf24 /* PTPSPARE1 */ 179 #define EN7581_EFUSE_TEMP_CPU_SENSOR_REG 0xf28 /* PTPSPARE2 */ 180 181 #define EN7581_SLOPE_X100_DIO_DEFAULT 5645 182 #define EN7581_SLOPE_X100_DIO_AVS 5645 183 184 #define EN7581_INIT_TEMP_CPK_X10 300 185 #define EN7581_INIT_TEMP_FTK_X10 620 186 #define EN7581_INIT_TEMP_NONK_X10 550 187 188 #define EN7581_SCU_THERMAL_PROTECT_KEY 0x12 189 #define EN7581_SCU_THERMAL_MUX_DIODE1 0x7 190 191 #define AN7583_SCU_THERMAL_PROTECT_KEY 0x80 192 #define AN7583_NUM_SENSOR 3 193 194 #define AIROHA_THERMAL_NO_MUX_SENSOR -1 195 #define AIROHA_THERMAL_MUX_TRIES 3 196 197 /* Convert temp to raw value as read from ADC ((((temp / 100) - init) * slope) / 1000) + offset */ 198 #define TEMP_TO_RAW(priv, temp) ((((((temp) / 100) - (priv)->init_temp) * \ 199 (priv)->default_slope) / 1000) + \ 200 (priv)->default_offset) 201 202 /* Convert raw to temp ((((temp - offset) * 1000) / slope + init) * 100) */ 203 #define RAW_TO_TEMP(priv, raw) (((((raw) - (priv)->default_offset) * 1000) / \ 204 (priv)->default_slope + \ 205 (priv)->init_temp) * 100) 206 207 #define AIROHA_MAX_SAMPLES 6 208 209 /* 210 * AN7583 supports all these ADC mux but the original driver 211 * always checked temp with the AN7583_BGP_TEMP_SENSOR. 212 * Assume using the other sensor temperature is invalid and 213 * always read from AN7583_BGP_TEMP_SENSOR. 214 * 215 * On top of this it's defined that AN7583 supports 3 216 * sensor: AN7583_BGP_TEMP_SENSOR, AN7583_GBE_TEMP_SENSOR, 217 * AN7583_CPU_TEMP_SENSOR. 218 * 219 * Provide the ADC mux for reference. 220 */ 221 enum an7583_thermal_adc_mux { 222 AN7583_BGP_TEMP_SENSOR, 223 AN7583_PAD_AVS, 224 AN7583_CORE_POWER, 225 AN7583_AVSDAC_OUT, 226 AN7583_VCM, 227 AN7583_GBE_TEMP_SENSOR, 228 AN7583_CPU_TEMP_SENSOR, 229 230 AN7583_ADC_MUX_MAX, 231 }; 232 233 enum an7583_thermal_diode_mux { 234 AN7583_D0_TADC, 235 AN7583_ZERO_TADC, 236 AN7583_D1_TADC, 237 }; 238 239 enum airoha_thermal_chip_scu_field { 240 AIROHA_THERMAL_DOUT_TADC, 241 AIROHA_THERMAL_MUX_SENSOR, 242 AIROHA_THERMAL_MUX_TADC, 243 244 /* keep last */ 245 AIROHA_THERMAL_FIELD_MAX, 246 }; 247 248 struct airoha_thermal_zone { 249 struct airoha_thermal_priv *priv; 250 int sensor; 251 }; 252 253 struct airoha_thermal_priv { 254 struct regmap *map; 255 struct regmap *chip_scu; 256 struct regmap_field *chip_scu_fields[AIROHA_THERMAL_FIELD_MAX]; 257 struct resource scu_adc_res; 258 259 u32 pllrg_protect; 260 /* Serialises mux selection and ADC sampling */ 261 struct mutex lock; 262 263 struct thermal_zone_device *tz; 264 int init_temp; 265 int default_slope; 266 int default_offset; 267 }; 268 269 struct airoha_thermal_soc_data { 270 u32 pllrg_protect; 271 /* Sensor mux value per zone, NULL without a sensor mux */ 272 const int *sensors; 273 int num_sensors; 274 275 const struct thermal_zone_device_ops *thdev_ops; 276 int (*probe)(struct platform_device *pdev, 277 struct airoha_thermal_priv *priv); 278 int (*post_probe)(struct platform_device *pdev); 279 }; 280 281 static const unsigned int an7583_thermal_coeff[AN7583_ADC_MUX_MAX] = { 282 [AN7583_BGP_TEMP_SENSOR] = 973, 283 [AN7583_GBE_TEMP_SENSOR] = 995, 284 [AN7583_CPU_TEMP_SENSOR] = 1035, 285 }; 286 287 static const unsigned int an7583_thermal_slope[AN7583_ADC_MUX_MAX] = { 288 [AN7583_BGP_TEMP_SENSOR] = 7440, 289 [AN7583_GBE_TEMP_SENSOR] = 7620, 290 [AN7583_CPU_TEMP_SENSOR] = 8390, 291 }; 292 293 static const unsigned int an7583_thermal_offset[AN7583_ADC_MUX_MAX] = { 294 [AN7583_BGP_TEMP_SENSOR] = 294, 295 [AN7583_GBE_TEMP_SENSOR] = 298, 296 [AN7583_CPU_TEMP_SENSOR] = 344, 297 }; 298 299 static int airoha_get_thermal_ADC(struct airoha_thermal_priv *priv) 300 { 301 u32 val; 302 303 regmap_field_read(priv->chip_scu_fields[AIROHA_THERMAL_DOUT_TADC], 304 &val); 305 return val; 306 } 307 308 static bool airoha_thermal_mux_holds(struct airoha_thermal_priv *priv, 309 int tdac_idx, int sensor_idx) 310 { 311 unsigned int val; 312 313 if (regmap_field_read(priv->chip_scu_fields[AIROHA_THERMAL_MUX_TADC], &val) || 314 val != tdac_idx) 315 return false; 316 317 if (sensor_idx == AIROHA_THERMAL_NO_MUX_SENSOR) 318 return true; 319 320 return !regmap_field_read(priv->chip_scu_fields[AIROHA_THERMAL_MUX_SENSOR], &val) && 321 val == sensor_idx; 322 } 323 324 static void airoha_set_thermal_mux(struct airoha_thermal_priv *priv, 325 int tdac_idx, int sensor_idx) 326 { 327 int tries = AIROHA_THERMAL_MUX_TRIES; 328 u32 pllrg; 329 330 /* Save PLLRG current value */ 331 regmap_read(priv->chip_scu, EN7581_PLLRG_PROTECT, &pllrg); 332 333 /* Give access to Thermal regs */ 334 regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, 335 priv->pllrg_protect); 336 337 /* 338 * Configure Thermal Sensor mux to sensor_idx and Thermal ADC mux to 339 * tdac_idx. Writes can be dropped silently, so read them back. 340 * (if not supported, sensor_idx is AIROHA_THERMAL_NO_MUX_SENSOR) 341 */ 342 do { 343 if (sensor_idx != AIROHA_THERMAL_NO_MUX_SENSOR) 344 regmap_field_write(priv->chip_scu_fields[AIROHA_THERMAL_MUX_SENSOR], 345 sensor_idx); 346 regmap_field_write(priv->chip_scu_fields[AIROHA_THERMAL_MUX_TADC], 347 tdac_idx); 348 } while (!airoha_thermal_mux_holds(priv, tdac_idx, sensor_idx) && --tries); 349 350 /* Restore PLLRG value on exit */ 351 regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, pllrg); 352 353 /* Sleep 10 ms for Thermal ADC to enable */ 354 usleep_range(10 * USEC_PER_MSEC, 11 * USEC_PER_MSEC); 355 } 356 357 static int en7581_thermal_get_temp(struct thermal_zone_device *tz, int *temp) 358 { 359 struct airoha_thermal_zone *zone = thermal_zone_device_priv(tz); 360 struct airoha_thermal_priv *priv = zone->priv; 361 int min_value, max_value, avg_value, value; 362 int i; 363 364 avg_value = 0; 365 min_value = INT_MAX; 366 max_value = INT_MIN; 367 368 for (i = 0; i < AIROHA_MAX_SAMPLES; i++) { 369 value = airoha_get_thermal_ADC(priv); 370 min_value = min(value, min_value); 371 max_value = max(value, max_value); 372 avg_value += value; 373 } 374 375 /* Drop min and max and average for the remaining sample */ 376 avg_value -= (min_value + max_value); 377 avg_value /= AIROHA_MAX_SAMPLES - 2; 378 379 *temp = RAW_TO_TEMP(priv, avg_value); 380 return 0; 381 } 382 383 static int en7581_thermal_set_trips(struct thermal_zone_device *tz, int low, 384 int high) 385 { 386 struct airoha_thermal_zone *zone = thermal_zone_device_priv(tz); 387 struct airoha_thermal_priv *priv = zone->priv; 388 bool enable_monitor = false; 389 390 if (high != INT_MAX) { 391 /* Validate high and clamp it a supported value */ 392 high = clamp_t(int, high, RAW_TO_TEMP(priv, 0), 393 RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK))); 394 395 /* We offset the high temp of 1°C to trigger correct event */ 396 regmap_write(priv->map, EN7581_TEMPOFFSETH, 397 TEMP_TO_RAW(priv, high) >> 4); 398 399 enable_monitor = true; 400 } 401 402 if (low != -INT_MAX) { 403 /* Validate low and clamp it to a supported value */ 404 low = clamp_t(int, low, RAW_TO_TEMP(priv, 0), 405 RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK))); 406 407 /* We offset the low temp of 1°C to trigger correct event */ 408 regmap_write(priv->map, EN7581_TEMPOFFSETL, 409 TEMP_TO_RAW(priv, low) >> 4); 410 411 enable_monitor = true; 412 } 413 414 /* Enable sensor 0 monitor after trip are set */ 415 if (enable_monitor) 416 regmap_write(priv->map, EN7581_TEMPMONCTL0, EN7581_SENSE0_EN); 417 418 return 0; 419 } 420 421 static const struct thermal_zone_device_ops en7581_thdev_ops = { 422 .get_temp = en7581_thermal_get_temp, 423 .set_trips = en7581_thermal_set_trips, 424 }; 425 426 static irqreturn_t en7581_thermal_irq(int irq, void *data) 427 { 428 struct airoha_thermal_priv *priv = data; 429 enum thermal_notify_event event; 430 bool update = false; 431 u32 status = 0; 432 433 regmap_read(priv->map, EN7581_TEMPMONINTSTS, &status); 434 switch (status & (EN7581_HOFSINTSTS0 | EN7581_LOFSINTSTS0)) { 435 case EN7581_HOFSINTSTS0: 436 event = THERMAL_TRIP_VIOLATED; 437 update = true; 438 break; 439 case EN7581_LOFSINTSTS0: 440 event = THERMAL_EVENT_UNSPECIFIED; 441 update = true; 442 break; 443 default: 444 /* Should be impossible as we enable only these Interrupt */ 445 break; 446 } 447 448 /* Reset Interrupt */ 449 regmap_write(priv->map, EN7581_TEMPMONINTSTS, status); 450 451 if (update) 452 thermal_zone_device_update(priv->tz, event); 453 454 return IRQ_HANDLED; 455 } 456 457 static void en7581_thermal_setup_adc_val(struct device *dev, 458 struct airoha_thermal_priv *priv) 459 { 460 u32 efuse_calib_info = 0; 461 u32 cpu_sensor = 0; 462 463 /* Setup Thermal Sensor to ADC mode and setup the mux to DIODE1 */ 464 airoha_set_thermal_mux(priv, EN7581_SCU_THERMAL_MUX_DIODE1, 465 AIROHA_THERMAL_NO_MUX_SENSOR); 466 467 regmap_read(priv->map, EN7581_EFUSE_TEMP_OFFSET_REG, &efuse_calib_info); 468 if (efuse_calib_info) { 469 priv->default_offset = FIELD_GET(EN7581_EFUSE_TEMP_OFFSET, efuse_calib_info); 470 /* Different slope are applied if the sensor is used for CPU or for package */ 471 regmap_read(priv->map, EN7581_EFUSE_TEMP_CPU_SENSOR_REG, &cpu_sensor); 472 if (cpu_sensor) { 473 priv->default_slope = EN7581_SLOPE_X100_DIO_DEFAULT; 474 priv->init_temp = EN7581_INIT_TEMP_FTK_X10; 475 } else { 476 priv->default_slope = EN7581_SLOPE_X100_DIO_AVS; 477 priv->init_temp = EN7581_INIT_TEMP_CPK_X10; 478 } 479 } else { 480 priv->default_offset = airoha_get_thermal_ADC(priv); 481 priv->default_slope = EN7581_SLOPE_X100_DIO_DEFAULT; 482 priv->init_temp = EN7581_INIT_TEMP_NONK_X10; 483 dev_info(dev, "missing thermal calibration EFUSE, using non calibrated value\n"); 484 } 485 } 486 487 static void en7581_thermal_setup_monitor(struct airoha_thermal_priv *priv) 488 { 489 /* Set measure mode */ 490 regmap_write(priv->map, EN7581_TEMPMSRCTL0, 491 FIELD_PREP(EN7581_MSRCTL0, EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4)); 492 493 /* 494 * Configure ADC valid reading addr 495 * The AHB temp monitor system doesn't have direct access to the 496 * thermal sensor. It does instead work by providing various 497 * addresses to configure how to access and setup an ADC for the 498 * sensor. EN7581 supports only one sensor hence the 499 * implementation is greatly simplified but the AHB supports 500 * up to 4 different sensors from the same ADC that can be 501 * switched by tuning the ADC mux or writing address. 502 * 503 * We set valid instead of volt as we don't enable valid/volt 504 * split reading and AHB read valid addr in such case. 505 */ 506 regmap_write(priv->map, EN7581_TEMPADCVALIDADDR, 507 priv->scu_adc_res.start + EN7581_DOUT_TADC); 508 509 /* 510 * Configure valid bit on a fake value of bit 16. The ADC outputs 511 * max of 2 bytes for voltage. 512 */ 513 regmap_write(priv->map, EN7581_TEMPADCVALIDMASK, 514 FIELD_PREP(EN7581_ADV_RD_VALID_POS, 16)); 515 516 /* 517 * AHB supports max 12 bytes for ADC voltage. Shift the read 518 * value 4 bit to the right. Precision lost by this is minimal 519 * in the order of half a °C and is acceptable in the context 520 * of triggering interrupt in critical condition. 521 */ 522 regmap_write(priv->map, EN7581_TEMPADCVOLTAGESHIFT, 523 FIELD_PREP(EN7581_ADC_VOLTAGE_SHIFT, 4)); 524 525 /* BUS clock is 300MHz counting unit is 3 * 68.64 * 256 = 52.715us */ 526 regmap_write(priv->map, EN7581_TEMPMONCTL1, 527 FIELD_PREP(EN7581_PERIOD_UNIT, 3)); 528 529 /* 530 * filt interval is 1 * 52.715us = 52.715us, 531 * sen interval is 379 * 52.715us = 19.97ms 532 */ 533 regmap_write(priv->map, EN7581_TEMPMONCTL2, 534 FIELD_PREP(EN7581_FILT_INTERVAL, 1) | 535 FIELD_PREP(EN7581_SEN_INTERVAL, 379)); 536 537 /* AHB poll is set to 146 * 68.64 = 10.02us */ 538 regmap_write(priv->map, EN7581_TEMPAHBPOLL, 539 FIELD_PREP(EN7581_ADC_POLL_INTVL, 146)); 540 } 541 542 static const struct regmap_config en7581_thermal_regmap_config = { 543 .reg_bits = 32, 544 .reg_stride = 4, 545 .val_bits = 32, 546 }; 547 548 static const struct reg_field en7581_chip_scu_fields[AIROHA_THERMAL_FIELD_MAX] = { 549 [AIROHA_THERMAL_DOUT_TADC] = REG_FIELD(EN7581_DOUT_TADC, 0, 15), 550 [AIROHA_THERMAL_MUX_TADC] = REG_FIELD(EN7581_PWD_TADC, 1, 3), 551 }; 552 553 static int en7581_thermal_probe(struct platform_device *pdev, 554 struct airoha_thermal_priv *priv) 555 { 556 struct device_node *chip_scu_np; 557 struct device *dev = &pdev->dev; 558 void __iomem *base; 559 int i; 560 561 base = devm_platform_ioremap_resource(pdev, 0); 562 if (IS_ERR(base)) 563 return PTR_ERR(base); 564 565 priv->map = devm_regmap_init_mmio(dev, base, 566 &en7581_thermal_regmap_config); 567 if (IS_ERR(priv->map)) 568 return PTR_ERR(priv->map); 569 570 chip_scu_np = of_parse_phandle(dev->of_node, "airoha,chip-scu", 0); 571 if (!chip_scu_np) 572 return -EINVAL; 573 574 priv->chip_scu = syscon_node_to_regmap(chip_scu_np); 575 if (IS_ERR(priv->chip_scu)) 576 return PTR_ERR(priv->chip_scu); 577 578 for (i = 0; i < AIROHA_THERMAL_FIELD_MAX; i++) { 579 struct regmap_field *field; 580 581 /* Skip registering MUX_SENSOR field as not supported */ 582 if (i == AIROHA_THERMAL_MUX_SENSOR) 583 continue; 584 585 field = devm_regmap_field_alloc(dev, priv->chip_scu, 586 en7581_chip_scu_fields[i]); 587 if (IS_ERR(field)) { 588 of_node_put(chip_scu_np); 589 return PTR_ERR(field); 590 } 591 592 priv->chip_scu_fields[i] = field; 593 } 594 595 of_address_to_resource(chip_scu_np, 0, &priv->scu_adc_res); 596 of_node_put(chip_scu_np); 597 598 en7581_thermal_setup_monitor(priv); 599 en7581_thermal_setup_adc_val(dev, priv); 600 601 return 0; 602 } 603 604 static int en7581_thermal_post_probe(struct platform_device *pdev) 605 { 606 struct airoha_thermal_priv *priv = platform_get_drvdata(pdev); 607 int irq, ret; 608 609 /* After zone registration: the handler uses priv->tz */ 610 irq = platform_get_irq(pdev, 0); 611 if (irq < 0) 612 return irq; 613 614 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 615 en7581_thermal_irq, IRQF_ONESHOT, 616 pdev->name, priv); 617 if (ret) 618 return ret; 619 620 /* Enable LOW and HIGH interrupt (if supported) */ 621 regmap_write(priv->map, EN7581_TEMPMONINT, 622 EN7581_HOFSINTEN0 | EN7581_LOFSINTEN0); 623 624 return 0; 625 } 626 627 static int an7583_thermal_read_diode(struct airoha_thermal_priv *priv, 628 int diode, int sensor_idx, int *val) 629 { 630 airoha_set_thermal_mux(priv, diode, sensor_idx); 631 *val = airoha_get_thermal_ADC(priv); 632 633 return airoha_thermal_mux_holds(priv, diode, sensor_idx) ? 0 : -EAGAIN; 634 } 635 636 static int an7583_thermal_read_diodes(struct airoha_thermal_priv *priv, 637 int sensor_idx, int *zero, int *d0, 638 int *d1) 639 { 640 int ret; 641 642 ret = an7583_thermal_read_diode(priv, AN7583_ZERO_TADC, sensor_idx, zero); 643 if (ret) 644 return ret; 645 646 ret = an7583_thermal_read_diode(priv, AN7583_D0_TADC, sensor_idx, d0); 647 if (ret) 648 return ret; 649 650 return an7583_thermal_read_diode(priv, AN7583_D1_TADC, sensor_idx, d1); 651 } 652 653 static int an7583_thermal_get_temp(struct thermal_zone_device *tz, int *temp) 654 { 655 struct airoha_thermal_zone *zone = thermal_zone_device_priv(tz); 656 struct airoha_thermal_priv *priv = zone->priv; 657 int sensor_idx = zone->sensor; 658 int delta_diode, delta_gain; 659 int coeff, slope, offset; 660 int tries = AIROHA_THERMAL_MUX_TRIES; 661 int ret; 662 663 int diode_zero, diode_d0, diode_d1; 664 665 coeff = an7583_thermal_coeff[sensor_idx]; 666 slope = an7583_thermal_slope[sensor_idx]; 667 offset = an7583_thermal_offset[sensor_idx]; 668 669 mutex_lock(&priv->lock); 670 do { 671 ret = an7583_thermal_read_diodes(priv, sensor_idx, &diode_zero, 672 &diode_d0, &diode_d1); 673 } while (ret == -EAGAIN && --tries); 674 mutex_unlock(&priv->lock); 675 if (ret) 676 return ret; 677 678 delta_diode = diode_d1 - diode_d0; 679 delta_gain = (delta_diode * coeff) / 100 + (diode_zero - diode_d1); 680 if (!delta_gain) 681 return -EINVAL; 682 683 *temp = (slope * delta_diode * 10) / delta_gain - offset * 10; 684 *temp *= 100; 685 686 return 0; 687 } 688 689 static const struct thermal_zone_device_ops an7583_tz_ops = { 690 .get_temp = an7583_thermal_get_temp, 691 }; 692 693 static const struct reg_field an7583_chip_scu_fields[AIROHA_THERMAL_FIELD_MAX] = { 694 [AIROHA_THERMAL_DOUT_TADC] = REG_FIELD(AN7583_DOUT_TADC, 0, 31), 695 [AIROHA_THERMAL_MUX_TADC] = REG_FIELD(AN7583_MUX_TADC, 2, 3), 696 [AIROHA_THERMAL_MUX_SENSOR] = REG_FIELD(AN7583_MUX_SENSOR, 1, 3), 697 }; 698 699 static int an7583_thermal_probe(struct platform_device *pdev, 700 struct airoha_thermal_priv *priv) 701 { 702 struct device *dev = &pdev->dev; 703 int i; 704 705 priv->chip_scu = device_node_to_regmap(dev->of_node); 706 if (IS_ERR(priv->chip_scu)) 707 return PTR_ERR(priv->chip_scu); 708 709 for (i = 0; i < AIROHA_THERMAL_FIELD_MAX; i++) { 710 struct regmap_field *field; 711 712 field = devm_regmap_field_alloc(dev, priv->chip_scu, 713 an7583_chip_scu_fields[i]); 714 if (IS_ERR(field)) 715 return PTR_ERR(field); 716 717 priv->chip_scu_fields[i] = field; 718 } 719 720 return 0; 721 } 722 723 static int airoha_thermal_probe(struct platform_device *pdev) 724 { 725 const struct airoha_thermal_soc_data *soc_data; 726 struct airoha_thermal_priv *priv; 727 struct device *dev = &pdev->dev; 728 int ret, i; 729 730 soc_data = device_get_match_data(dev); 731 732 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 733 if (!priv) 734 return -ENOMEM; 735 736 priv->pllrg_protect = soc_data->pllrg_protect; 737 738 ret = devm_mutex_init(dev, &priv->lock); 739 if (ret) 740 return ret; 741 742 if (!soc_data->probe) 743 return -EINVAL; 744 745 ret = soc_data->probe(pdev, priv); 746 if (ret) 747 return ret; 748 749 /* register of thermal sensor and get info from DT */ 750 for (i = 0; i < soc_data->num_sensors; i++) { 751 struct airoha_thermal_zone *zone; 752 struct thermal_zone_device *tz; 753 754 zone = devm_kzalloc(dev, sizeof(*zone), GFP_KERNEL); 755 if (!zone) 756 return -ENOMEM; 757 758 zone->priv = priv; 759 zone->sensor = soc_data->sensors ? soc_data->sensors[i] : 760 AIROHA_THERMAL_NO_MUX_SENSOR; 761 762 tz = devm_thermal_of_zone_register(dev, i, zone, 763 soc_data->thdev_ops); 764 if (IS_ERR(tz)) { 765 /* A DT may describe fewer zones than sensors */ 766 if (i && PTR_ERR(tz) == -ENODEV) 767 continue; 768 769 dev_err(dev, "register thermal zone %d failed\n", i); 770 return PTR_ERR(tz); 771 } 772 773 if (!i) 774 priv->tz = tz; 775 } 776 777 platform_set_drvdata(pdev, priv); 778 779 return soc_data->post_probe ? soc_data->post_probe(pdev) : 0; 780 } 781 782 /* The bandgap sensor stays zone 0 */ 783 static const int an7583_zone_sensors[AN7583_NUM_SENSOR] = { 784 AN7583_BGP_TEMP_SENSOR, 785 AN7583_GBE_TEMP_SENSOR, 786 AN7583_CPU_TEMP_SENSOR, 787 }; 788 789 static const struct airoha_thermal_soc_data en7581_data = { 790 .num_sensors = 1, 791 .pllrg_protect = EN7581_SCU_THERMAL_PROTECT_KEY, 792 .thdev_ops = &en7581_thdev_ops, 793 .probe = &en7581_thermal_probe, 794 .post_probe = &en7581_thermal_post_probe, 795 }; 796 797 static const struct airoha_thermal_soc_data an7583_data = { 798 .sensors = an7583_zone_sensors, 799 .num_sensors = AN7583_NUM_SENSOR, 800 .pllrg_protect = AN7583_SCU_THERMAL_PROTECT_KEY, 801 .thdev_ops = &an7583_tz_ops, 802 .probe = &an7583_thermal_probe, 803 }; 804 805 static const struct of_device_id airoha_thermal_match[] = { 806 { .compatible = "airoha,en7581-thermal", .data = &en7581_data }, 807 { .compatible = "airoha,an7583-chip-scu", .data = &an7583_data }, 808 {}, 809 }; 810 MODULE_DEVICE_TABLE(of, airoha_thermal_match); 811 812 static struct platform_driver airoha_thermal_driver = { 813 .driver = { 814 .name = "airoha-thermal", 815 .of_match_table = airoha_thermal_match, 816 }, 817 .probe = airoha_thermal_probe, 818 }; 819 820 module_platform_driver(airoha_thermal_driver); 821 822 MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>"); 823 MODULE_DESCRIPTION("Airoha thermal driver"); 824 MODULE_LICENSE("GPL"); 825