1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
4 * All rights reserved.
5 *
6 * ESWIN EIC7700 Clk Provider Driver
7 *
8 * Authors:
9 * Yifeng Huang <huangyifeng@eswincomputing.com>
10 * Xuyang Dong <dongxuyang@eswincomputing.com>
11 */
12
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/platform_device.h>
16
17 #include <dt-bindings/clock/eswin,eic7700-clock.h>
18
19 #include "common.h"
20
21 /* REG OFFSET OF SYS-CRG */
22 #define EIC7700_REG_OFFSET_SPLL0_CFG_0 0x0
23 #define EIC7700_REG_OFFSET_SPLL0_CFG_1 0x4
24 #define EIC7700_REG_OFFSET_SPLL0_CFG_2 0x8
25 #define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL 0xC
26 #define EIC7700_REG_OFFSET_SPLL0_SSC 0x10
27 #define EIC7700_REG_OFFSET_SPLL1_CFG_0 0x14
28 #define EIC7700_REG_OFFSET_SPLL1_CFG_1 0x18
29 #define EIC7700_REG_OFFSET_SPLL1_CFG_2 0x1C
30 #define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL 0x20
31 #define EIC7700_REG_OFFSET_SPLL1_SSC 0x24
32 #define EIC7700_REG_OFFSET_SPLL2_CFG_0 0x28
33 #define EIC7700_REG_OFFSET_SPLL2_CFG_1 0x2C
34 #define EIC7700_REG_OFFSET_SPLL2_CFG_2 0x30
35 #define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL 0x34
36 #define EIC7700_REG_OFFSET_SPLL2_SSC 0x38
37 #define EIC7700_REG_OFFSET_VPLL_CFG_0 0x3C
38 #define EIC7700_REG_OFFSET_VPLL_CFG_1 0x40
39 #define EIC7700_REG_OFFSET_VPLL_CFG_2 0x44
40 #define EIC7700_REG_OFFSET_VPLL_DSKEWCAL 0x48
41 #define EIC7700_REG_OFFSET_VPLL_SSC 0x4C
42 #define EIC7700_REG_OFFSET_APLL_CFG_0 0x50
43 #define EIC7700_REG_OFFSET_APLL_CFG_1 0x54
44 #define EIC7700_REG_OFFSET_APLL_CFG_2 0x58
45 #define EIC7700_REG_OFFSET_APLL_DSKEWCAL 0x5C
46 #define EIC7700_REG_OFFSET_APLL_SSC 0x60
47 #define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0 0x64
48 #define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1 0x68
49 #define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2 0x6C
50 #define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0x70
51 #define EIC7700_REG_OFFSET_MCPUT_PLL_SSC 0x74
52 #define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0 0x78
53 #define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1 0x7C
54 #define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2 0x80
55 #define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL 0x84
56 #define EIC7700_REG_OFFSET_DDRT_PLL_SSC 0x88
57 #define EIC7700_REG_OFFSET_PLL_STATUS 0xA4
58 #define EIC7700_REG_OFFSET_NOC 0x100
59 #define EIC7700_REG_OFFSET_BOOTSPI 0x104
60 #define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK 0x108
61 #define EIC7700_REG_OFFSET_SCPU_CORE 0x10C
62 #define EIC7700_REG_OFFSET_SCPU_BUSCLK 0x110
63 #define EIC7700_REG_OFFSET_LPCPU_CORE 0x114
64 #define EIC7700_REG_OFFSET_LPCPU_BUSCLK 0x118
65 #define EIC7700_REG_OFFSET_TCU_ACLK 0x11C
66 #define EIC7700_REG_OFFSET_TCU_CFG 0x120
67 #define EIC7700_REG_OFFSET_DDR 0x124
68 #define EIC7700_REG_OFFSET_DDR1 0x128
69 #define EIC7700_REG_OFFSET_GPU_ACLK 0x12C
70 #define EIC7700_REG_OFFSET_GPU_CFG 0x130
71 #define EIC7700_REG_OFFSET_GPU_GRAY 0x134
72 #define EIC7700_REG_OFFSET_DSP_ACLK 0x138
73 #define EIC7700_REG_OFFSET_DSP_CFG 0x13C
74 #define EIC7700_REG_OFFSET_D2D_ACLK 0x140
75 #define EIC7700_REG_OFFSET_D2D_CFG 0x144
76 #define EIC7700_REG_OFFSET_HSP_ACLK 0x148
77 #define EIC7700_REG_OFFSET_HSP_CFG 0x14C
78 #define EIC7700_REG_OFFSET_SATA_RBC 0x150
79 #define EIC7700_REG_OFFSET_SATA_OOB 0x154
80 #define EIC7700_REG_OFFSET_ETH0 0x158
81 #define EIC7700_REG_OFFSET_ETH1 0x15C
82 #define EIC7700_REG_OFFSET_MSHC0_CORE 0x160
83 #define EIC7700_REG_OFFSET_MSHC1_CORE 0x164
84 #define EIC7700_REG_OFFSET_MSHC2_CORE 0x168
85 #define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK 0x16C
86 #define EIC7700_REG_OFFSET_PCIE_ACLK 0x170
87 #define EIC7700_REG_OFFSET_PCIE_CFG 0x174
88 #define EIC7700_REG_OFFSET_NPU_ACLK 0x178
89 #define EIC7700_REG_OFFSET_NPU_LLC 0x17C
90 #define EIC7700_REG_OFFSET_NPU_CORE 0x180
91 #define EIC7700_REG_OFFSET_VI_DWCLK 0x184
92 #define EIC7700_REG_OFFSET_VI_ACLK 0x188
93 #define EIC7700_REG_OFFSET_VI_DIG_ISP 0x18C
94 #define EIC7700_REG_OFFSET_VI_DVP 0x190
95 #define EIC7700_REG_OFFSET_VI_SHUTTER0 0x194
96 #define EIC7700_REG_OFFSET_VI_SHUTTER1 0x198
97 #define EIC7700_REG_OFFSET_VI_SHUTTER2 0x19C
98 #define EIC7700_REG_OFFSET_VI_SHUTTER3 0x1A0
99 #define EIC7700_REG_OFFSET_VI_SHUTTER4 0x1A4
100 #define EIC7700_REG_OFFSET_VI_SHUTTER5 0x1A8
101 #define EIC7700_REG_OFFSET_VI_PHY 0x1AC
102 #define EIC7700_REG_OFFSET_VO_ACLK 0x1B0
103 #define EIC7700_REG_OFFSET_VO_IESMCLK 0x1B4
104 #define EIC7700_REG_OFFSET_VO_PIXEL 0x1B8
105 #define EIC7700_REG_OFFSET_VO_MCLK 0x1BC
106 #define EIC7700_REG_OFFSET_VO_PHY_CLK 0x1C0
107 #define EIC7700_REG_OFFSET_VC_ACLK 0x1C4
108 #define EIC7700_REG_OFFSET_VCDEC_ROOT 0x1C8
109 #define EIC7700_REG_OFFSET_G2D 0x1CC
110 #define EIC7700_REG_OFFSET_VC_CLKEN 0x1D0
111 #define EIC7700_REG_OFFSET_JE 0x1D4
112 #define EIC7700_REG_OFFSET_JD 0x1D8
113 #define EIC7700_REG_OFFSET_VD 0x1DC
114 #define EIC7700_REG_OFFSET_VE 0x1E0
115 #define EIC7700_REG_OFFSET_AON_DMA 0x1E4
116 #define EIC7700_REG_OFFSET_TIMER 0x1E8
117 #define EIC7700_REG_OFFSET_RTC 0x1EC
118 #define EIC7700_REG_OFFSET_PKA 0x1F0
119 #define EIC7700_REG_OFFSET_SPACC 0x1F4
120 #define EIC7700_REG_OFFSET_TRNG 0x1F8
121 #define EIC7700_REG_OFFSET_OTP 0x1FC
122 #define EIC7700_REG_OFFSET_LSP_EN0 0x200
123 #define EIC7700_REG_OFFSET_LSP_EN1 0x204
124 #define EIC7700_REG_OFFSET_U84 0x208
125 #define EIC7700_REG_OFFSET_SYSCFG 0x20C
126 #define EIC7700_REG_OFFSET_I2C0 0x210
127 #define EIC7700_REG_OFFSET_I2C1 0x214
128
129 #define EIC7700_NR_CLKS (EIC7700_CLK_GATE_NOC_WDREF + 1)
130
131 /*
132 * The 24 MHz oscillator, the root of most of the clock tree.
133 */
134 static const struct clk_parent_data xtal24M[] = {
135 { .index = 0, }
136 };
137
138 /* fixed rate clocks */
139 static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = {
140 ESWIN_FIXED(EIC7700_CLK_XTAL_32K, "fixed_rate_clk_xtal_32k", 0, 32768),
141 ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT1, "fixed_rate_clk_spll0_fout1", 0,
142 1600000000),
143 ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT2, "fixed_rate_clk_spll0_fout2", 0,
144 800000000),
145 ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT3, "fixed_rate_clk_spll0_fout3", 0,
146 400000000),
147 ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT1, "fixed_rate_clk_spll1_fout1", 0,
148 1500000000),
149 ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT2, "fixed_rate_clk_spll1_fout2", 0,
150 300000000),
151 ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT3, "fixed_rate_clk_spll1_fout3", 0,
152 250000000),
153 ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT1, "fixed_rate_clk_spll2_fout1", 0,
154 2080000000),
155 ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT2, "fixed_rate_clk_spll2_fout2", 0,
156 1040000000),
157 ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT3, "fixed_rate_clk_spll2_fout3", 0,
158 416000000),
159 ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT1, "fixed_rate_clk_vpll_fout1", 0,
160 1188000000),
161 ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT2, "fixed_rate_clk_vpll_fout2", 0,
162 594000000),
163 ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT3, "fixed_rate_clk_vpll_fout3", 0,
164 49500000),
165 ESWIN_FIXED(EIC7700_CLK_APLL_FOUT2, "fixed_rate_clk_apll_fout2", 0, 0),
166 ESWIN_FIXED(EIC7700_CLK_APLL_FOUT3, "fixed_rate_clk_apll_fout3", 0, 0),
167 ESWIN_FIXED(EIC7700_CLK_EXT_MCLK, "fixed_rate_ext_mclk", 0, 0),
168 ESWIN_FIXED(EIC7700_CLK_LPDDR_REF_BAK, "fixed_rate_lpddr_ref_bak", 0,
169 50000000),
170 };
171
172 /* pll clocks */
173 static struct eswin_pll_clock eic7700_pll_clks[] = {
174 ESWIN_PLL(EIC7700_CLK_APLL_FOUT1, "clk_apll_fout1", xtal24M,
175 EIC7700_REG_OFFSET_APLL_CFG_0, 20,
176 EIC7700_REG_OFFSET_APLL_CFG_1, 4,
177 EIC7700_REG_OFFSET_APLL_CFG_2, EIC7700_REG_OFFSET_PLL_STATUS,
178 4, 1, APLL_HIGH_FREQ, APLL_LOW_FREQ),
179 ESWIN_PLL(EIC7700_CLK_PLL_CPU, "clk_pll_cpu", xtal24M,
180 EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 20,
181 EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4,
182 EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2,
183 EIC7700_REG_OFFSET_PLL_STATUS, 5, 1, PLL_HIGH_FREQ,
184 PLL_LOW_FREQ),
185 };
186
187 /* fixed factor clocks */
188 static struct eswin_fixed_factor_clock eic7700_factor_clks[] = {
189 ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24,
190 "fixed_factor_clk_1m_div24", xtal24M, 1, 24, 0),
191 ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_PVT_DIV20,
192 "fixed_factor_pvt_div20", xtal24M, 1, 20, 0),
193 };
194
195 /* divider clocks */
196 static struct eswin_divider_clock eic7700_div_clks[] = {
197 ESWIN_DIV(EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM,
198 "divider_u84_rtc_toggle_dynm", xtal24M, 0,
199 EIC7700_REG_OFFSET_RTC, 16, 5,
200 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
201 ESWIN_DIV(EIC7700_CLK_DIV_NOC_WDREF_DYNM, "divider_noc_wdref_dynm",
202 xtal24M, 0, EIC7700_REG_OFFSET_NOC, 4, 16,
203 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
204 };
205
206 /* gate clocks */
207 static struct eswin_gate_clock eic7700_gate_clks[] = {
208 ESWIN_GATE(EIC7700_CLK_GATE_GPU_GRAY_CLK, "gate_gpu_gray_clk", xtal24M,
209 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_GRAY, 31, 0),
210 ESWIN_GATE(EIC7700_CLK_GATE_VI_PHY_CFG, "gate_vi_phy_cfg", xtal24M,
211 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 1, 0),
212 ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_0, "gate_time_clk_0", xtal24M,
213 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 0, 0),
214 ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_1, "gate_time_clk_1", xtal24M,
215 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 1, 0),
216 ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_2, "gate_time_clk_2", xtal24M,
217 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 2, 0),
218 ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_3, "gate_time_clk_3", xtal24M,
219 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 3, 0),
220 };
221
222 /* Define the early clocks as the parent clocks of the mux clocks. */
223 static struct eswin_clk_info eic7700_early_clks[] = {
224 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6,
225 "fixed_factor_hsp_rmii_ref_div6",
226 EIC7700_CLK_SPLL1_FOUT2, 1, 6, 0),
227 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM,
228 "divider_npu_llc_src0_div_dynm",
229 EIC7700_CLK_SPLL0_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC,
230 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
231 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM,
232 "divider_npu_llc_src1_div_dynm",
233 EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC,
234 8, 4, 0, ESWIN_PRIV_DIV_MIN_2),
235 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPLL0_FOUT2, "gate_clk_spll0_fout2",
236 EIC7700_CLK_SPLL0_FOUT2,
237 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
238 EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0),
239 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm",
240 EIC7700_CLK_GATE_SPLL0_FOUT2, 0,
241 EIC7700_REG_OFFSET_BOOTSPI, 4, 6, 0,
242 ESWIN_PRIV_DIV_MIN_2),
243 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SCPU_CORE_DYNM,
244 "divider_scpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
245 EIC7700_REG_OFFSET_SCPU_CORE, 4, 4, 0,
246 ESWIN_PRIV_DIV_MIN_2),
247 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_LPCPU_CORE_DYNM,
248 "divider_lpcpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1,
249 0, EIC7700_REG_OFFSET_LPCPU_CORE, 4, 4, 0,
250 ESWIN_PRIV_DIV_MIN_2),
251 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_MCLK_DYNM, "divider_vo_mclk_div_dynm",
252 EIC7700_CLK_APLL_FOUT1, 0, EIC7700_REG_OFFSET_VO_MCLK, 4,
253 8, 0, ESWIN_PRIV_DIV_MIN_2),
254 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AONDMA_AXI_DYNM,
255 "divider_aondma_axi_div_dynm", EIC7700_CLK_SPLL0_FOUT1,
256 0, EIC7700_REG_OFFSET_AON_DMA, 4, 4, 0,
257 ESWIN_PRIV_DIV_MIN_2),
258 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SATA_PHY_REF_DYNM,
259 "divider_sata_phy_ref_div_dynm",
260 EIC7700_CLK_SPLL1_FOUT2, 0, EIC7700_REG_OFFSET_SATA_OOB,
261 0, 4, 0, ESWIN_PRIV_DIV_MIN_2),
262 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm",
263 EIC7700_CLK_SPLL0_FOUT3, 0, EIC7700_REG_OFFSET_SYSCFG, 4,
264 3, 0, ESWIN_PRIV_DIV_MIN_2),
265 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2,
266 "fixed_factor_u84_core_lp_div2",
267 EIC7700_CLK_GATE_SPLL0_FOUT2, 1, 2, 0),
268 };
269
270 static const struct clk_parent_data dsp_aclk_root_2mux1_gfree_mux_p[] = {
271 { .hw = &eic7700_fixed_rate_clks[7].hw },
272 { .hw = &eic7700_fixed_rate_clks[1].hw },
273 };
274
275 static const struct clk_parent_data d2d_aclk_root_2mux1_gfree_mux_p[] = {
276 { .hw = &eic7700_fixed_rate_clks[7].hw },
277 { .hw = &eic7700_fixed_rate_clks[1].hw },
278 };
279
280 static const struct clk_parent_data ddr_aclk_root_2mux1_gfree_mux_p[] = {
281 { .hw = &eic7700_fixed_rate_clks[7].hw },
282 { .hw = &eic7700_fixed_rate_clks[1].hw },
283 };
284
285 static const struct clk_parent_data mshcore_root_3mux1_0_mux_p[] = {
286 { .hw = &eic7700_fixed_rate_clks[3].hw },
287 { .hw = &eic7700_fixed_rate_clks[9].hw },
288 };
289
290 static const struct clk_parent_data mshcore_root_3mux1_1_mux_p[] = {
291 { .hw = &eic7700_fixed_rate_clks[3].hw },
292 { .hw = &eic7700_fixed_rate_clks[9].hw },
293 };
294
295 static const struct clk_parent_data mshcore_root_3mux1_2_mux_p[] = {
296 { .hw = &eic7700_fixed_rate_clks[3].hw },
297 { .hw = &eic7700_fixed_rate_clks[9].hw },
298 };
299
300 static const struct clk_parent_data npu_core_3mux1_gfree_mux_p[] = {
301 { .hw = &eic7700_fixed_rate_clks[4].hw },
302 { .hw = &eic7700_fixed_rate_clks[10].hw },
303 { .hw = &eic7700_fixed_rate_clks[8].hw },
304 };
305
306 static const struct clk_parent_data npu_e31_3mux1_gfree_mux_p[] = {
307 { .hw = &eic7700_fixed_rate_clks[4].hw },
308 { .hw = &eic7700_fixed_rate_clks[10].hw },
309 { .hw = &eic7700_fixed_rate_clks[8].hw },
310 };
311
312 static const struct clk_parent_data vi_aclk_root_2mux1_gfree_mux_p[] = {
313 { .hw = &eic7700_fixed_rate_clks[1].hw },
314 { .hw = &eic7700_fixed_rate_clks[7].hw },
315 };
316
317 static const struct clk_parent_data mux_vi_dw_root_2mux1_p[] = {
318 { .hw = &eic7700_fixed_rate_clks[10].hw },
319 { .hw = &eic7700_fixed_rate_clks[1].hw },
320 };
321
322 static const struct clk_parent_data mux_vi_dvp_root_2mux1_gfree_p[] = {
323 { .hw = &eic7700_fixed_rate_clks[10].hw },
324 { .hw = &eic7700_fixed_rate_clks[1].hw },
325 };
326
327 static const struct clk_parent_data mux_vi_dig_isp_root_2mux1_gfree_p[] = {
328 { .hw = &eic7700_fixed_rate_clks[10].hw },
329 { .hw = &eic7700_fixed_rate_clks[1].hw },
330 };
331
332 static const struct clk_parent_data mux_vo_aclk_root_2mux1_gfree_p[] = {
333 { .hw = &eic7700_fixed_rate_clks[1].hw },
334 { .hw = &eic7700_fixed_rate_clks[7].hw },
335 };
336
337 static const struct clk_parent_data mux_vo_pixel_root_2mux1_p[] = {
338 { .hw = &eic7700_fixed_rate_clks[10].hw },
339 { .hw = &eic7700_fixed_rate_clks[8].hw },
340 };
341
342 static const struct clk_parent_data mux_vcdec_root_2mux1_gfree_p[] = {
343 { .hw = &eic7700_fixed_rate_clks[1].hw },
344 { .hw = &eic7700_fixed_rate_clks[7].hw },
345 };
346
347 static const struct clk_parent_data mux_vcaclk_root_2mux1_gfree_p[] = {
348 { .hw = &eic7700_fixed_rate_clks[1].hw },
349 { .hw = &eic7700_fixed_rate_clks[7].hw },
350 };
351
352 static const struct clk_parent_data npu_llclk_3mux1_gfree_mux_p[] = {
353 { .hw = &eic7700_early_clks[1].hw },
354 { .hw = &eic7700_early_clks[2].hw },
355 { .hw = &eic7700_fixed_rate_clks[10].hw },
356 };
357
358 static const struct clk_parent_data mux_bootspi_clk_2mux1_gfree_p[] = {
359 { .hw = &eic7700_early_clks[4].hw },
360 { .index = 0 },
361 };
362
363 static const struct clk_parent_data mux_scpu_core_clk_2mux1_gfree_p[] = {
364 { .hw = &eic7700_early_clks[5].hw },
365 { .index = 0 },
366 };
367
368 static const struct clk_parent_data mux_lpcpu_core_clk_2mux1_gfree_p[] = {
369 { .hw = &eic7700_early_clks[6].hw },
370 { .index = 0 },
371 };
372
373 static const struct clk_parent_data mux_vo_mclk_2mux_ext_mclk_p[] = {
374 { .hw = &eic7700_early_clks[7].hw },
375 { .hw = &eic7700_fixed_rate_clks[15].hw },
376 };
377
378 static const struct clk_parent_data mux_aondma_axi2mux1_gfree_p[] = {
379 { .hw = &eic7700_early_clks[8].hw },
380 { .index = 0 },
381 };
382
383 static const struct clk_parent_data mux_rmii_ref_2mux1_p[] = {
384 { .hw = &eic7700_early_clks[0].hw },
385 { .hw = &eic7700_fixed_rate_clks[16].hw },
386 };
387
388 static const struct clk_parent_data mux_eth_core_2mux1_p[] = {
389 { .hw = &eic7700_fixed_rate_clks[6].hw },
390 { .hw = &eic7700_fixed_rate_clks[16].hw },
391 };
392
393 static const struct clk_parent_data mux_sata_phy_2mux1_p[] = {
394 { .hw = &eic7700_early_clks[9].hw },
395 { .hw = &eic7700_fixed_rate_clks[16].hw },
396 };
397
398 static const struct clk_parent_data mux_syscfg_clk_root_2mux1_gfree_p[] = {
399 { .hw = &eic7700_early_clks[10].hw },
400 { .index = 0 },
401 };
402
403 static const struct clk_parent_data mux_cpu_root_3mux1_gfree_p[] = {
404 { .hw = &eic7700_pll_clks[1].hw },
405 { .hw = &eic7700_early_clks[11].hw },
406 { .index = 0 },
407 };
408
409 static struct eswin_mux_clock eic7700_mux_clks[] = {
410 ESWIN_MUX(EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
411 "mux_cpu_root_3mux1_gfree", mux_cpu_root_3mux1_gfree_p,
412 ARRAY_SIZE(mux_cpu_root_3mux1_gfree_p),
413 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 0, 2,
414 CLK_MUX_ROUND_CLOSEST),
415 ESWIN_MUX(EIC7700_CLK_MUX_RMII_REF_2MUX, "mux_rmii_ref_2mux1",
416 mux_rmii_ref_2mux1_p, ARRAY_SIZE(mux_rmii_ref_2mux1_p),
417 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 2, 1,
418 CLK_MUX_ROUND_CLOSEST),
419 ESWIN_MUX(EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE,
420 "mux_dsp_aclk_root_2mux1_gfree",
421 dsp_aclk_root_2mux1_gfree_mux_p,
422 ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p),
423 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK, 0, 1,
424 CLK_MUX_ROUND_CLOSEST),
425 ESWIN_MUX(EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE,
426 "mux_d2d_aclk_root_2mux1_gfree",
427 d2d_aclk_root_2mux1_gfree_mux_p,
428 ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p),
429 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK, 0, 1,
430 CLK_MUX_ROUND_CLOSEST),
431 ESWIN_MUX(EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE,
432 "mux_ddr_aclk_root_2mux1_gfree",
433 ddr_aclk_root_2mux1_gfree_mux_p,
434 ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p),
435 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 16, 1,
436 CLK_MUX_ROUND_CLOSEST),
437 ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0,
438 "mux_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p,
439 ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT,
440 EIC7700_REG_OFFSET_MSHC0_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
441 ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1,
442 "mux_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p,
443 ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT,
444 EIC7700_REG_OFFSET_MSHC1_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
445 ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2,
446 "mux_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p,
447 ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT,
448 EIC7700_REG_OFFSET_MSHC2_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
449 ESWIN_MUX(EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE,
450 "mux_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p,
451 ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p),
452 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 0, 2,
453 CLK_MUX_ROUND_CLOSEST),
454 ESWIN_MUX(EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE,
455 "mux_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p,
456 ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT,
457 EIC7700_REG_OFFSET_NPU_CORE, 0, 2, CLK_MUX_ROUND_CLOSEST),
458 ESWIN_MUX(EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE,
459 "mux_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p,
460 ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT,
461 EIC7700_REG_OFFSET_NPU_CORE, 8, 2, CLK_MUX_ROUND_CLOSEST),
462 ESWIN_MUX(EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE,
463 "mux_vi_aclk_root_2mux1_gfree",
464 vi_aclk_root_2mux1_gfree_mux_p,
465 ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p),
466 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 0, 1,
467 CLK_MUX_ROUND_CLOSEST),
468 ESWIN_MUX(EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, "mux_vi_dw_root_2mux1",
469 mux_vi_dw_root_2mux1_p, ARRAY_SIZE(mux_vi_dw_root_2mux1_p),
470 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK, 0, 1,
471 CLK_MUX_ROUND_CLOSEST),
472 ESWIN_MUX(EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE,
473 "mux_vi_dvp_root_2mux1_gfree",
474 mux_vi_dvp_root_2mux1_gfree_p,
475 ARRAY_SIZE(mux_vi_dvp_root_2mux1_gfree_p),
476 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP, 0, 1,
477 CLK_MUX_ROUND_CLOSEST),
478 ESWIN_MUX(EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE,
479 "mux_vi_dig_isp_root_2mux1_gfree",
480 mux_vi_dig_isp_root_2mux1_gfree_p,
481 ARRAY_SIZE(mux_vi_dig_isp_root_2mux1_gfree_p),
482 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP, 0, 1,
483 CLK_MUX_ROUND_CLOSEST),
484 ESWIN_MUX(EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE,
485 "mux_vo_aclk_root_2mux1_gfree",
486 mux_vo_aclk_root_2mux1_gfree_p,
487 ARRAY_SIZE(mux_vo_aclk_root_2mux1_gfree_p),
488 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 0, 1,
489 CLK_MUX_ROUND_CLOSEST),
490 ESWIN_MUX(EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1,
491 "mux_vo_pixel_root_2mux1", mux_vo_pixel_root_2mux1_p,
492 ARRAY_SIZE(mux_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT,
493 EIC7700_REG_OFFSET_VO_PIXEL, 0, 1, CLK_MUX_ROUND_CLOSEST),
494 ESWIN_MUX(EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE,
495 "mux_vcdec_root_2mux1_gfree", mux_vcdec_root_2mux1_gfree_p,
496 ARRAY_SIZE(mux_vcdec_root_2mux1_gfree_p),
497 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOT, 0, 1,
498 CLK_MUX_ROUND_CLOSEST),
499 ESWIN_MUX(EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE,
500 "mux_vcaclk_root_2mux1_gfree",
501 mux_vcaclk_root_2mux1_gfree_p,
502 ARRAY_SIZE(mux_vcaclk_root_2mux1_gfree_p),
503 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK, 0, 1,
504 CLK_MUX_ROUND_CLOSEST),
505 ESWIN_MUX(EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
506 "mux_syscfg_clk_root_2mux1_gfree",
507 mux_syscfg_clk_root_2mux1_gfree_p,
508 ARRAY_SIZE(mux_syscfg_clk_root_2mux1_gfree_p),
509 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG, 0, 1,
510 CLK_MUX_ROUND_CLOSEST),
511 ESWIN_MUX(EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE,
512 "mux_bootspi_clk_2mux1_gfree",
513 mux_bootspi_clk_2mux1_gfree_p,
514 ARRAY_SIZE(mux_bootspi_clk_2mux1_gfree_p),
515 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 0, 1,
516 CLK_MUX_ROUND_CLOSEST),
517 ESWIN_MUX(EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE,
518 "mux_scpu_core_clk_2mux1_gfree",
519 mux_scpu_core_clk_2mux1_gfree_p,
520 ARRAY_SIZE(mux_scpu_core_clk_2mux1_gfree_p),
521 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 0, 1,
522 CLK_MUX_ROUND_CLOSEST),
523 ESWIN_MUX(EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE,
524 "mux_lpcpu_core_clk_2mux1_gfree",
525 mux_lpcpu_core_clk_2mux1_gfree_p,
526 ARRAY_SIZE(mux_lpcpu_core_clk_2mux1_gfree_p),
527 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 0, 1,
528 CLK_MUX_ROUND_CLOSEST),
529 ESWIN_MUX(EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK,
530 "mux_vo_mclk_2mux_ext_mclk", mux_vo_mclk_2mux_ext_mclk_p,
531 ARRAY_SIZE(mux_vo_mclk_2mux_ext_mclk_p),
532 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 0, 1,
533 CLK_MUX_ROUND_CLOSEST),
534 ESWIN_MUX(EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
535 "mux_aondma_axi2mux1_gfree", mux_aondma_axi2mux1_gfree_p,
536 ARRAY_SIZE(mux_aondma_axi2mux1_gfree_p),
537 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 0, 1,
538 CLK_MUX_ROUND_CLOSEST),
539 ESWIN_MUX(EIC7700_CLK_MUX_ETH_CORE_2MUX1, "mux_eth_core_2mux1",
540 mux_eth_core_2mux1_p, ARRAY_SIZE(mux_eth_core_2mux1_p),
541 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 1, 1,
542 CLK_MUX_ROUND_CLOSEST),
543 ESWIN_MUX(EIC7700_CLK_MUX_SATA_PHY_2MUX1, "mux_sata_phy_2mux1",
544 mux_sata_phy_2mux1_p, ARRAY_SIZE(mux_sata_phy_2mux1_p),
545 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 9, 1,
546 CLK_MUX_ROUND_CLOSEST),
547 };
548
549 static const struct clk_parent_data mux_cpu_aclk_2mux1_gfree_p[] = {
550 { .hw = &eic7700_mux_clks[1].hw },
551 { .hw = &eic7700_mux_clks[0].hw },
552 };
553
554 static struct eswin_clk_info eic7700_clks[] = {
555 ESWIN_MUX_TYPE(EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE,
556 "mux_cpu_aclk_2mux1_gfree", mux_cpu_aclk_2mux1_gfree_p,
557 ARRAY_SIZE(mux_cpu_aclk_2mux1_gfree_p),
558 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 20, 1,
559 CLK_MUX_ROUND_CLOSEST, NULL),
560 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_COM_CLK,
561 "gate_clk_cpu_trace_com_clk",
562 EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE,
563 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 23, 0),
564 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_CPU_DIV2,
565 "fixed_factor_cpu_div2",
566 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 1, 2, 0),
567 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
568 "fixed_factor_mipi_txesc_div10",
569 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 10,
570 0),
571 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2,
572 "fixed_factor_scpu_bus_div2",
573 EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0),
574 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2,
575 "fixed_factor_lpcpu_bus_div2",
576 EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0),
577 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2,
578 "fixed_factor_pcie_cr_div2",
579 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 2, 0),
580 ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4,
581 "fixed_factor_pcie_aux_div4",
582 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 4, 0),
583 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_D2D_ACLK_DYNM,
584 "divider_d2d_aclk_div_dynm",
585 EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, 0,
586 EIC7700_REG_OFFSET_D2D_ACLK, 4, 4, 0,
587 ESWIN_PRIV_DIV_MIN_2),
588 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_ACLK_DYNM,
589 "divider_dsp_aclk_div_dynm",
590 EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0,
591 EIC7700_REG_OFFSET_DSP_ACLK, 4, 4, 0,
592 ESWIN_PRIV_DIV_MIN_2),
593 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DDR_ACLK_DYNM,
594 "divider_ddr_aclk_div_dynm",
595 EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, 0,
596 EIC7700_REG_OFFSET_DDR, 20, 4, 0, ESWIN_PRIV_DIV_MIN_2),
597 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0,
598 "divider_eth_txclk_div_dynm_0",
599 EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0,
600 EIC7700_REG_OFFSET_ETH0, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2),
601 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1,
602 "divider_eth_txclk_div_dynm_1",
603 EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0,
604 EIC7700_REG_OFFSET_ETH1, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2),
605 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_0,
606 "divider_mshc_core_div_dynm_0",
607 EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0,
608 0, EIC7700_REG_OFFSET_MSHC0_CORE, 4, 12,
609 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
610 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_1,
611 "divider_mshc_core_div_dynm_1",
612 EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1,
613 0, EIC7700_REG_OFFSET_MSHC1_CORE, 4, 12,
614 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
615 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_2,
616 "divider_mshc_core_div_dynm_2",
617 EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2,
618 0, EIC7700_REG_OFFSET_MSHC2_CORE, 4, 12,
619 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
620 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_CORECLK_DYNM,
621 "divider_npu_coreclk_div_dynm",
622 EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE,
623 0, EIC7700_REG_OFFSET_NPU_CORE, 4, 4,
624 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
625 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_E31_DYNM, "divider_npu_e31_div_dynm",
626 EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, 0,
627 EIC7700_REG_OFFSET_NPU_CORE, 12, 4,
628 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
629 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_ACLK_DYNM, "divider_vi_aclk_div_dynm",
630 EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, 0,
631 EIC7700_REG_OFFSET_VI_ACLK, 4, 4, 0,
632 ESWIN_PRIV_DIV_MIN_2),
633 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DW_DYNM, "divider_vi_dw_div_dynm",
634 EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, 0,
635 EIC7700_REG_OFFSET_VI_DWCLK, 4, 4, 0,
636 ESWIN_PRIV_DIV_MIN_2),
637 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DVP_DYNM, "divider_vi_dvp_div_dynm",
638 EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, 0,
639 EIC7700_REG_OFFSET_VI_DVP, 4, 4, 0,
640 ESWIN_PRIV_DIV_MIN_2),
641 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DIG_ISP_DYNM,
642 "divider_vi_dig_isp_div_dynm",
643 EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, 0,
644 EIC7700_REG_OFFSET_VI_DIG_ISP, 4, 4, 0,
645 ESWIN_PRIV_DIV_MIN_2),
646 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_ACLK_DYNM, "divider_vo_aclk_div_dynm",
647 EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, 0,
648 EIC7700_REG_OFFSET_VO_ACLK, 4, 4, 0,
649 ESWIN_PRIV_DIV_MIN_2),
650 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_PIXEL_DYNM,
651 "divider_vo_pixel_div_dynm",
652 EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, 0,
653 EIC7700_REG_OFFSET_VO_PIXEL, 4, 6, 0,
654 ESWIN_PRIV_DIV_MIN_2),
655 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VC_ACLK_DYNM, "divider_vc_aclk_div_dynm",
656 EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, 0,
657 EIC7700_REG_OFFSET_VC_ACLK, 4, 4, 0,
658 ESWIN_PRIV_DIV_MIN_2),
659 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JD_DYNM, "divider_jd_div_dynm",
660 EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
661 EIC7700_REG_OFFSET_JD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
662 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JE_DYNM, "divider_je_div_dynm",
663 EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
664 EIC7700_REG_OFFSET_JE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
665 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VE_DYNM, "divider_ve_div_dynm",
666 EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
667 EIC7700_REG_OFFSET_VE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
668 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VD_DYNM, "divider_vd_div_dynm",
669 EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
670 EIC7700_REG_OFFSET_VD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
671 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_G2D_DYNM, "divider_g2d_div_dynm",
672 EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0,
673 EIC7700_REG_OFFSET_G2D, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
674 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm",
675 EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NOC, 0, 3,
676 0, ESWIN_PRIV_DIV_MIN_2),
677 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_GPU_ACLK_DYNM,
678 "divider_gpu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
679 EIC7700_REG_OFFSET_GPU_ACLK, 4, 4, 0,
680 ESWIN_PRIV_DIV_MIN_2),
681 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_HSP_ACLK_DYNM,
682 "divider_hsp_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
683 EIC7700_REG_OFFSET_HSP_ACLK, 4, 4, 0,
684 ESWIN_PRIV_DIV_MIN_2),
685 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_PCIE_ACLK_DYNM,
686 "divider_pcie_aclk_div_dynm", EIC7700_CLK_SPLL2_FOUT2, 0,
687 EIC7700_REG_OFFSET_PCIE_ACLK, 4, 4, 0,
688 ESWIN_PRIV_DIV_MIN_2),
689 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_ACLK_DYNM,
690 "divider_npu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
691 EIC7700_REG_OFFSET_NPU_ACLK, 4, 4, 0,
692 ESWIN_PRIV_DIV_MIN_2),
693 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0,
694 "divider_vi_shutter_div_dynm_0",
695 EIC7700_CLK_VPLL_FOUT2, 0,
696 EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, 0,
697 ESWIN_PRIV_DIV_MIN_2),
698 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1,
699 "divider_vi_shutter_div_dynm_1",
700 EIC7700_CLK_VPLL_FOUT2, 0,
701 EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7, 0,
702 ESWIN_PRIV_DIV_MIN_2),
703 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2,
704 "divider_vi_shutter_div_dynm_2",
705 EIC7700_CLK_VPLL_FOUT2, 0,
706 EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, 0,
707 ESWIN_PRIV_DIV_MIN_2),
708 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3,
709 "divider_vi_shutter_div_dynm_3",
710 EIC7700_CLK_VPLL_FOUT2, 0,
711 EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, 0,
712 ESWIN_PRIV_DIV_MIN_2),
713 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4,
714 "divider_vi_shutter_div_dynm_4",
715 EIC7700_CLK_VPLL_FOUT2, 0,
716 EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, 0,
717 ESWIN_PRIV_DIV_MIN_2),
718 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5,
719 "divider_vi_shutter_div_dynm_5",
720 EIC7700_CLK_VPLL_FOUT2, 0,
721 EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, 0,
722 ESWIN_PRIV_DIV_MIN_2),
723 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_IESMCLK_DYNM, "divider_iesmclk_div_dynm",
724 EIC7700_CLK_SPLL0_FOUT3, 0,
725 EIC7700_REG_OFFSET_VO_IESMCLK, 4, 4, 0,
726 ESWIN_PRIV_DIV_MIN_2),
727 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_CEC_DYNM, "divider_vo_cec_div_dynm",
728 EIC7700_CLK_VPLL_FOUT2, 0,
729 EIC7700_REG_OFFSET_VO_PHY_CLK, 16, 16, 0,
730 ESWIN_PRIV_DIV_MIN_2),
731 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_CRYPTO_DYNM, "divider_crypto_div_dynm",
732 EIC7700_CLK_SPLL0_FOUT1, 0,
733 EIC7700_REG_OFFSET_SPACC, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
734 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AON_RTC_DYNM, "divider_aon_rtc_div_dynm",
735 EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, 0,
736 EIC7700_REG_OFFSET_RTC, 21, 11, 0,
737 ESWIN_PRIV_DIV_MIN_2),
738 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_ACLK, "gate_dspt_aclk",
739 EIC7700_CLK_DIV_DSP_ACLK_DYNM, CLK_SET_RATE_PARENT,
740 EIC7700_REG_OFFSET_DSP_ACLK, 31, 0),
741 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_0_ACLK_DYNM,
742 "divider_dsp_0_aclk_div_dynm",
743 EIC7700_CLK_GATE_DSPT_ACLK, 0,
744 EIC7700_REG_OFFSET_DSP_CFG, 19, 1, 0, 0),
745 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_1_ACLK_DYNM,
746 "divider_dsp_1_aclk_div_dynm",
747 EIC7700_CLK_GATE_DSPT_ACLK, 0,
748 EIC7700_REG_OFFSET_DSP_CFG, 20, 1, 0, 0),
749 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_2_ACLK_DYNM,
750 "divider_dsp_2_aclk_div_dynm",
751 EIC7700_CLK_GATE_DSPT_ACLK, 0,
752 EIC7700_REG_OFFSET_DSP_CFG, 21, 1, 0, 0),
753 ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_3_ACLK_DYNM,
754 "divider_dsp_3_aclk_div_dynm",
755 EIC7700_CLK_GATE_DSPT_ACLK, 0,
756 EIC7700_REG_OFFSET_DSP_CFG, 22, 1, 0, 0),
757 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0,
758 "gate_clk_cpu_ext_src_core_clk_0",
759 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
760 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
761 EIC7700_REG_OFFSET_U84, 28, 0),
762 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1,
763 "gate_clk_cpu_ext_src_core_clk_1",
764 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
765 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
766 EIC7700_REG_OFFSET_U84, 29, 0),
767 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2,
768 "gate_clk_cpu_ext_src_core_clk_2",
769 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
770 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
771 EIC7700_REG_OFFSET_U84, 30, 0),
772 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3,
773 "gate_clk_cpu_ext_src_core_clk_3",
774 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
775 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
776 EIC7700_REG_OFFSET_U84, 31, 0),
777 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_0,
778 "gate_clk_cpu_trace_clk_0",
779 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
780 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 24, 0),
781 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_1,
782 "gate_clk_cpu_trace_clk_1",
783 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
784 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 25, 0),
785 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_2,
786 "gate_clk_cpu_trace_clk_2",
787 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
788 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 26, 0),
789 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_3,
790 "gate_clk_cpu_trace_clk_3",
791 EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
792 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 27, 0),
793 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_NSP_CLK, "gate_noc_nsp_clk",
794 EIC7700_CLK_DIV_NOC_NSP_DYNM,
795 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
796 EIC7700_REG_OFFSET_NOC, 31, 0),
797 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI, "gate_clk_bootspi",
798 EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE,
799 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 31, 0),
800 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI_CFG, "gate_clk_bootspi_cfg",
801 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
802 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CFGCLK,
803 31, 0),
804 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_CORE, "gate_clk_scpu_core",
805 EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE,
806 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 31,
807 0),
808 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_BUS, "gate_clk_scpu_bus",
809 EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2,
810 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_BUSCLK, 31,
811 0),
812 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_CORE, "gate_clk_lpcpu_core",
813 EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE,
814 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 31,
815 0),
816 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_BUS, "gate_clk_lpcpu_bus",
817 EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2,
818 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_BUSCLK,
819 31, 0),
820 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_ACLK, "gate_gpu_aclk",
821 EIC7700_CLK_DIV_GPU_ACLK_DYNM, CLK_SET_RATE_PARENT,
822 EIC7700_REG_OFFSET_GPU_ACLK, 31, 0),
823 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_CFG_CLK, "gate_gpu_cfg_clk",
824 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
825 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_CFG, 31, 0),
826 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_CFG_CLK, "gate_dspt_cfg_clk",
827 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
828 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_CFG, 31, 0),
829 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_ACLK, "gate_d2d_aclk",
830 EIC7700_CLK_DIV_D2D_ACLK_DYNM, CLK_SET_RATE_PARENT,
831 EIC7700_REG_OFFSET_D2D_ACLK, 31, 0),
832 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk",
833 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
834 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_CFG, 31, 0),
835 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk",
836 EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
837 EIC7700_REG_OFFSET_TCU_ACLK, 31, 0),
838 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk",
839 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
840 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TCU_CFG, 31, 0),
841 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT_CFG_CLK, "gate_ddrt_cfg_clk",
842 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
843 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 9, 0),
844 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P0_ACLK, "gate_ddrt0_p0_aclk",
845 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
846 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
847 EIC7700_REG_OFFSET_DDR, 4, 0),
848 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P1_ACLK, "gate_ddrt0_p1_aclk",
849 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
850 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
851 EIC7700_REG_OFFSET_DDR, 5, 0),
852 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P2_ACLK, "gate_ddrt0_p2_aclk",
853 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
854 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
855 EIC7700_REG_OFFSET_DDR, 6, 0),
856 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P3_ACLK, "gate_ddrt0_p3_aclk",
857 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
858 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
859 EIC7700_REG_OFFSET_DDR, 7, 0),
860 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P4_ACLK, "gate_ddrt0_p4_aclk",
861 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
862 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
863 EIC7700_REG_OFFSET_DDR, 8, 0),
864 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P0_ACLK, "gate_ddrt1_p0_aclk",
865 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
866 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
867 EIC7700_REG_OFFSET_DDR1, 4, 0),
868 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P1_ACLK, "gate_ddrt1_p1_aclk",
869 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
870 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
871 EIC7700_REG_OFFSET_DDR1, 5, 0),
872 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P2_ACLK, "gate_ddrt1_p2_aclk",
873 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
874 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
875 EIC7700_REG_OFFSET_DDR1, 6, 0),
876 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P3_ACLK, "gate_ddrt1_p3_aclk",
877 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
878 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
879 EIC7700_REG_OFFSET_DDR1, 7, 0),
880 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P4_ACLK, "gate_ddrt1_p4_aclk",
881 EIC7700_CLK_DIV_DDR_ACLK_DYNM,
882 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
883 EIC7700_REG_OFFSET_DDR1, 8, 0),
884 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ACLK, "gate_clk_hsp_aclk",
885 EIC7700_CLK_DIV_HSP_ACLK_DYNM, CLK_SET_RATE_PARENT,
886 EIC7700_REG_OFFSET_HSP_ACLK, 31, 0),
887 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_CFG_CLK, "gate_clk_hsp_cfg_clk",
888 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
889 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_CFG, 31, 0),
890 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_ACLK, "gate_pciet_aclk",
891 EIC7700_CLK_DIV_PCIE_ACLK_DYNM, CLK_SET_RATE_PARENT,
892 EIC7700_REG_OFFSET_PCIE_ACLK, 31, 0),
893 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CFG_CLK, "gate_pciet_cfg_clk",
894 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
895 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 31,
896 0),
897 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CR_CLK, "gate_pciet_cr_clk",
898 EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2,
899 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 0, 0),
900 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_AUX_CLK, "gate_pciet_aux_clk",
901 EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4,
902 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 1, 0),
903 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_ACLK, "gate_npu_aclk",
904 EIC7700_CLK_DIV_NPU_ACLK_DYNM, CLK_SET_RATE_PARENT,
905 EIC7700_REG_OFFSET_NPU_ACLK, 31, 0),
906 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CFG_CLK, "gate_npu_cfg_clk",
907 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
908 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_ACLK, 30,
909 0),
910 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_LLC_ACLK, "gate_npu_llc_aclk",
911 EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE,
912 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 31, 0),
913 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CLK, "gate_npu_clk",
914 EIC7700_CLK_DIV_NPU_CORECLK_DYNM, CLK_SET_RATE_PARENT,
915 EIC7700_REG_OFFSET_NPU_CORE, 31, 0),
916 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_E31_CLK, "gate_npu_e31_clk",
917 EIC7700_CLK_DIV_NPU_E31_DYNM, CLK_SET_RATE_PARENT,
918 EIC7700_REG_OFFSET_NPU_CORE, 30, 0),
919 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_ACLK, "gate_vi_aclk",
920 EIC7700_CLK_DIV_VI_ACLK_DYNM, CLK_SET_RATE_PARENT,
921 EIC7700_REG_OFFSET_VI_ACLK, 31, 0),
922 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_CFG_CLK, "gate_vi_cfg_clk",
923 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
924 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 30, 0),
925 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_DW_CLK, "gate_vi_dig_dw_clk",
926 EIC7700_CLK_DIV_VI_DW_DYNM, CLK_SET_RATE_PARENT,
927 EIC7700_REG_OFFSET_VI_DWCLK, 31, 0),
928 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DVP_CLK, "gate_vi_dvp_clk",
929 EIC7700_CLK_DIV_VI_DVP_DYNM, CLK_SET_RATE_PARENT,
930 EIC7700_REG_OFFSET_VI_DVP, 31, 0),
931 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_ISP_CLK, "gate_vi_dig_isp_clk",
932 EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, CLK_SET_RATE_PARENT,
933 EIC7700_REG_OFFSET_VI_DIG_ISP, 31, 0),
934 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_0, "gate_vi_shutter_0",
935 EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, CLK_SET_RATE_PARENT,
936 EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0),
937 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_1, "gate_vi_shutter_1",
938 EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, CLK_SET_RATE_PARENT,
939 EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0),
940 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_2, "gate_vi_shutter_2",
941 EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, CLK_SET_RATE_PARENT,
942 EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0),
943 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_3, "gate_vi_shutter_3",
944 EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, CLK_SET_RATE_PARENT,
945 EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0),
946 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_4, "gate_vi_shutter_4",
947 EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, CLK_SET_RATE_PARENT,
948 EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0),
949 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_5, "gate_vi_shutter_5",
950 EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, CLK_SET_RATE_PARENT,
951 EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0),
952 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_PHY_TXCLKESC,
953 "gate_vi_phy_txclkesc",
954 EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
955 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 0, 0),
956 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_ACLK, "gate_vo_aclk",
957 EIC7700_CLK_DIV_VO_ACLK_DYNM, CLK_SET_RATE_PARENT,
958 EIC7700_REG_OFFSET_VO_ACLK, 31, 0),
959 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CFG_CLK, "gate_vo_cfg_clk",
960 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
961 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 30, 0),
962 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_HDMI_IESMCLK,
963 "gate_vo_hdmi_iesmclk", EIC7700_CLK_DIV_IESMCLK_DYNM,
964 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_IESMCLK, 31,
965 0),
966 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_PIXEL_CLK, "gate_vo_pixel_clk",
967 EIC7700_CLK_DIV_VO_PIXEL_DYNM, CLK_SET_RATE_PARENT,
968 EIC7700_REG_OFFSET_VO_PIXEL, 31, 0),
969 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_I2S_MCLK, "gate_vo_i2s_mclk",
970 EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK,
971 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 31, 0),
972 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CR_CLK, "gate_vo_cr_clk",
973 EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
974 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_PHY_CLK, 1,
975 0),
976 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_ACLK, "gate_vc_aclk",
977 EIC7700_CLK_DIV_VC_ACLK_DYNM, CLK_SET_RATE_PARENT,
978 EIC7700_REG_OFFSET_VC_ACLK, 31, 0),
979 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_CFG_CLK, "gate_vc_cfg_clk",
980 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
981 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 0, 0),
982 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_CLK, "gate_vc_je_clk",
983 EIC7700_CLK_DIV_JE_DYNM, CLK_SET_RATE_PARENT,
984 EIC7700_REG_OFFSET_JE, 31, 0),
985 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_CLK, "gate_vc_jd_clk",
986 EIC7700_CLK_DIV_JD_DYNM, CLK_SET_RATE_PARENT,
987 EIC7700_REG_OFFSET_JD, 31, 0),
988 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_CLK, "gate_vc_ve_clk",
989 EIC7700_CLK_DIV_VE_DYNM, CLK_SET_RATE_PARENT,
990 EIC7700_REG_OFFSET_VE, 31, 0),
991 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_CLK, "gate_vc_vd_clk",
992 EIC7700_CLK_DIV_VD_DYNM, CLK_SET_RATE_PARENT,
993 EIC7700_REG_OFFSET_VD, 31, 0),
994 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CFG_CLK, "gate_g2d_cfg_clk",
995 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
996 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_G2D, 28, 0),
997 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CLK, "gate_g2d_clk",
998 EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT,
999 EIC7700_REG_OFFSET_G2D, 30, 0),
1000 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_ACLK, "gate_g2d_aclk",
1001 EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT,
1002 EIC7700_REG_OFFSET_G2D, 31, 0),
1003 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_CFG, "gate_clk_aondma_cfg",
1004 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1005 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 30, 0),
1006 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_ACLK, "gate_aondma_aclk",
1007 EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
1008 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 31, 0),
1009 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_ACLK, "gate_aon_aclk",
1010 EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
1011 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 29, 0),
1012 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_0, "gate_timer_pclk_0",
1013 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1014 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 4, 0),
1015 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_1, "gate_timer_pclk_1",
1016 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1017 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 5, 0),
1018 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_2, "gate_timer_pclk_2",
1019 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1020 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 6, 0),
1021 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_3, "gate_timer_pclk_3",
1022 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1023 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 7, 0),
1024 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER3_CLK8, "gate_timer3_clk8",
1025 EIC7700_CLK_VPLL_FOUT3, CLK_SET_RATE_PARENT,
1026 EIC7700_REG_OFFSET_TIMER, 8, 0),
1027 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC_CFG, "gate_clk_rtc_cfg",
1028 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1029 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_RTC, 2, 0),
1030 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC, "gate_clk_rtc",
1031 EIC7700_CLK_DIV_AON_RTC_DYNM, CLK_SET_RATE_PARENT,
1032 EIC7700_REG_OFFSET_RTC, 1, 0),
1033 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_0, "gate_hsp_rmii_ref_0",
1034 EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT,
1035 EIC7700_REG_OFFSET_ETH0, 31, 0),
1036 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_1, "gate_hsp_rmii_ref_1",
1037 EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT,
1038 EIC7700_REG_OFFSET_ETH1, 31, 0),
1039 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PKA_CFG, "gate_clk_pka_cfg",
1040 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1041 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PKA, 31, 0),
1042 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPACC_CFG, "gate_clk_spacc_cfg",
1043 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1044 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SPACC, 31, 0),
1045 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CRYPTO, "gate_clk_crypto",
1046 EIC7700_CLK_DIV_CRYPTO_DYNM, CLK_SET_RATE_PARENT,
1047 EIC7700_REG_OFFSET_SPACC, 30, 0),
1048 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TRNG_CFG, "gate_clk_trng_cfg",
1049 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1050 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TRNG, 31, 0),
1051 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_OTP_CFG, "gate_clk_otp_cfg",
1052 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1053 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_OTP, 31, 0),
1054 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_0, "gate_clk_mailbox_0",
1055 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1056 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 0, 0),
1057 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_1, "gate_clk_mailbox_1",
1058 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1059 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 1, 0),
1060 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_2, "gate_clk_mailbox_2",
1061 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1062 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 2, 0),
1063 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_3, "gate_clk_mailbox_3",
1064 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1065 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 3, 0),
1066 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_4, "gate_clk_mailbox_4",
1067 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1068 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 4, 0),
1069 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_5, "gate_clk_mailbox_5",
1070 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1071 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 5, 0),
1072 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_6, "gate_clk_mailbox_6",
1073 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1074 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 6, 0),
1075 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_7, "gate_clk_mailbox_7",
1076 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1077 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 7, 0),
1078 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_8, "gate_clk_mailbox_8",
1079 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1080 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 8, 0),
1081 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_9, "gate_clk_mailbox_9",
1082 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1083 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 9, 0),
1084 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_10, "gate_clk_mailbox_10",
1085 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1086 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 10, 0),
1087 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_11, "gate_clk_mailbox_11",
1088 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1089 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 11, 0),
1090 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_12, "gate_clk_mailbox_12",
1091 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1092 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 12, 0),
1093 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_13, "gate_clk_mailbox_13",
1094 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1095 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 13, 0),
1096 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_14, "gate_clk_mailbox_14",
1097 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1098 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 14, 0),
1099 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_15, "gate_clk_mailbox_15",
1100 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1101 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 15, 0),
1102 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C0_PCLK, "gate_i2c0_pclk",
1103 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1104 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 7, 0),
1105 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C1_PCLK, "gate_i2c1_pclk",
1106 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1107 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 8, 0),
1108 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C2_PCLK, "gate_i2c2_pclk",
1109 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1110 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 9, 0),
1111 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C3_PCLK, "gate_i2c3_pclk",
1112 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1113 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 10, 0),
1114 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C4_PCLK, "gate_i2c4_pclk",
1115 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1116 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 11, 0),
1117 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C5_PCLK, "gate_i2c5_pclk",
1118 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1119 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 12, 0),
1120 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C6_PCLK, "gate_i2c6_pclk",
1121 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1122 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 13, 0),
1123 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C7_PCLK, "gate_i2c7_pclk",
1124 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1125 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 14, 0),
1126 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C8_PCLK, "gate_i2c8_pclk",
1127 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1128 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 15, 0),
1129 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C9_PCLK, "gate_i2c9_pclk",
1130 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1131 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 16, 0),
1132 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT0_PCLK, "gate_lsp_wdt0_pclk",
1133 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1134 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 28, 0),
1135 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT1_PCLK, "gate_lsp_wdt1_pclk",
1136 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1137 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 29, 0),
1138 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT2_PCLK, "gate_lsp_wdt2_pclk",
1139 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1140 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 30, 0),
1141 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT3_PCLK, "gate_lsp_wdt3_pclk",
1142 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1143 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 31, 0),
1144 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI0_PCLK, "gate_lsp_ssi0_pclk",
1145 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1146 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 26, 0),
1147 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI1_PCLK, "gate_lsp_ssi1_pclk",
1148 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1149 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 27, 0),
1150 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART0_PCLK, "gate_lsp_uart0_pclk",
1151 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1152 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1153 EIC7700_REG_OFFSET_LSP_EN0, 17, 0),
1154 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART1_PCLK, "gate_lsp_uart1_pclk",
1155 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1156 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 18, 0),
1157 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART2_PCLK, "gate_lsp_uart2_pclk",
1158 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1159 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1160 EIC7700_REG_OFFSET_LSP_EN0, 19, 0),
1161 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART3_PCLK, "gate_lsp_uart3_pclk",
1162 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1163 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 20, 0),
1164 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART4_PCLK, "gate_lsp_uart4_pclk",
1165 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1166 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 21, 0),
1167 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_TIMER_PCLK, "gate_lsp_timer_pclk",
1168 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1169 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1170 EIC7700_REG_OFFSET_LSP_EN0, 25, 0),
1171 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_FAN_PCLK, "gate_lsp_fan_pclk",
1172 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1173 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 0, 0),
1174 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT_PCLK, "gate_lsp_pvt_pclk",
1175 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1176 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 1, 0),
1177 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT0_CLK, "gate_pvt0_clk",
1178 EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT,
1179 EIC7700_REG_OFFSET_LSP_EN1, 16, 0),
1180 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT1_CLK, "gate_pvt1_clk",
1181 EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT,
1182 EIC7700_REG_OFFSET_LSP_EN1, 17, 0),
1183 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_PCLK, "gate_vc_je_pclk",
1184 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1185 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 2, 0),
1186 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_PCLK, "gate_vc_jd_pclk",
1187 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1188 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 1, 0),
1189 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_PCLK, "gate_vc_ve_pclk",
1190 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1191 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 5, 0),
1192 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_PCLK, "gate_vc_vd_pclk",
1193 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1194 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 4, 0),
1195 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_MON_PCLK, "gate_vc_mon_pclk",
1196 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1197 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 3, 0),
1198 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK,
1199 "gate_hsp_mshc0_core_clk",
1200 EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, CLK_SET_RATE_PARENT,
1201 EIC7700_REG_OFFSET_MSHC0_CORE, 16, 0),
1202 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK,
1203 "gate_hsp_mshc1_core_clk",
1204 EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, CLK_SET_RATE_PARENT,
1205 EIC7700_REG_OFFSET_MSHC1_CORE, 16, 0),
1206 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK,
1207 "gate_hsp_mshc2_core_clk",
1208 EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, CLK_SET_RATE_PARENT,
1209 EIC7700_REG_OFFSET_MSHC2_CORE, 16, 0),
1210 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_RBC_CLK,
1211 "gate_hsp_sata_rbc_clk", EIC7700_CLK_SPLL1_FOUT2,
1212 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_RBC,
1213 0, 0),
1214 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_OOB_CLK,
1215 "gate_hsp_sata_oob_clk", EIC7700_CLK_MUX_SATA_PHY_2MUX1,
1216 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 31,
1217 0),
1218 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST,
1219 "gate_hsp_dma0_clk_test", EIC7700_CLK_GATE_HSP_ACLK,
1220 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_ACLK, 1, 0),
1221 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK, "gate_hsp_dma0_clk",
1222 EIC7700_CLK_GATE_HSP_ACLK, CLK_SET_RATE_PARENT,
1223 EIC7700_REG_OFFSET_HSP_ACLK, 0, 0),
1224 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK,
1225 "gate_hsp_eth0_core_clk",
1226 EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, CLK_SET_RATE_PARENT,
1227 EIC7700_REG_OFFSET_ETH0, 0, 0),
1228 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK,
1229 "gate_hsp_eth1_core_clk",
1230 EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, CLK_SET_RATE_PARENT,
1231 EIC7700_REG_OFFSET_ETH1, 0, 0),
1232 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C0_PCLK, "gate_aon_i2c0_pclk",
1233 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1234 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C0, 31, 0),
1235 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C1_PCLK, "gate_aon_i2c1_pclk",
1236 EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1237 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C1, 31, 0),
1238 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR0_TRACE, "gate_ddr0_trace",
1239 EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
1240 EIC7700_REG_OFFSET_DDR, 0, 0),
1241 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR1_TRACE, "gate_ddr1_trace",
1242 EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
1243 EIC7700_REG_OFFSET_DDR1, 0, 0),
1244 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RNOC_NSP, "gate_rnoc_nsp",
1245 EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT,
1246 EIC7700_REG_OFFSET_NOC, 29, 0),
1247 ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_WDREF, "gate_noc_wdref",
1248 EIC7700_CLK_DIV_NOC_WDREF_DYNM, CLK_SET_RATE_PARENT,
1249 EIC7700_REG_OFFSET_NOC, 30, 0),
1250 };
1251
1252 /*
1253 * This clock notifier is called when the rate of clk_pll_cpu clock is to be
1254 * changed. The mux_cpu_root_3mux1_gfree clock should save the current parent
1255 * clock and switch its parent clock to fixed_factor_u84_core_lp_div2 before
1256 * clk_pll_cpu rate will be changed. Then switch its parent clock back after
1257 * the clk_pll_cpu rate is completed.
1258 */
eic7700_clk_pll_cpu_notifier_cb(struct notifier_block * nb,unsigned long action,void * data)1259 static int eic7700_clk_pll_cpu_notifier_cb(struct notifier_block *nb,
1260 unsigned long action, void *data)
1261 {
1262 struct eswin_clock_data *pdata;
1263 struct clk_hw *mux_clk;
1264 struct clk_hw *lp_clk;
1265 int ret = 0;
1266
1267 pdata = container_of(nb, struct eswin_clock_data, pll_nb);
1268
1269 mux_clk = &eic7700_mux_clks[0].hw;
1270 lp_clk = &eic7700_early_clks[11].hw;
1271
1272 if (action == PRE_RATE_CHANGE) {
1273 pdata->original_clk = clk_hw_get_parent(mux_clk);
1274 ret = clk_hw_set_parent(mux_clk, lp_clk);
1275 } else if (action == POST_RATE_CHANGE) {
1276 ret = clk_hw_set_parent(mux_clk, pdata->original_clk);
1277 }
1278
1279 return notifier_from_errno(ret);
1280 }
1281
eic7700_clk_probe(struct platform_device * pdev)1282 static int eic7700_clk_probe(struct platform_device *pdev)
1283 {
1284 struct eswin_clock_data *clk_data;
1285 struct device *dev = &pdev->dev;
1286 struct clk *pll_clk;
1287 int ret;
1288
1289 clk_data = eswin_clk_init(pdev, EIC7700_NR_CLKS);
1290 if (IS_ERR(clk_data))
1291 return dev_err_probe(dev, PTR_ERR(clk_data),
1292 "failed to get clk data!\n");
1293
1294 ret = eswin_clk_register_fixed_rate(dev, eic7700_fixed_rate_clks,
1295 ARRAY_SIZE(eic7700_fixed_rate_clks),
1296 clk_data);
1297 if (ret)
1298 return dev_err_probe(dev, ret,
1299 "failed to register fixed rate clock\n");
1300
1301 ret = eswin_clk_register_pll(dev, eic7700_pll_clks,
1302 ARRAY_SIZE(eic7700_pll_clks),
1303 clk_data);
1304 if (ret)
1305 return dev_err_probe(dev, ret,
1306 "failed to register pll clock\n");
1307
1308 pll_clk = devm_clk_hw_get_clk(dev, &eic7700_pll_clks[1].hw,
1309 "clk_pll_cpu");
1310 if (IS_ERR(pll_clk))
1311 return dev_err_probe(dev, PTR_ERR(pll_clk),
1312 "failed to get clk_pll_cpu\n");
1313
1314 clk_data->pll_nb.notifier_call = eic7700_clk_pll_cpu_notifier_cb;
1315 ret = devm_clk_notifier_register(dev, pll_clk, &clk_data->pll_nb);
1316 if (ret)
1317 return ret;
1318
1319 ret = eswin_clk_register_fixed_factor(dev, eic7700_factor_clks,
1320 ARRAY_SIZE(eic7700_factor_clks),
1321 clk_data);
1322 if (ret)
1323 return dev_err_probe(dev, ret,
1324 "failed to register fixed factor clock\n");
1325
1326 ret = eswin_clk_register_divider(dev, eic7700_div_clks,
1327 ARRAY_SIZE(eic7700_div_clks),
1328 clk_data);
1329 if (ret)
1330 return dev_err_probe(dev, ret,
1331 "failed to register divider clock\n");
1332
1333 ret = eswin_clk_register_gate(dev, eic7700_gate_clks,
1334 ARRAY_SIZE(eic7700_gate_clks), clk_data);
1335 if (ret)
1336 return dev_err_probe(dev, ret,
1337 "failed to register gate clock\n");
1338
1339 ret = eswin_clk_register_clks(dev, eic7700_early_clks,
1340 ARRAY_SIZE(eic7700_early_clks), clk_data);
1341 if (ret)
1342 return dev_err_probe(dev, ret, "failed to register clock\n");
1343
1344 ret = eswin_clk_register_mux(dev, eic7700_mux_clks,
1345 ARRAY_SIZE(eic7700_mux_clks), clk_data);
1346 if (ret)
1347 return dev_err_probe(dev, ret,
1348 "failed to register mux clock\n");
1349
1350 ret = eswin_clk_register_clks(dev, eic7700_clks,
1351 ARRAY_SIZE(eic7700_clks), clk_data);
1352 if (ret)
1353 return dev_err_probe(dev, ret, "failed to register clock\n");
1354
1355 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1356 &clk_data->clk_data);
1357 }
1358
1359 static const struct of_device_id eic7700_clock_dt_ids[] = {
1360 { .compatible = "eswin,eic7700-clock", },
1361 { /* sentinel */ }
1362 };
1363 MODULE_DEVICE_TABLE(of, eic7700_clock_dt_ids);
1364
1365 static struct platform_driver eic7700_clock_driver = {
1366 .probe = eic7700_clk_probe,
1367 .driver = {
1368 .name = "eic7700-clock",
1369 .of_match_table = eic7700_clock_dt_ids,
1370 },
1371 };
1372 module_platform_driver(eic7700_clock_driver);
1373
1374 MODULE_LICENSE("GPL");
1375 MODULE_AUTHOR("Yifeng Huang <huangyifeng@eswincomputing.com>");
1376 MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
1377 MODULE_DESCRIPTION("ESWIN EIC7700 clock controller driver");
1378