Searched refs:EFX_MAX_CHANNELS (Results 1 – 10 of 10) sorted by relevance
35 int eventq_dma[EFX_MAX_CHANNELS];36 int eventq_int[EFX_MAX_CHANNELS];
55 #define EFX_MAX_CHANNELS 32U macro56 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS65 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)72 #define EFX_MAX_TX_QUEUES (EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)968 struct efx_channel *channel[EFX_MAX_CHANNELS];969 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
182 unsigned int read_ptr[EFX_MAX_CHANNELS]; in efx_test_eventq_irq()186 BUILD_BUG_ON(EFX_MAX_CHANNELS > BITS_PER_LONG); in efx_test_eventq_irq()
1981 MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS)); in efx_siena_mcdi_flush_rxqs()1984 BUILD_BUG_ON(EFX_MAX_CHANNELS > in efx_siena_mcdi_flush_rxqs()
1295 BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE); in efx_siena_sriov_init()
56 #define EFX_MAX_CHANNELS 32U macro57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS67 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)72 #define EFX_MAX_TX_QUEUES (EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)1049 struct efx_channel *channel[EFX_MAX_CHANNELS];1050 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
73 DECLARE_BITMAP(evq_phases, EFX_MAX_CHANNELS);
181 unsigned int read_ptr[EFX_MAX_CHANNELS]; in efx_test_eventq_irq()185 BUILD_BUG_ON(EFX_MAX_CHANNELS > BITS_PER_LONG); in efx_test_eventq_irq()
617 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, in efx_ef10_probe()