| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-corediv-clock.txt | 1 * Core Divider Clock bindings for Marvell MVEBU SoCs
12 - reg : must be the register address of Core Divider control register
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| H A D | dove-divider-clock.txt | 18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | smu7_fusion.h | 157 uint8_t Divider; member
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| H A D | smu7_discrete.h | 247 uint8_t Divider; member
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| H A D | kv_dpm.c | 758 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
821 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
880 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
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| H A D | ci_dpm.c | 2670 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2703 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2735 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu7_fusion.h | 157 uint8_t Divider; member
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| H A D | smu7_discrete.h | 258 uint8_t Divider; member
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| H A D | smu71_discrete.h | 205 uint8_t Divider; member
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| H A D | smu72_discrete.h | 187 uint8_t Divider; member
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| H A D | smu74_discrete.h | 198 uint8_t Divider; member
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| H A D | smu73_discrete.h | 171 uint8_t Divider; member
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| H A D | smu75_discrete.h | 213 uint8_t Divider; member
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| /linux/drivers/video/fbdev/aty/ |
| H A D | atyfb_base.c | 199 int Multiplier, Divider, Remainder; in ATIReduceRatio() local
202 Divider = *Denominator; in ATIReduceRatio()
204 while ((Remainder = Multiplier % Divider)) { in ATIReduceRatio()
205 Multiplier = Divider; in ATIReduceRatio()
206 Divider = Remainder; in ATIReduceRatio()
209 *Numerator /= Divider; in ATIReduceRatio()
210 *Denominator /= Divider; in ATIReduceRatio()
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| /linux/Documentation/hwmon/ |
| H A D | vt1211.rst | 96 Voltage R1 R2 Divider Raw Value
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | kv_dpm.c | 990 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
1053 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1112 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | fiji_smumgr.c | 1449 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_vce_level()
1485 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_acp_level()
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| H A D | polaris10_smumgr.c | 1407 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_vce_level()
1456 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_samu_level()
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| H A D | ci_smumgr.c | 1583 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_vce_level()
1613 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_acp_level()
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| H A D | tonga_smumgr.c | 1405 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_vce_level()
1449 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_acp_level()
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| H A D | vegam_smumgr.c | 1236 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_vce_level()
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | timekeeping.rst | 231 bit 6-4 = Divider for clock
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