1 /* 2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 3 All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, 9 this list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, 11 this list of conditions and the following disclaimer in the documentation 12 and/or other materials provided with the distribution. 13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works 14 nor the names of its contributors may be used to endorse or promote 15 products derived from this software without specific prior written 16 permission. 17 18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __DRXDRIVER_H__ 32 #define __DRXDRIVER_H__ 33 34 #include <linux/kernel.h> 35 #include <linux/errno.h> 36 #include <linux/i2c.h> 37 38 /* 39 * This structure contains the I2C address, the device ID and a user_data pointer. 40 * The user_data pointer can be used for application specific purposes. 41 */ 42 struct i2c_device_addr { 43 u16 i2c_addr; /* The I2C address of the device. */ 44 u16 i2c_dev_id; /* The device identifier. */ 45 void *user_data; /* User data pointer */ 46 }; 47 48 /* 49 * \def IS_I2C_10BIT( addr ) 50 * \brief Determine if I2C address 'addr' is a 10 bits address or not. 51 * \param addr The I2C address. 52 * \return int. 53 * \retval 0 if address is not a 10 bits I2C address. 54 * \retval 1 if address is a 10 bits I2C address. 55 */ 56 #define IS_I2C_10BIT(addr) \ 57 (((addr) & 0xF8) == 0xF0) 58 59 /*------------------------------------------------------------------------------ 60 Exported FUNCTIONS 61 ------------------------------------------------------------------------------*/ 62 63 /* 64 * \fn drxbsp_i2c_init() 65 * \brief Initialize I2C communication module. 66 * \return int Return status. 67 * \retval 0 Initialization successful. 68 * \retval -EIO Initialization failed. 69 */ 70 int drxbsp_i2c_init(void); 71 72 /* 73 * \fn drxbsp_i2c_term() 74 * \brief Terminate I2C communication module. 75 * \return int Return status. 76 * \retval 0 Termination successful. 77 * \retval -EIO Termination failed. 78 */ 79 int drxbsp_i2c_term(void); 80 81 /* 82 * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, 83 * u16 w_count, 84 * u8 * wData, 85 * struct i2c_device_addr *r_dev_addr, 86 * u16 r_count, 87 * u8 * r_data) 88 * \brief Read and/or write count bytes from I2C bus, store them in data[]. 89 * \param w_dev_addr The device i2c address and the device ID to write to 90 * \param w_count The number of bytes to write 91 * \param wData The array to write the data to 92 * \param r_dev_addr The device i2c address and the device ID to read from 93 * \param r_count The number of bytes to read 94 * \param r_data The array to read the data from 95 * \return int Return status. 96 * \retval 0 Success. 97 * \retval -EIO Failure. 98 * \retval -EINVAL Parameter 'wcount' is not zero but parameter 99 * 'wdata' contains NULL. 100 * Idem for 'rcount' and 'rdata'. 101 * Both w_dev_addr and r_dev_addr are NULL. 102 * 103 * This function must implement an atomic write and/or read action on the I2C bus 104 * No other process may use the I2C bus when this function is executing. 105 * The critical section of this function runs from and including the I2C 106 * write, up to and including the I2C read action. 107 * 108 * The device ID can be useful if several devices share an I2C address. 109 * It can be used to control a "switch" on the I2C bus to the correct device. 110 */ 111 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, 112 u16 w_count, 113 u8 *wData, 114 struct i2c_device_addr *r_dev_addr, 115 u16 r_count, u8 *r_data); 116 117 /* 118 * \fn drxbsp_i2c_error_text() 119 * \brief Returns a human readable error. 120 * Counter part of numerical drx_i2c_error_g. 121 * 122 * \return char* Pointer to human readable error text. 123 */ 124 char *drxbsp_i2c_error_text(void); 125 126 /* 127 * \var drx_i2c_error_g; 128 * \brief I2C specific error codes, platform dependent. 129 */ 130 extern int drx_i2c_error_g; 131 132 #define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ 133 #define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ 134 #define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ 135 #define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ 136 #define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ 137 #define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ 138 #define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ 139 #define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ 140 141 #define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ 142 #define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ 143 #define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ 144 #define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ 145 #define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ 146 #define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ 147 #define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ 148 149 #define TUNER_MODE_SUB_MAX 8 150 #define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ 151 TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ 152 TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ 153 TUNER_MODE_SUB6 | TUNER_MODE_SUB7) 154 155 156 enum tuner_lock_status { 157 TUNER_LOCKED, 158 TUNER_NOT_LOCKED 159 }; 160 161 struct tuner_common { 162 char *name; /* Tuner brand & type name */ 163 s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ 164 s32 max_freq_rf; /* Highest RF input frequency, in kHz */ 165 166 u8 sub_mode; /* Index to sub-mode in use */ 167 char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ 168 u8 sub_modes; /* Number of available sub-modes */ 169 170 /* The following fields will be either 0, NULL or false and do not need 171 initialisation */ 172 void *self_check; /* gives proof of initialization */ 173 bool programmed; /* only valid if self_check is OK */ 174 s32 r_ffrequency; /* only valid if programmed */ 175 s32 i_ffrequency; /* only valid if programmed */ 176 177 void *my_user_data; /* pointer to associated demod instance */ 178 u16 my_capabilities; /* value for storing application flags */ 179 }; 180 181 struct tuner_instance; 182 183 typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); 184 typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); 185 186 typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, 187 u32 mode, 188 s32 189 frequency); 190 191 typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, 192 u32 mode, 193 s32 * 194 r_ffrequency, 195 s32 * 196 i_ffrequency); 197 198 typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, 199 enum tuner_lock_status * 200 lock_stat); 201 202 typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, 203 struct i2c_device_addr * 204 w_dev_addr, u16 w_count, 205 u8 *wData, 206 struct i2c_device_addr * 207 r_dev_addr, u16 r_count, 208 u8 *r_data); 209 210 struct tuner_ops { 211 tuner_open_func_t open_func; 212 tuner_close_func_t close_func; 213 tuner_set_frequency_func_t set_frequency_func; 214 tuner_get_frequency_func_t get_frequency_func; 215 tuner_lock_status_func_t lock_status_func; 216 tune_ri2c_write_read_func_t i2c_write_read_func; 217 218 }; 219 220 struct tuner_instance { 221 struct i2c_device_addr my_i2c_dev_addr; 222 struct tuner_common *my_common_attr; 223 void *my_ext_attr; 224 struct tuner_ops *my_funct; 225 }; 226 227 int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, 228 u32 mode, 229 s32 frequency); 230 231 int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, 232 u32 mode, 233 s32 *r_ffrequency, 234 s32 *i_ffrequency); 235 236 int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, 237 struct i2c_device_addr *w_dev_addr, 238 u16 w_count, 239 u8 *wData, 240 struct i2c_device_addr *r_dev_addr, 241 u16 r_count, u8 *r_data); 242 243 /************* 244 * 245 * This section configures the DRX Data Access Protocols (DAPs). 246 * 247 **************/ 248 249 /* 250 * \def DRXDAP_SINGLE_MASTER 251 * \brief Enable I2C single or I2C multimaster mode on host. 252 * 253 * Set to 1 to enable single master mode 254 * Set to 0 to enable multi master mode 255 * 256 * The actual DAP implementation may be restricted to only one of the modes. 257 * A compiler warning or error will be generated if the DAP implementation 258 * overrides or cannot handle the mode defined below. 259 */ 260 #ifndef DRXDAP_SINGLE_MASTER 261 #define DRXDAP_SINGLE_MASTER 1 262 #endif 263 264 /* 265 * \def DRXDAP_MAX_WCHUNKSIZE 266 * \brief Defines maximum chunksize of an i2c write action by host. 267 * 268 * This indicates the maximum size of data the I2C device driver is able to 269 * write at a time. This includes I2C device address and register addressing. 270 * 271 * This maximum size may be restricted by the actual DAP implementation. 272 * A compiler warning or error will be generated if the DAP implementation 273 * overrides or cannot handle the chunksize defined below. 274 * 275 * Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data 276 * buffer. Do not undefine or choose too large, unless your system is able to 277 * handle a stack buffer of that size. 278 * 279 */ 280 #ifndef DRXDAP_MAX_WCHUNKSIZE 281 #define DRXDAP_MAX_WCHUNKSIZE 60 282 #endif 283 284 /* 285 * \def DRXDAP_MAX_RCHUNKSIZE 286 * \brief Defines maximum chunksize of an i2c read action by host. 287 * 288 * This indicates the maximum size of data the I2C device driver is able to read 289 * at a time. Minimum value is 2. Also, the read chunk size must be even. 290 * 291 * This maximum size may be restricted by the actual DAP implementation. 292 * A compiler warning or error will be generated if the DAP implementation 293 * overrides or cannot handle the chunksize defined below. 294 */ 295 #ifndef DRXDAP_MAX_RCHUNKSIZE 296 #define DRXDAP_MAX_RCHUNKSIZE 60 297 #endif 298 299 /************* 300 * 301 * This section describes drxdriver defines. 302 * 303 **************/ 304 305 /* 306 * \def DRX_UNKNOWN 307 * \brief Generic UNKNOWN value for DRX enumerated types. 308 * 309 * Used to indicate that the parameter value is unknown or not yet initialized. 310 */ 311 #ifndef DRX_UNKNOWN 312 #define DRX_UNKNOWN (254) 313 #endif 314 315 /* 316 * \def DRX_AUTO 317 * \brief Generic AUTO value for DRX enumerated types. 318 * 319 * Used to instruct the driver to automatically determine the value of the 320 * parameter. 321 */ 322 #ifndef DRX_AUTO 323 #define DRX_AUTO (255) 324 #endif 325 326 /************* 327 * 328 * This section describes flag definitions for the device capbilities. 329 * 330 **************/ 331 332 /* 333 * \brief LNA capability flag 334 * 335 * Device has a Low Noise Amplifier 336 * 337 */ 338 #define DRX_CAPABILITY_HAS_LNA (1UL << 0) 339 /* 340 * \brief OOB-RX capability flag 341 * 342 * Device has OOB-RX 343 * 344 */ 345 #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) 346 /* 347 * \brief ATV capability flag 348 * 349 * Device has ATV 350 * 351 */ 352 #define DRX_CAPABILITY_HAS_ATV (1UL << 2) 353 /* 354 * \brief DVB-T capability flag 355 * 356 * Device has DVB-T 357 * 358 */ 359 #define DRX_CAPABILITY_HAS_DVBT (1UL << 3) 360 /* 361 * \brief ITU-B capability flag 362 * 363 * Device has ITU-B 364 * 365 */ 366 #define DRX_CAPABILITY_HAS_ITUB (1UL << 4) 367 /* 368 * \brief Audio capability flag 369 * 370 * Device has Audio 371 * 372 */ 373 #define DRX_CAPABILITY_HAS_AUD (1UL << 5) 374 /* 375 * \brief SAW switch capability flag 376 * 377 * Device has SAW switch 378 * 379 */ 380 #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) 381 /* 382 * \brief GPIO1 capability flag 383 * 384 * Device has GPIO1 385 * 386 */ 387 #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) 388 /* 389 * \brief GPIO2 capability flag 390 * 391 * Device has GPIO2 392 * 393 */ 394 #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) 395 /* 396 * \brief IRQN capability flag 397 * 398 * Device has IRQN 399 * 400 */ 401 #define DRX_CAPABILITY_HAS_IRQN (1UL << 9) 402 /* 403 * \brief 8VSB capability flag 404 * 405 * Device has 8VSB 406 * 407 */ 408 #define DRX_CAPABILITY_HAS_8VSB (1UL << 10) 409 /* 410 * \brief SMA-TX capability flag 411 * 412 * Device has SMATX 413 * 414 */ 415 #define DRX_CAPABILITY_HAS_SMATX (1UL << 11) 416 /* 417 * \brief SMA-RX capability flag 418 * 419 * Device has SMARX 420 * 421 */ 422 #define DRX_CAPABILITY_HAS_SMARX (1UL << 12) 423 /* 424 * \brief ITU-A/C capability flag 425 * 426 * Device has ITU-A/C 427 * 428 */ 429 #define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) 430 431 /*------------------------------------------------------------------------- 432 MACROS 433 -------------------------------------------------------------------------*/ 434 /* Macros to stringify the version number */ 435 #define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ 436 DRX_VERSIONSTRING_HELP(MAJOR)"." \ 437 DRX_VERSIONSTRING_HELP(MINOR)"." \ 438 DRX_VERSIONSTRING_HELP(PATCH) 439 #define DRX_VERSIONSTRING_HELP(NUM) #NUM 440 441 /* 442 * \brief Macro to create byte array elements from 16 bit integers. 443 * This macro is used to create byte arrays for block writes. 444 * Block writes speed up I2C traffic between host and demod. 445 * The macro takes care of the required byte order in a 16 bits word. 446 * x->lowbyte(x), highbyte(x) 447 */ 448 #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ 449 ((u8)((((u16)x)>>8)&0xFF)) 450 451 /* 452 * \brief Macro to convert 16 bit register value to a s32 453 */ 454 #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ 455 ((s32) \ 456 (((u32) x) | 0xFFFF0000)) : \ 457 ((s32) x)) 458 459 /*------------------------------------------------------------------------- 460 ENUM 461 -------------------------------------------------------------------------*/ 462 463 /* 464 * \enum enum drx_standard 465 * \brief Modulation standards. 466 */ 467 enum drx_standard { 468 DRX_STANDARD_DVBT = 0, /*< Terrestrial DVB-T. */ 469 DRX_STANDARD_8VSB, /*< Terrestrial 8VSB. */ 470 DRX_STANDARD_NTSC, /*< Terrestrial\Cable analog NTSC. */ 471 DRX_STANDARD_PAL_SECAM_BG, 472 /*< Terrestrial analog PAL/SECAM B/G */ 473 DRX_STANDARD_PAL_SECAM_DK, 474 /*< Terrestrial analog PAL/SECAM D/K */ 475 DRX_STANDARD_PAL_SECAM_I, 476 /*< Terrestrial analog PAL/SECAM I */ 477 DRX_STANDARD_PAL_SECAM_L, 478 /*< Terrestrial analog PAL/SECAM L 479 with negative modulation */ 480 DRX_STANDARD_PAL_SECAM_LP, 481 /*< Terrestrial analog PAL/SECAM L 482 with positive modulation */ 483 DRX_STANDARD_ITU_A, /*< Cable ITU ANNEX A. */ 484 DRX_STANDARD_ITU_B, /*< Cable ITU ANNEX B. */ 485 DRX_STANDARD_ITU_C, /*< Cable ITU ANNEX C. */ 486 DRX_STANDARD_ITU_D, /*< Cable ITU ANNEX D. */ 487 DRX_STANDARD_FM, /*< Terrestrial\Cable FM radio */ 488 DRX_STANDARD_DTMB, /*< Terrestrial DTMB standard (China)*/ 489 DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, 490 /*< Standard unknown. */ 491 DRX_STANDARD_AUTO = DRX_AUTO 492 /*< Autodetect standard. */ 493 }; 494 495 /* 496 * \enum enum drx_standard 497 * \brief Modulation sub-standards. 498 */ 499 enum drx_substandard { 500 DRX_SUBSTANDARD_MAIN = 0, /*< Main subvariant of standard */ 501 DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, 502 DRX_SUBSTANDARD_ATV_DK_POLAND, 503 DRX_SUBSTANDARD_ATV_DK_CHINA, 504 DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, 505 /*< Sub-standard unknown. */ 506 DRX_SUBSTANDARD_AUTO = DRX_AUTO 507 /*< Auto (default) sub-standard */ 508 }; 509 510 /* 511 * \enum enum drx_bandwidth 512 * \brief Channel bandwidth or channel spacing. 513 */ 514 enum drx_bandwidth { 515 DRX_BANDWIDTH_8MHZ = 0, /*< Bandwidth 8 MHz. */ 516 DRX_BANDWIDTH_7MHZ, /*< Bandwidth 7 MHz. */ 517 DRX_BANDWIDTH_6MHZ, /*< Bandwidth 6 MHz. */ 518 DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, 519 /*< Bandwidth unknown. */ 520 DRX_BANDWIDTH_AUTO = DRX_AUTO 521 /*< Auto Set Bandwidth */ 522 }; 523 524 /* 525 * \enum enum drx_mirror 526 * \brief Indicate if channel spectrum is mirrored or not. 527 */ 528 enum drx_mirror { 529 DRX_MIRROR_NO = 0, /*< Spectrum is not mirrored. */ 530 DRX_MIRROR_YES, /*< Spectrum is mirrored. */ 531 DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, 532 /*< Unknown if spectrum is mirrored. */ 533 DRX_MIRROR_AUTO = DRX_AUTO 534 /*< Autodetect if spectrum is mirrored. */ 535 }; 536 537 /* 538 * \enum enum drx_modulation 539 * \brief Constellation type of the channel. 540 */ 541 enum drx_modulation { 542 DRX_CONSTELLATION_BPSK = 0, /*< Modulation is BPSK. */ 543 DRX_CONSTELLATION_QPSK, /*< Constellation is QPSK. */ 544 DRX_CONSTELLATION_PSK8, /*< Constellation is PSK8. */ 545 DRX_CONSTELLATION_QAM16, /*< Constellation is QAM16. */ 546 DRX_CONSTELLATION_QAM32, /*< Constellation is QAM32. */ 547 DRX_CONSTELLATION_QAM64, /*< Constellation is QAM64. */ 548 DRX_CONSTELLATION_QAM128, /*< Constellation is QAM128. */ 549 DRX_CONSTELLATION_QAM256, /*< Constellation is QAM256. */ 550 DRX_CONSTELLATION_QAM512, /*< Constellation is QAM512. */ 551 DRX_CONSTELLATION_QAM1024, /*< Constellation is QAM1024. */ 552 DRX_CONSTELLATION_QPSK_NR, /*< Constellation is QPSK_NR */ 553 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, 554 /*< Constellation unknown. */ 555 DRX_CONSTELLATION_AUTO = DRX_AUTO 556 /*< Autodetect constellation. */ 557 }; 558 559 /* 560 * \enum enum drx_hierarchy 561 * \brief Hierarchy of the channel. 562 */ 563 enum drx_hierarchy { 564 DRX_HIERARCHY_NONE = 0, /*< None hierarchical channel. */ 565 DRX_HIERARCHY_ALPHA1, /*< Hierarchical channel, alpha=1. */ 566 DRX_HIERARCHY_ALPHA2, /*< Hierarchical channel, alpha=2. */ 567 DRX_HIERARCHY_ALPHA4, /*< Hierarchical channel, alpha=4. */ 568 DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, 569 /*< Hierarchy unknown. */ 570 DRX_HIERARCHY_AUTO = DRX_AUTO 571 /*< Autodetect hierarchy. */ 572 }; 573 574 /* 575 * \enum enum drx_priority 576 * \brief Channel priority in case of hierarchical transmission. 577 */ 578 enum drx_priority { 579 DRX_PRIORITY_LOW = 0, /*< Low priority channel. */ 580 DRX_PRIORITY_HIGH, /*< High priority channel. */ 581 DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN 582 /*< Priority unknown. */ 583 }; 584 585 /* 586 * \enum enum drx_coderate 587 * \brief Channel priority in case of hierarchical transmission. 588 */ 589 enum drx_coderate { 590 DRX_CODERATE_1DIV2 = 0, /*< Code rate 1/2nd. */ 591 DRX_CODERATE_2DIV3, /*< Code rate 2/3nd. */ 592 DRX_CODERATE_3DIV4, /*< Code rate 3/4nd. */ 593 DRX_CODERATE_5DIV6, /*< Code rate 5/6nd. */ 594 DRX_CODERATE_7DIV8, /*< Code rate 7/8nd. */ 595 DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, 596 /*< Code rate unknown. */ 597 DRX_CODERATE_AUTO = DRX_AUTO 598 /*< Autodetect code rate. */ 599 }; 600 601 /* 602 * \enum enum drx_guard 603 * \brief Guard interval of a channel. 604 */ 605 enum drx_guard { 606 DRX_GUARD_1DIV32 = 0, /*< Guard interval 1/32nd. */ 607 DRX_GUARD_1DIV16, /*< Guard interval 1/16th. */ 608 DRX_GUARD_1DIV8, /*< Guard interval 1/8th. */ 609 DRX_GUARD_1DIV4, /*< Guard interval 1/4th. */ 610 DRX_GUARD_UNKNOWN = DRX_UNKNOWN, 611 /*< Guard interval unknown. */ 612 DRX_GUARD_AUTO = DRX_AUTO 613 /*< Autodetect guard interval. */ 614 }; 615 616 /* 617 * \enum enum drx_fft_mode 618 * \brief FFT mode. 619 */ 620 enum drx_fft_mode { 621 DRX_FFTMODE_2K = 0, /*< 2K FFT mode. */ 622 DRX_FFTMODE_4K, /*< 4K FFT mode. */ 623 DRX_FFTMODE_8K, /*< 8K FFT mode. */ 624 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, 625 /*< FFT mode unknown. */ 626 DRX_FFTMODE_AUTO = DRX_AUTO 627 /*< Autodetect FFT mode. */ 628 }; 629 630 /* 631 * \enum enum drx_classification 632 * \brief Channel classification. 633 */ 634 enum drx_classification { 635 DRX_CLASSIFICATION_GAUSS = 0, /*< Gaussion noise. */ 636 DRX_CLASSIFICATION_HVY_GAUSS, /*< Heavy Gaussion noise. */ 637 DRX_CLASSIFICATION_COCHANNEL, /*< Co-channel. */ 638 DRX_CLASSIFICATION_STATIC, /*< Static echo. */ 639 DRX_CLASSIFICATION_MOVING, /*< Moving echo. */ 640 DRX_CLASSIFICATION_ZERODB, /*< Zero dB echo. */ 641 DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, 642 /*< Unknown classification */ 643 DRX_CLASSIFICATION_AUTO = DRX_AUTO 644 /*< Autodetect classification. */ 645 }; 646 647 /* 648 * /enum enum drx_interleave_mode 649 * /brief Interleave modes 650 */ 651 enum drx_interleave_mode { 652 DRX_INTERLEAVEMODE_I128_J1 = 0, 653 DRX_INTERLEAVEMODE_I128_J1_V2, 654 DRX_INTERLEAVEMODE_I128_J2, 655 DRX_INTERLEAVEMODE_I64_J2, 656 DRX_INTERLEAVEMODE_I128_J3, 657 DRX_INTERLEAVEMODE_I32_J4, 658 DRX_INTERLEAVEMODE_I128_J4, 659 DRX_INTERLEAVEMODE_I16_J8, 660 DRX_INTERLEAVEMODE_I128_J5, 661 DRX_INTERLEAVEMODE_I8_J16, 662 DRX_INTERLEAVEMODE_I128_J6, 663 DRX_INTERLEAVEMODE_RESERVED_11, 664 DRX_INTERLEAVEMODE_I128_J7, 665 DRX_INTERLEAVEMODE_RESERVED_13, 666 DRX_INTERLEAVEMODE_I128_J8, 667 DRX_INTERLEAVEMODE_RESERVED_15, 668 DRX_INTERLEAVEMODE_I12_J17, 669 DRX_INTERLEAVEMODE_I5_J4, 670 DRX_INTERLEAVEMODE_B52_M240, 671 DRX_INTERLEAVEMODE_B52_M720, 672 DRX_INTERLEAVEMODE_B52_M48, 673 DRX_INTERLEAVEMODE_B52_M0, 674 DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, 675 /*< Unknown interleave mode */ 676 DRX_INTERLEAVEMODE_AUTO = DRX_AUTO 677 /*< Autodetect interleave mode */ 678 }; 679 680 /* 681 * \enum enum drx_carrier_mode 682 * \brief Channel Carrier Mode. 683 */ 684 enum drx_carrier_mode { 685 DRX_CARRIER_MULTI = 0, /*< Multi carrier mode */ 686 DRX_CARRIER_SINGLE, /*< Single carrier mode */ 687 DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, 688 /*< Carrier mode unknown. */ 689 DRX_CARRIER_AUTO = DRX_AUTO /*< Autodetect carrier mode */ 690 }; 691 692 /* 693 * \enum enum drx_frame_mode 694 * \brief Channel Frame Mode. 695 */ 696 enum drx_frame_mode { 697 DRX_FRAMEMODE_420 = 0, /*< 420 with variable PN */ 698 DRX_FRAMEMODE_595, /*< 595 */ 699 DRX_FRAMEMODE_945, /*< 945 with variable PN */ 700 DRX_FRAMEMODE_420_FIXED_PN, 701 /*< 420 with fixed PN */ 702 DRX_FRAMEMODE_945_FIXED_PN, 703 /*< 945 with fixed PN */ 704 DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, 705 /*< Frame mode unknown. */ 706 DRX_FRAMEMODE_AUTO = DRX_AUTO 707 /*< Autodetect frame mode */ 708 }; 709 710 /* 711 * \enum enum drx_tps_frame 712 * \brief Frame number in current super-frame. 713 */ 714 enum drx_tps_frame { 715 DRX_TPS_FRAME1 = 0, /*< TPS frame 1. */ 716 DRX_TPS_FRAME2, /*< TPS frame 2. */ 717 DRX_TPS_FRAME3, /*< TPS frame 3. */ 718 DRX_TPS_FRAME4, /*< TPS frame 4. */ 719 DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN 720 /*< TPS frame unknown. */ 721 }; 722 723 /* 724 * \enum enum drx_ldpc 725 * \brief TPS LDPC . 726 */ 727 enum drx_ldpc { 728 DRX_LDPC_0_4 = 0, /*< LDPC 0.4 */ 729 DRX_LDPC_0_6, /*< LDPC 0.6 */ 730 DRX_LDPC_0_8, /*< LDPC 0.8 */ 731 DRX_LDPC_UNKNOWN = DRX_UNKNOWN, 732 /*< LDPC unknown. */ 733 DRX_LDPC_AUTO = DRX_AUTO /*< Autodetect LDPC */ 734 }; 735 736 /* 737 * \enum enum drx_pilot_mode 738 * \brief Pilot modes in DTMB. 739 */ 740 enum drx_pilot_mode { 741 DRX_PILOT_ON = 0, /*< Pilot On */ 742 DRX_PILOT_OFF, /*< Pilot Off */ 743 DRX_PILOT_UNKNOWN = DRX_UNKNOWN, 744 /*< Pilot unknown. */ 745 DRX_PILOT_AUTO = DRX_AUTO /*< Autodetect Pilot */ 746 }; 747 748 /* 749 * enum drxu_code_action - indicate if firmware has to be uploaded or verified. 750 * @UCODE_UPLOAD: Upload the microcode image to device 751 * @UCODE_VERIFY: Compare microcode image with code on device 752 */ 753 enum drxu_code_action { 754 UCODE_UPLOAD, 755 UCODE_VERIFY 756 }; 757 758 /* 759 * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. 760 * 761 * The generic lock states have device dependent semantics. 762 763 DRX_NEVER_LOCK = 0, 764 **< Device will never lock on this signal * 765 DRX_NOT_LOCKED, 766 **< Device has no lock at all * 767 DRX_LOCK_STATE_1, 768 **< Generic lock state * 769 DRX_LOCK_STATE_2, 770 **< Generic lock state * 771 DRX_LOCK_STATE_3, 772 **< Generic lock state * 773 DRX_LOCK_STATE_4, 774 **< Generic lock state * 775 DRX_LOCK_STATE_5, 776 **< Generic lock state * 777 DRX_LOCK_STATE_6, 778 **< Generic lock state * 779 DRX_LOCK_STATE_7, 780 **< Generic lock state * 781 DRX_LOCK_STATE_8, 782 **< Generic lock state * 783 DRX_LOCK_STATE_9, 784 **< Generic lock state * 785 DRX_LOCKED **< Device is in lock * 786 */ 787 788 enum drx_lock_status { 789 DRX_NEVER_LOCK = 0, 790 DRX_NOT_LOCKED, 791 DRX_LOCK_STATE_1, 792 DRX_LOCK_STATE_2, 793 DRX_LOCK_STATE_3, 794 DRX_LOCK_STATE_4, 795 DRX_LOCK_STATE_5, 796 DRX_LOCK_STATE_6, 797 DRX_LOCK_STATE_7, 798 DRX_LOCK_STATE_8, 799 DRX_LOCK_STATE_9, 800 DRX_LOCKED 801 }; 802 803 /* 804 * \enum enum drx_uio* \brief Used to address a User IO (UIO). 805 */ 806 enum drx_uio { 807 DRX_UIO1, 808 DRX_UIO2, 809 DRX_UIO3, 810 DRX_UIO4, 811 DRX_UIO5, 812 DRX_UIO6, 813 DRX_UIO7, 814 DRX_UIO8, 815 DRX_UIO9, 816 DRX_UIO10, 817 DRX_UIO11, 818 DRX_UIO12, 819 DRX_UIO13, 820 DRX_UIO14, 821 DRX_UIO15, 822 DRX_UIO16, 823 DRX_UIO17, 824 DRX_UIO18, 825 DRX_UIO19, 826 DRX_UIO20, 827 DRX_UIO21, 828 DRX_UIO22, 829 DRX_UIO23, 830 DRX_UIO24, 831 DRX_UIO25, 832 DRX_UIO26, 833 DRX_UIO27, 834 DRX_UIO28, 835 DRX_UIO29, 836 DRX_UIO30, 837 DRX_UIO31, 838 DRX_UIO32, 839 DRX_UIO_MAX = DRX_UIO32 840 }; 841 842 /* 843 * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. 844 * 845 * DRX_UIO_MODE_FIRMWARE is an old uio mode. 846 * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. 847 * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to 848 * DRX_UIO_MODE_FIRMWARE0. 849 */ 850 enum drxuio_mode { 851 DRX_UIO_MODE_DISABLE = 0x01, 852 /*< not used, pin is configured as input */ 853 DRX_UIO_MODE_READWRITE = 0x02, 854 /*< used for read/write by application */ 855 DRX_UIO_MODE_FIRMWARE = 0x04, 856 /*< controlled by firmware, function 0 */ 857 DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, 858 /*< same as above */ 859 DRX_UIO_MODE_FIRMWARE1 = 0x08, 860 /*< controlled by firmware, function 1 */ 861 DRX_UIO_MODE_FIRMWARE2 = 0x10, 862 /*< controlled by firmware, function 2 */ 863 DRX_UIO_MODE_FIRMWARE3 = 0x20, 864 /*< controlled by firmware, function 3 */ 865 DRX_UIO_MODE_FIRMWARE4 = 0x40, 866 /*< controlled by firmware, function 4 */ 867 DRX_UIO_MODE_FIRMWARE5 = 0x80 868 /*< controlled by firmware, function 5 */ 869 }; 870 871 /* 872 * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. 873 * 874 * Based on ANSI 55-1 and 55-2 875 */ 876 enum drxoob_downstream_standard { 877 DRX_OOB_MODE_A = 0, 878 /*< ANSI 55-1 */ 879 DRX_OOB_MODE_B_GRADE_A, 880 /*< ANSI 55-2 A */ 881 DRX_OOB_MODE_B_GRADE_B 882 /*< ANSI 55-2 B */ 883 }; 884 885 /*------------------------------------------------------------------------- 886 STRUCTS 887 -------------------------------------------------------------------------*/ 888 889 /*============================================================================*/ 890 /*============================================================================*/ 891 /*== CTRL CFG related data structures ========================================*/ 892 /*============================================================================*/ 893 /*============================================================================*/ 894 895 #ifndef DRX_CFG_BASE 896 #define DRX_CFG_BASE 0 897 #endif 898 899 #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ 900 #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ 901 #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ 902 #define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ 903 #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ 904 #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ 905 #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ 906 #define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ 907 #define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ 908 #define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ 909 #define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ 910 #define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ 911 #define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ 912 #define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ 913 #define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ 914 #define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ 915 #define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ 916 #define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ 917 #define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ 918 919 #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE 920 /*============================================================================*/ 921 /*============================================================================*/ 922 /*== CTRL related data structures ============================================*/ 923 /*============================================================================*/ 924 /*============================================================================*/ 925 926 /* 927 * struct drxu_code_info Parameters for microcode upload and verfiy. 928 * 929 * @mc_file: microcode file name 930 * 931 * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE 932 */ 933 struct drxu_code_info { 934 char *mc_file; 935 }; 936 937 /* 938 * \struct drx_mc_version_rec_t 939 * \brief Microcode version record 940 * Version numbers are stored in BCD format, as usual: 941 * o major number = bits 31-20 (first three nibbles of MSW) 942 * o minor number = bits 19-16 (fourth nibble of MSW) 943 * o patch number = bits 15-0 (remaining nibbles in LSW) 944 * 945 * The device type indicates for which the device is meant. It is based on the 946 * JTAG ID, using everything except the bond ID and the metal fix. 947 * 948 * Special values: 949 * - mc_dev_type == 0 => any device allowed 950 * - mc_base_version == 0.0.0 => full microcode (mc_version is the version) 951 * - mc_base_version != 0.0.0 => patch microcode, the base microcode version 952 * (mc_version is the version) 953 */ 954 #define AUX_VER_RECORD 0x8000 955 956 struct drx_mc_version_rec { 957 u16 aux_type; /* type of aux data - 0x8000 for version record */ 958 u32 mc_dev_type; /* device type, based on JTAG ID */ 959 u32 mc_version; /* version of microcode */ 960 u32 mc_base_version; /* in case of patch: the original microcode version */ 961 }; 962 963 /*========================================*/ 964 965 /* 966 * \struct drx_filter_info_t 967 * \brief Parameters for loading filter coefficients 968 * 969 * Used by DRX_CTRL_LOAD_FILTER 970 */ 971 struct drx_filter_info { 972 u8 *data_re; 973 /*< pointer to coefficients for RE */ 974 u8 *data_im; 975 /*< pointer to coefficients for IM */ 976 u16 size_re; 977 /*< size of coefficients for RE */ 978 u16 size_im; 979 /*< size of coefficients for IM */ 980 }; 981 982 /*========================================*/ 983 984 /* 985 * \struct struct drx_channel * \brief The set of parameters describing a single channel. 986 * 987 * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. 988 * Only certain fields need to be used for a specific standard. 989 * 990 */ 991 struct drx_channel { 992 s32 frequency; 993 /*< frequency in kHz */ 994 enum drx_bandwidth bandwidth; 995 /*< bandwidth */ 996 enum drx_mirror mirror; /*< mirrored or not on RF */ 997 enum drx_modulation constellation; 998 /*< constellation */ 999 enum drx_hierarchy hierarchy; 1000 /*< hierarchy */ 1001 enum drx_priority priority; /*< priority */ 1002 enum drx_coderate coderate; /*< coderate */ 1003 enum drx_guard guard; /*< guard interval */ 1004 enum drx_fft_mode fftmode; /*< fftmode */ 1005 enum drx_classification classification; 1006 /*< classification */ 1007 u32 symbolrate; 1008 /*< symbolrate in symbols/sec */ 1009 enum drx_interleave_mode interleavemode; 1010 /*< interleaveMode QAM */ 1011 enum drx_ldpc ldpc; /*< ldpc */ 1012 enum drx_carrier_mode carrier; /*< carrier */ 1013 enum drx_frame_mode framemode; 1014 /*< frame mode */ 1015 enum drx_pilot_mode pilot; /*< pilot mode */ 1016 }; 1017 1018 /*========================================*/ 1019 1020 enum drx_cfg_sqi_speed { 1021 DRX_SQI_SPEED_FAST = 0, 1022 DRX_SQI_SPEED_MEDIUM, 1023 DRX_SQI_SPEED_SLOW, 1024 DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN 1025 }; 1026 1027 /*========================================*/ 1028 1029 /* 1030 * \struct struct drx_complex * A complex number. 1031 * 1032 * Used by DRX_CTRL_CONSTEL. 1033 */ 1034 struct drx_complex { 1035 s16 im; 1036 /*< Imaginary part. */ 1037 s16 re; 1038 /*< Real part. */ 1039 }; 1040 1041 /*========================================*/ 1042 1043 /* 1044 * \struct struct drx_frequency_plan * Array element of a frequency plan. 1045 * 1046 * Used by DRX_CTRL_SCAN_INIT. 1047 */ 1048 struct drx_frequency_plan { 1049 s32 first; 1050 /*< First centre frequency in this band */ 1051 s32 last; 1052 /*< Last centre frequency in this band */ 1053 s32 step; 1054 /*< Stepping frequency in this band */ 1055 enum drx_bandwidth bandwidth; 1056 /*< Bandwidth within this frequency band */ 1057 u16 ch_number; 1058 /*< First channel number in this band, or first 1059 index in ch_names */ 1060 char **ch_names; 1061 /*< Optional list of channel names in this 1062 band */ 1063 }; 1064 1065 /*========================================*/ 1066 1067 /* 1068 * \struct struct drx_scan_param * Parameters for channel scan. 1069 * 1070 * Used by DRX_CTRL_SCAN_INIT. 1071 */ 1072 struct drx_scan_param { 1073 struct drx_frequency_plan *frequency_plan; 1074 /*< Frequency plan (array)*/ 1075 u16 frequency_plan_size; /*< Number of bands */ 1076 u32 num_tries; /*< Max channels tried */ 1077 s32 skip; /*< Minimum frequency step to take 1078 after a channel is found */ 1079 void *ext_params; /*< Standard specific params */ 1080 }; 1081 1082 /*========================================*/ 1083 1084 /* 1085 * \brief Scan commands. 1086 * Used by scanning algorithms. 1087 */ 1088 enum drx_scan_command { 1089 DRX_SCAN_COMMAND_INIT = 0,/*< Initialize scanning */ 1090 DRX_SCAN_COMMAND_NEXT, /*< Next scan */ 1091 DRX_SCAN_COMMAND_STOP /*< Stop scanning */ 1092 }; 1093 1094 /*========================================*/ 1095 1096 /* 1097 * \brief Inner scan function prototype. 1098 */ 1099 typedef int(*drx_scan_func_t) (void *scan_context, 1100 enum drx_scan_command scan_command, 1101 struct drx_channel *scan_channel, 1102 bool *get_next_channel); 1103 1104 /*========================================*/ 1105 1106 /* 1107 * \struct struct drxtps_info * TPS information, DVB-T specific. 1108 * 1109 * Used by DRX_CTRL_TPS_INFO. 1110 */ 1111 struct drxtps_info { 1112 enum drx_fft_mode fftmode; /*< Fft mode */ 1113 enum drx_guard guard; /*< Guard interval */ 1114 enum drx_modulation constellation; 1115 /*< Constellation */ 1116 enum drx_hierarchy hierarchy; 1117 /*< Hierarchy */ 1118 enum drx_coderate high_coderate; 1119 /*< High code rate */ 1120 enum drx_coderate low_coderate; 1121 /*< Low cod rate */ 1122 enum drx_tps_frame frame; /*< Tps frame */ 1123 u8 length; /*< Length */ 1124 u16 cell_id; /*< Cell id */ 1125 }; 1126 1127 /*========================================*/ 1128 1129 /* 1130 * \brief Power mode of device. 1131 * 1132 * Used by DRX_CTRL_SET_POWER_MODE. 1133 */ 1134 enum drx_power_mode { 1135 DRX_POWER_UP = 0, 1136 /*< Generic , Power Up Mode */ 1137 DRX_POWER_MODE_1, 1138 /*< Device specific , Power Up Mode */ 1139 DRX_POWER_MODE_2, 1140 /*< Device specific , Power Up Mode */ 1141 DRX_POWER_MODE_3, 1142 /*< Device specific , Power Up Mode */ 1143 DRX_POWER_MODE_4, 1144 /*< Device specific , Power Up Mode */ 1145 DRX_POWER_MODE_5, 1146 /*< Device specific , Power Up Mode */ 1147 DRX_POWER_MODE_6, 1148 /*< Device specific , Power Up Mode */ 1149 DRX_POWER_MODE_7, 1150 /*< Device specific , Power Up Mode */ 1151 DRX_POWER_MODE_8, 1152 /*< Device specific , Power Up Mode */ 1153 1154 DRX_POWER_MODE_9, 1155 /*< Device specific , Power Down Mode */ 1156 DRX_POWER_MODE_10, 1157 /*< Device specific , Power Down Mode */ 1158 DRX_POWER_MODE_11, 1159 /*< Device specific , Power Down Mode */ 1160 DRX_POWER_MODE_12, 1161 /*< Device specific , Power Down Mode */ 1162 DRX_POWER_MODE_13, 1163 /*< Device specific , Power Down Mode */ 1164 DRX_POWER_MODE_14, 1165 /*< Device specific , Power Down Mode */ 1166 DRX_POWER_MODE_15, 1167 /*< Device specific , Power Down Mode */ 1168 DRX_POWER_MODE_16, 1169 /*< Device specific , Power Down Mode */ 1170 DRX_POWER_DOWN = 255 1171 /*< Generic , Power Down Mode */ 1172 }; 1173 1174 /*========================================*/ 1175 1176 /* 1177 * \enum enum drx_module * \brief Software module identification. 1178 * 1179 * Used by DRX_CTRL_VERSION. 1180 */ 1181 enum drx_module { 1182 DRX_MODULE_DEVICE, 1183 DRX_MODULE_MICROCODE, 1184 DRX_MODULE_DRIVERCORE, 1185 DRX_MODULE_DEVICEDRIVER, 1186 DRX_MODULE_DAP, 1187 DRX_MODULE_BSP_I2C, 1188 DRX_MODULE_BSP_TUNER, 1189 DRX_MODULE_BSP_HOST, 1190 DRX_MODULE_UNKNOWN 1191 }; 1192 1193 /* 1194 * \enum struct drx_version * \brief Version information of one software module. 1195 * 1196 * Used by DRX_CTRL_VERSION. 1197 */ 1198 struct drx_version { 1199 enum drx_module module_type; 1200 /*< Type identifier of the module */ 1201 char *module_name; 1202 /*< Name or description of module */ 1203 u16 v_major; /*< Major version number */ 1204 u16 v_minor; /*< Minor version number */ 1205 u16 v_patch; /*< Patch version number */ 1206 char *v_string; /*< Version as text string */ 1207 }; 1208 1209 /* 1210 * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. 1211 * 1212 * Used by DRX_CTRL_VERSION. 1213 */ 1214 struct drx_version_list { 1215 struct drx_version *version;/*< Version information */ 1216 struct drx_version_list *next; 1217 /*< Next list element */ 1218 }; 1219 1220 /*========================================*/ 1221 1222 /* 1223 * \brief Parameters needed to confiugure a UIO. 1224 * 1225 * Used by DRX_CTRL_UIO_CFG. 1226 */ 1227 struct drxuio_cfg { 1228 enum drx_uio uio; 1229 /*< UIO identifier */ 1230 enum drxuio_mode mode; 1231 /*< UIO operational mode */ 1232 }; 1233 1234 /*========================================*/ 1235 1236 /* 1237 * \brief Parameters needed to read from or write to a UIO. 1238 * 1239 * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. 1240 */ 1241 struct drxuio_data { 1242 enum drx_uio uio; 1243 /*< UIO identifier */ 1244 bool value; 1245 /*< UIO value (true=1, false=0) */ 1246 }; 1247 1248 /*========================================*/ 1249 1250 /* 1251 * \brief Parameters needed to configure OOB. 1252 * 1253 * Used by DRX_CTRL_SET_OOB. 1254 */ 1255 struct drxoob { 1256 s32 frequency; /*< Frequency in kHz */ 1257 enum drxoob_downstream_standard standard; 1258 /*< OOB standard */ 1259 bool spectrum_inverted; /*< If true, then spectrum 1260 is inverted */ 1261 }; 1262 1263 /*========================================*/ 1264 1265 /* 1266 * \brief Metrics from OOB. 1267 * 1268 * Used by DRX_CTRL_GET_OOB. 1269 */ 1270 struct drxoob_status { 1271 s32 frequency; /*< Frequency in Khz */ 1272 enum drx_lock_status lock; /*< Lock status */ 1273 u32 mer; /*< MER */ 1274 s32 symbol_rate_offset; /*< Symbolrate offset in ppm */ 1275 }; 1276 1277 /*========================================*/ 1278 1279 /* 1280 * \brief Device dependent configuration data. 1281 * 1282 * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. 1283 * A sort of nested drx_ctrl() functionality for device specific controls. 1284 */ 1285 struct drx_cfg { 1286 u32 cfg_type; 1287 /*< Function identifier */ 1288 void *cfg_data; 1289 /*< Function data */ 1290 }; 1291 1292 /*========================================*/ 1293 1294 /* 1295 * /struct DRXMpegStartWidth_t 1296 * MStart width [nr MCLK cycles] for serial MPEG output. 1297 */ 1298 1299 enum drxmpeg_str_width { 1300 DRX_MPEG_STR_WIDTH_1, 1301 DRX_MPEG_STR_WIDTH_8 1302 }; 1303 1304 /* CTRL CFG MPEG output */ 1305 /* 1306 * \struct struct drx_cfg_mpeg_output * \brief Configuration parameters for MPEG output control. 1307 * 1308 * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and 1309 * DRX_CTRL_GET_CFG. 1310 */ 1311 1312 struct drx_cfg_mpeg_output { 1313 bool enable_mpeg_output;/*< If true, enable MPEG output */ 1314 bool insert_rs_byte; /*< If true, insert RS byte */ 1315 bool enable_parallel; /*< If true, parallel out otherwise 1316 serial */ 1317 bool invert_data; /*< If true, invert DATA signals */ 1318 bool invert_err; /*< If true, invert ERR signal */ 1319 bool invert_str; /*< If true, invert STR signals */ 1320 bool invert_val; /*< If true, invert VAL signals */ 1321 bool invert_clk; /*< If true, invert CLK signals */ 1322 bool static_clk; /*< If true, static MPEG clockrate 1323 will be used, otherwise clockrate 1324 will adapt to the bitrate of the 1325 TS */ 1326 u32 bitrate; /*< Maximum bitrate in b/s in case 1327 static clockrate is selected */ 1328 enum drxmpeg_str_width width_str; 1329 /*< MPEG start width */ 1330 }; 1331 1332 1333 /*========================================*/ 1334 1335 /* 1336 * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. 1337 * 1338 * Used by DRX_CTRL_I2C_READWRITE. 1339 * If port_nr is equal to primairy port_nr BSPI2C will be used. 1340 * 1341 */ 1342 struct drxi2c_data { 1343 u16 port_nr; /*< I2C port number */ 1344 struct i2c_device_addr *w_dev_addr; 1345 /*< Write device address */ 1346 u16 w_count; /*< Size of write data in bytes */ 1347 u8 *wData; /*< Pointer to write data */ 1348 struct i2c_device_addr *r_dev_addr; 1349 /*< Read device address */ 1350 u16 r_count; /*< Size of data to read in bytes */ 1351 u8 *r_data; /*< Pointer to read buffer */ 1352 }; 1353 1354 /*========================================*/ 1355 1356 /* 1357 * \enum enum drx_aud_standard * \brief Audio standard identifier. 1358 * 1359 * Used by DRX_CTRL_SET_AUD. 1360 */ 1361 enum drx_aud_standard { 1362 DRX_AUD_STANDARD_BTSC, /*< set BTSC standard (USA) */ 1363 DRX_AUD_STANDARD_A2, /*< set A2-Korea FM Stereo */ 1364 DRX_AUD_STANDARD_EIAJ, /*< set to Japanese FM Stereo */ 1365 DRX_AUD_STANDARD_FM_STEREO,/*< set to FM-Stereo Radio */ 1366 DRX_AUD_STANDARD_M_MONO, /*< for 4.5 MHz mono detected */ 1367 DRX_AUD_STANDARD_D_K_MONO, /*< for 6.5 MHz mono detected */ 1368 DRX_AUD_STANDARD_BG_FM, /*< set BG_FM standard */ 1369 DRX_AUD_STANDARD_D_K1, /*< set D_K1 standard */ 1370 DRX_AUD_STANDARD_D_K2, /*< set D_K2 standard */ 1371 DRX_AUD_STANDARD_D_K3, /*< set D_K3 standard */ 1372 DRX_AUD_STANDARD_BG_NICAM_FM, 1373 /*< set BG_NICAM_FM standard */ 1374 DRX_AUD_STANDARD_L_NICAM_AM, 1375 /*< set L_NICAM_AM standard */ 1376 DRX_AUD_STANDARD_I_NICAM_FM, 1377 /*< set I_NICAM_FM standard */ 1378 DRX_AUD_STANDARD_D_K_NICAM_FM, 1379 /*< set D_K_NICAM_FM standard */ 1380 DRX_AUD_STANDARD_NOT_READY,/*< used to detect audio standard */ 1381 DRX_AUD_STANDARD_AUTO = DRX_AUTO, 1382 /*< Automatic Standard Detection */ 1383 DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN 1384 /*< used as auto and for readback */ 1385 }; 1386 1387 /* CTRL_AUD_GET_STATUS - struct drx_aud_status */ 1388 /* 1389 * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. 1390 */ 1391 enum drx_aud_nicam_status { 1392 DRX_AUD_NICAM_DETECTED = 0, 1393 /*< NICAM carrier detected */ 1394 DRX_AUD_NICAM_NOT_DETECTED, 1395 /*< NICAM carrier not detected */ 1396 DRX_AUD_NICAM_BAD /*< NICAM carrier bad quality */ 1397 }; 1398 1399 /* 1400 * \struct struct drx_aud_status * \brief Audio status characteristics. 1401 */ 1402 struct drx_aud_status { 1403 bool stereo; /*< stereo detection */ 1404 bool carrier_a; /*< carrier A detected */ 1405 bool carrier_b; /*< carrier B detected */ 1406 bool sap; /*< sap / bilingual detection */ 1407 bool rds; /*< RDS data array present */ 1408 enum drx_aud_nicam_status nicam_status; 1409 /*< status of NICAM carrier */ 1410 s8 fm_ident; /*< FM Identification value */ 1411 }; 1412 1413 /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ 1414 1415 /* 1416 * \struct DRXRDSdata_t 1417 * \brief Raw RDS data array. 1418 */ 1419 struct drx_cfg_aud_rds { 1420 bool valid; /*< RDS data validation */ 1421 u16 data[18]; /*< data from one RDS data array */ 1422 }; 1423 1424 /* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ 1425 /* 1426 * \enum DRXAudAVCDecayTime_t 1427 * \brief Automatic volume control configuration. 1428 */ 1429 enum drx_aud_avc_mode { 1430 DRX_AUD_AVC_OFF, /*< Automatic volume control off */ 1431 DRX_AUD_AVC_DECAYTIME_8S, /*< level volume in 8 seconds */ 1432 DRX_AUD_AVC_DECAYTIME_4S, /*< level volume in 4 seconds */ 1433 DRX_AUD_AVC_DECAYTIME_2S, /*< level volume in 2 seconds */ 1434 DRX_AUD_AVC_DECAYTIME_20MS/*< level volume in 20 millisec */ 1435 }; 1436 1437 /* 1438 * /enum DRXAudMaxAVCGain_t 1439 * /brief Automatic volume control max gain in audio baseband. 1440 */ 1441 enum drx_aud_avc_max_gain { 1442 DRX_AUD_AVC_MAX_GAIN_0DB, /*< maximum AVC gain 0 dB */ 1443 DRX_AUD_AVC_MAX_GAIN_6DB, /*< maximum AVC gain 6 dB */ 1444 DRX_AUD_AVC_MAX_GAIN_12DB /*< maximum AVC gain 12 dB */ 1445 }; 1446 1447 /* 1448 * /enum DRXAudMaxAVCAtten_t 1449 * /brief Automatic volume control max attenuation in audio baseband. 1450 */ 1451 enum drx_aud_avc_max_atten { 1452 DRX_AUD_AVC_MAX_ATTEN_12DB, 1453 /*< maximum AVC attenuation 12 dB */ 1454 DRX_AUD_AVC_MAX_ATTEN_18DB, 1455 /*< maximum AVC attenuation 18 dB */ 1456 DRX_AUD_AVC_MAX_ATTEN_24DB/*< maximum AVC attenuation 24 dB */ 1457 }; 1458 /* 1459 * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. 1460 */ 1461 struct drx_cfg_aud_volume { 1462 bool mute; /*< mute overrides volume setting */ 1463 s16 volume; /*< volume, range -114 to 12 dB */ 1464 enum drx_aud_avc_mode avc_mode; /*< AVC auto volume control mode */ 1465 u16 avc_ref_level; /*< AVC reference level */ 1466 enum drx_aud_avc_max_gain avc_max_gain; 1467 /*< AVC max gain selection */ 1468 enum drx_aud_avc_max_atten avc_max_atten; 1469 /*< AVC max attenuation selection */ 1470 s16 strength_left; /*< quasi-peak, left speaker */ 1471 s16 strength_right; /*< quasi-peak, right speaker */ 1472 }; 1473 1474 /* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ 1475 /* 1476 * \enum enum drxi2s_mode * \brief I2S output mode. 1477 */ 1478 enum drxi2s_mode { 1479 DRX_I2S_MODE_MASTER, /*< I2S is in master mode */ 1480 DRX_I2S_MODE_SLAVE /*< I2S is in slave mode */ 1481 }; 1482 1483 /* 1484 * \enum enum drxi2s_word_length * \brief Width of I2S data. 1485 */ 1486 enum drxi2s_word_length { 1487 DRX_I2S_WORDLENGTH_32 = 0,/*< I2S data is 32 bit wide */ 1488 DRX_I2S_WORDLENGTH_16 = 1 /*< I2S data is 16 bit wide */ 1489 }; 1490 1491 /* 1492 * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. 1493 */ 1494 enum drxi2s_format { 1495 DRX_I2S_FORMAT_WS_WITH_DATA, 1496 /*< I2S data and wordstrobe are aligned */ 1497 DRX_I2S_FORMAT_WS_ADVANCED 1498 /*< I2S data one cycle after wordstrobe */ 1499 }; 1500 1501 /* 1502 * \enum enum drxi2s_polarity * \brief Polarity of I2S data. 1503 */ 1504 enum drxi2s_polarity { 1505 DRX_I2S_POLARITY_RIGHT,/*< wordstrobe - right high, left low */ 1506 DRX_I2S_POLARITY_LEFT /*< wordstrobe - right low, left high */ 1507 }; 1508 1509 /* 1510 * \struct struct drx_cfg_i2s_output * \brief I2S output configuration. 1511 */ 1512 struct drx_cfg_i2s_output { 1513 bool output_enable; /*< I2S output enable */ 1514 u32 frequency; /*< range from 8000-48000 Hz */ 1515 enum drxi2s_mode mode; /*< I2S mode, master or slave */ 1516 enum drxi2s_word_length word_length; 1517 /*< I2S wordlength, 16 or 32 bits */ 1518 enum drxi2s_polarity polarity;/*< I2S wordstrobe polarity */ 1519 enum drxi2s_format format; /*< I2S wordstrobe delay to data */ 1520 }; 1521 1522 /* ------------------------------expert interface-----------------------------*/ 1523 /* 1524 * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. 1525 * 1526 */ 1527 enum drx_aud_fm_deemphasis { 1528 DRX_AUD_FM_DEEMPH_50US, 1529 DRX_AUD_FM_DEEMPH_75US, 1530 DRX_AUD_FM_DEEMPH_OFF 1531 }; 1532 1533 /* 1534 * /enum DRXAudDeviation_t 1535 * setting for deviation mode in audio demodulator. 1536 * 1537 */ 1538 enum drx_cfg_aud_deviation { 1539 DRX_AUD_DEVIATION_NORMAL, 1540 DRX_AUD_DEVIATION_HIGH 1541 }; 1542 1543 /* 1544 * /enum enum drx_no_carrier_option * setting for carrier, mute/noise. 1545 * 1546 */ 1547 enum drx_no_carrier_option { 1548 DRX_NO_CARRIER_MUTE, 1549 DRX_NO_CARRIER_NOISE 1550 }; 1551 1552 /* 1553 * \enum DRXAudAutoSound_t 1554 * \brief Automatic Sound 1555 */ 1556 enum drx_cfg_aud_auto_sound { 1557 DRX_AUD_AUTO_SOUND_OFF = 0, 1558 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, 1559 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF 1560 }; 1561 1562 /* 1563 * \enum DRXAudASSThres_t 1564 * \brief Automatic Sound Select Thresholds 1565 */ 1566 struct drx_cfg_aud_ass_thres { 1567 u16 a2; /* A2 Threshold for ASS configuration */ 1568 u16 btsc; /* BTSC Threshold for ASS configuration */ 1569 u16 nicam; /* Nicam Threshold for ASS configuration */ 1570 }; 1571 1572 /* 1573 * \struct struct drx_aud_carrier * \brief Carrier detection related parameters 1574 */ 1575 struct drx_aud_carrier { 1576 u16 thres; /* carrier detetcion threshold for primary carrier (A) */ 1577 enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ 1578 s32 shift; /* DC level of incoming signal (A) */ 1579 s32 dco; /* frequency adjustment (A) */ 1580 }; 1581 1582 /* 1583 * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct 1584 */ 1585 struct drx_cfg_aud_carriers { 1586 struct drx_aud_carrier a; 1587 struct drx_aud_carrier b; 1588 }; 1589 1590 /* 1591 * /enum enum drx_aud_i2s_src * Selection of audio source 1592 */ 1593 enum drx_aud_i2s_src { 1594 DRX_AUD_SRC_MONO, 1595 DRX_AUD_SRC_STEREO_OR_AB, 1596 DRX_AUD_SRC_STEREO_OR_A, 1597 DRX_AUD_SRC_STEREO_OR_B}; 1598 1599 /* 1600 * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. 1601 */ 1602 enum drx_aud_i2s_matrix { 1603 DRX_AUD_I2S_MATRIX_A_MONO, 1604 /*< A sound only, stereo or mono */ 1605 DRX_AUD_I2S_MATRIX_B_MONO, 1606 /*< B sound only, stereo or mono */ 1607 DRX_AUD_I2S_MATRIX_STEREO, 1608 /*< A+B sound, transparent */ 1609 DRX_AUD_I2S_MATRIX_MONO /*< A+B mixed to mono sum, (L+R)/2 */}; 1610 1611 /* 1612 * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. 1613 * 1614 */ 1615 enum drx_aud_fm_matrix { 1616 DRX_AUD_FM_MATRIX_NO_MATRIX, 1617 DRX_AUD_FM_MATRIX_GERMAN, 1618 DRX_AUD_FM_MATRIX_KOREAN, 1619 DRX_AUD_FM_MATRIX_SOUND_A, 1620 DRX_AUD_FM_MATRIX_SOUND_B}; 1621 1622 /* 1623 * \struct DRXAudMatrices_t 1624 * \brief Mixer settings 1625 */ 1626 struct drx_cfg_aud_mixer { 1627 enum drx_aud_i2s_src source_i2s; 1628 enum drx_aud_i2s_matrix matrix_i2s; 1629 enum drx_aud_fm_matrix matrix_fm; 1630 }; 1631 1632 /* 1633 * \enum DRXI2SVidSync_t 1634 * \brief Audio/video synchronization, interacts with I2S mode. 1635 * AUTO_1 and AUTO_2 are for automatic video standard detection with preference 1636 * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) 1637 */ 1638 enum drx_cfg_aud_av_sync { 1639 DRX_AUD_AVSYNC_OFF,/*< audio/video synchronization is off */ 1640 DRX_AUD_AVSYNC_NTSC, 1641 /*< it is an NTSC system */ 1642 DRX_AUD_AVSYNC_MONOCHROME, 1643 /*< it is a MONOCHROME system */ 1644 DRX_AUD_AVSYNC_PAL_SECAM 1645 /*< it is a PAL/SECAM system */}; 1646 1647 /* 1648 * \struct struct drx_cfg_aud_prescale * \brief Prescalers 1649 */ 1650 struct drx_cfg_aud_prescale { 1651 u16 fm_deviation; 1652 s16 nicam_gain; 1653 }; 1654 1655 /* 1656 * \struct struct drx_aud_beep * \brief Beep 1657 */ 1658 struct drx_aud_beep { 1659 s16 volume; /* dB */ 1660 u16 frequency; /* Hz */ 1661 bool mute; 1662 }; 1663 1664 /* 1665 * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode 1666 */ 1667 enum drx_aud_btsc_detect { 1668 DRX_BTSC_STEREO, 1669 DRX_BTSC_MONO_AND_SAP}; 1670 1671 /* 1672 * \struct struct drx_aud_data * \brief Audio data structure 1673 */ 1674 struct drx_aud_data { 1675 /* audio storage */ 1676 bool audio_is_active; 1677 enum drx_aud_standard audio_standard; 1678 struct drx_cfg_i2s_output i2sdata; 1679 struct drx_cfg_aud_volume volume; 1680 enum drx_cfg_aud_auto_sound auto_sound; 1681 struct drx_cfg_aud_ass_thres ass_thresholds; 1682 struct drx_cfg_aud_carriers carriers; 1683 struct drx_cfg_aud_mixer mixer; 1684 enum drx_cfg_aud_deviation deviation; 1685 enum drx_cfg_aud_av_sync av_sync; 1686 struct drx_cfg_aud_prescale prescale; 1687 enum drx_aud_fm_deemphasis deemph; 1688 enum drx_aud_btsc_detect btsc_detect; 1689 /* rds */ 1690 u16 rds_data_counter; 1691 bool rds_data_present; 1692 }; 1693 1694 /* 1695 * \enum enum drx_qam_lock_range * \brief QAM lock range mode 1696 */ 1697 enum drx_qam_lock_range { 1698 DRX_QAM_LOCKRANGE_NORMAL, 1699 DRX_QAM_LOCKRANGE_EXTENDED}; 1700 1701 /*============================================================================*/ 1702 /*============================================================================*/ 1703 /*== Data access structures ==================================================*/ 1704 /*============================================================================*/ 1705 /*============================================================================*/ 1706 1707 /* Address on device */ 1708 typedef u32 dr_xaddr_t, *pdr_xaddr_t; 1709 1710 /* Protocol specific flags */ 1711 typedef u32 dr_xflags_t, *pdr_xflags_t; 1712 1713 /* Write block of data to device */ 1714 typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1715 u32 addr, /* address of register/memory */ 1716 u16 datasize, /* size of data in bytes */ 1717 u8 *data, /* data to send */ 1718 u32 flags); 1719 1720 /* Read block of data from device */ 1721 typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1722 u32 addr, /* address of register/memory */ 1723 u16 datasize, /* size of data in bytes */ 1724 u8 *data, /* receive buffer */ 1725 u32 flags); 1726 1727 /* Write 8-bits value to device */ 1728 typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1729 u32 addr, /* address of register/memory */ 1730 u8 data, /* data to send */ 1731 u32 flags); 1732 1733 /* Read 8-bits value to device */ 1734 typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1735 u32 addr, /* address of register/memory */ 1736 u8 *data, /* receive buffer */ 1737 u32 flags); 1738 1739 /* Read modify write 8-bits value to device */ 1740 typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1741 u32 waddr, /* write address of register */ 1742 u32 raddr, /* read address of register */ 1743 u8 wdata, /* data to write */ 1744 u8 *rdata); /* data to read */ 1745 1746 /* Write 16-bits value to device */ 1747 typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1748 u32 addr, /* address of register/memory */ 1749 u16 data, /* data to send */ 1750 u32 flags); 1751 1752 /* Read 16-bits value to device */ 1753 typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1754 u32 addr, /* address of register/memory */ 1755 u16 *data, /* receive buffer */ 1756 u32 flags); 1757 1758 /* Read modify write 16-bits value to device */ 1759 typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1760 u32 waddr, /* write address of register */ 1761 u32 raddr, /* read address of register */ 1762 u16 wdata, /* data to write */ 1763 u16 *rdata); /* data to read */ 1764 1765 /* Write 32-bits value to device */ 1766 typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1767 u32 addr, /* address of register/memory */ 1768 u32 data, /* data to send */ 1769 u32 flags); 1770 1771 /* Read 32-bits value to device */ 1772 typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1773 u32 addr, /* address of register/memory */ 1774 u32 *data, /* receive buffer */ 1775 u32 flags); 1776 1777 /* Read modify write 32-bits value to device */ 1778 typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1779 u32 waddr, /* write address of register */ 1780 u32 raddr, /* read address of register */ 1781 u32 wdata, /* data to write */ 1782 u32 *rdata); /* data to read */ 1783 1784 /* 1785 * \struct struct drx_access_func * \brief Interface to an access protocol. 1786 */ 1787 struct drx_access_func { 1788 drx_write_block_func_t write_block_func; 1789 drx_read_block_func_t read_block_func; 1790 drx_write_reg8func_t write_reg8func; 1791 drx_read_reg8func_t read_reg8func; 1792 drx_read_modify_write_reg8func_t read_modify_write_reg8func; 1793 drx_write_reg16func_t write_reg16func; 1794 drx_read_reg16func_t read_reg16func; 1795 drx_read_modify_write_reg16func_t read_modify_write_reg16func; 1796 drx_write_reg32func_t write_reg32func; 1797 drx_read_reg32func_t read_reg32func; 1798 drx_read_modify_write_reg32func_t read_modify_write_reg32func; 1799 }; 1800 1801 /* Register address and data for register dump function */ 1802 struct drx_reg_dump { 1803 u32 address; 1804 u32 data; 1805 }; 1806 1807 /*============================================================================*/ 1808 /*============================================================================*/ 1809 /*== Demod instance data structures ==========================================*/ 1810 /*============================================================================*/ 1811 /*============================================================================*/ 1812 1813 /* 1814 * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. 1815 */ 1816 struct drx_common_attr { 1817 /* Microcode (firmware) attributes */ 1818 char *microcode_file; /*< microcode filename */ 1819 bool verify_microcode; 1820 /*< Use microcode verify or not. */ 1821 struct drx_mc_version_rec mcversion; 1822 /*< Version record of microcode from file */ 1823 1824 /* Clocks and tuner attributes */ 1825 s32 intermediate_freq; 1826 /*< IF,if tuner instance not used. (kHz)*/ 1827 s32 sys_clock_freq; 1828 /*< Systemclock frequency. (kHz) */ 1829 s32 osc_clock_freq; 1830 /*< Oscillator clock frequency. (kHz) */ 1831 s16 osc_clock_deviation; 1832 /*< Oscillator clock deviation. (ppm) */ 1833 bool mirror_freq_spect; 1834 /*< Mirror IF frequency spectrum or not.*/ 1835 1836 /* Initial MPEG output attributes */ 1837 struct drx_cfg_mpeg_output mpeg_cfg; 1838 /*< MPEG configuration */ 1839 1840 bool is_opened; /*< if true instance is already opened. */ 1841 1842 /* Channel scan */ 1843 struct drx_scan_param *scan_param; 1844 /*< scan parameters */ 1845 u16 scan_freq_plan_index; 1846 /*< next index in freq plan */ 1847 s32 scan_next_frequency; 1848 /*< next freq to scan */ 1849 bool scan_ready; /*< scan ready flag */ 1850 u32 scan_max_channels;/*< number of channels in freqplan */ 1851 u32 scan_channels_scanned; 1852 /*< number of channels scanned */ 1853 /* Channel scan - inner loop: demod related */ 1854 drx_scan_func_t scan_function; 1855 /*< function to check channel */ 1856 /* Channel scan - inner loop: SYSObj related */ 1857 void *scan_context; /*< Context Pointer of SYSObj */ 1858 /* Channel scan - parameters for default DTV scan function in core driver */ 1859 u16 scan_demod_lock_timeout; 1860 /*< millisecs to wait for lock */ 1861 enum drx_lock_status scan_desired_lock; 1862 /*< lock requirement for channel found */ 1863 /* scan_active can be used by SetChannel to decide how to program the tuner, 1864 fast or slow (but stable). Usually fast during scan. */ 1865 bool scan_active; /*< true when scan routines are active */ 1866 1867 /* Power management */ 1868 enum drx_power_mode current_power_mode; 1869 /*< current power management mode */ 1870 1871 /* Tuner */ 1872 u8 tuner_port_nr; /*< nr of I2C port to which tuner is */ 1873 s32 tuner_min_freq_rf; 1874 /*< minimum RF input frequency, in kHz */ 1875 s32 tuner_max_freq_rf; 1876 /*< maximum RF input frequency, in kHz */ 1877 bool tuner_rf_agc_pol; /*< if true invert RF AGC polarity */ 1878 bool tuner_if_agc_pol; /*< if true invert IF AGC polarity */ 1879 bool tuner_slow_mode; /*< if true invert IF AGC polarity */ 1880 1881 struct drx_channel current_channel; 1882 /*< current channel parameters */ 1883 enum drx_standard current_standard; 1884 /*< current standard selection */ 1885 enum drx_standard prev_standard; 1886 /*< previous standard selection */ 1887 enum drx_standard di_cache_standard; 1888 /*< standard in DI cache if available */ 1889 bool use_bootloader; /*< use bootloader in open */ 1890 u32 capabilities; /*< capabilities flags */ 1891 u32 product_id; /*< product ID inc. metal fix number */}; 1892 1893 /* 1894 * Generic functions for DRX devices. 1895 */ 1896 1897 struct drx_demod_instance; 1898 1899 /* 1900 * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. 1901 */ 1902 struct drx_demod_instance { 1903 /*< data access protocol functions */ 1904 struct i2c_device_addr *my_i2c_dev_addr; 1905 /*< i2c address and device identifier */ 1906 struct drx_common_attr *my_common_attr; 1907 /*< common DRX attributes */ 1908 void *my_ext_attr; /*< device specific attributes */ 1909 /* generic demodulator data */ 1910 1911 struct i2c_adapter *i2c; 1912 }; 1913 1914 /*------------------------------------------------------------------------- 1915 MACROS 1916 Conversion from enum values to human readable form. 1917 -------------------------------------------------------------------------*/ 1918 1919 /* standard */ 1920 1921 #define DRX_STR_STANDARD(x) ( \ 1922 (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ 1923 (x == DRX_STANDARD_8VSB) ? "8VSB" : \ 1924 (x == DRX_STANDARD_NTSC) ? "NTSC" : \ 1925 (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ 1926 (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ 1927 (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ 1928 (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ 1929 (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ 1930 (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ 1931 (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ 1932 (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ 1933 (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ 1934 (x == DRX_STANDARD_FM) ? "FM" : \ 1935 (x == DRX_STANDARD_DTMB) ? "DTMB" : \ 1936 (x == DRX_STANDARD_AUTO) ? "Auto" : \ 1937 (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ 1938 "(Invalid)") 1939 1940 /* channel */ 1941 1942 #define DRX_STR_BANDWIDTH(x) ( \ 1943 (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ 1944 (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ 1945 (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ 1946 (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ 1947 (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ 1948 "(Invalid)") 1949 #define DRX_STR_FFTMODE(x) ( \ 1950 (x == DRX_FFTMODE_2K) ? "2k" : \ 1951 (x == DRX_FFTMODE_4K) ? "4k" : \ 1952 (x == DRX_FFTMODE_8K) ? "8k" : \ 1953 (x == DRX_FFTMODE_AUTO) ? "Auto" : \ 1954 (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ 1955 "(Invalid)") 1956 #define DRX_STR_GUARD(x) ( \ 1957 (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ 1958 (x == DRX_GUARD_1DIV16) ? "1/16th" : \ 1959 (x == DRX_GUARD_1DIV8) ? "1/8th" : \ 1960 (x == DRX_GUARD_1DIV4) ? "1/4th" : \ 1961 (x == DRX_GUARD_AUTO) ? "Auto" : \ 1962 (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ 1963 "(Invalid)") 1964 #define DRX_STR_CONSTELLATION(x) ( \ 1965 (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ 1966 (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ 1967 (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ 1968 (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ 1969 (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ 1970 (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ 1971 (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ 1972 (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ 1973 (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ 1974 (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ 1975 (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ 1976 (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ 1977 (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ 1978 "(Invalid)") 1979 #define DRX_STR_CODERATE(x) ( \ 1980 (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ 1981 (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ 1982 (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ 1983 (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ 1984 (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ 1985 (x == DRX_CODERATE_AUTO) ? "Auto" : \ 1986 (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ 1987 "(Invalid)") 1988 #define DRX_STR_HIERARCHY(x) ( \ 1989 (x == DRX_HIERARCHY_NONE) ? "None" : \ 1990 (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ 1991 (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ 1992 (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ 1993 (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ 1994 (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ 1995 "(Invalid)") 1996 #define DRX_STR_PRIORITY(x) ( \ 1997 (x == DRX_PRIORITY_LOW) ? "Low" : \ 1998 (x == DRX_PRIORITY_HIGH) ? "High" : \ 1999 (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ 2000 "(Invalid)") 2001 #define DRX_STR_MIRROR(x) ( \ 2002 (x == DRX_MIRROR_NO) ? "Normal" : \ 2003 (x == DRX_MIRROR_YES) ? "Mirrored" : \ 2004 (x == DRX_MIRROR_AUTO) ? "Auto" : \ 2005 (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ 2006 "(Invalid)") 2007 #define DRX_STR_CLASSIFICATION(x) ( \ 2008 (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ 2009 (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ 2010 (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ 2011 (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ 2012 (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ 2013 (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ 2014 (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ 2015 (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ 2016 "(Invalid)") 2017 2018 #define DRX_STR_INTERLEAVEMODE(x) ( \ 2019 (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ 2020 (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ 2021 (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ 2022 (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ 2023 (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ 2024 (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ 2025 (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ 2026 (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ 2027 (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ 2028 (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ 2029 (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ 2030 (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ 2031 (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ 2032 (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ 2033 (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ 2034 (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ 2035 (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ 2036 (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ 2037 (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ 2038 (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ 2039 (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ 2040 (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ 2041 (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ 2042 (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ 2043 "(Invalid)") 2044 2045 #define DRX_STR_LDPC(x) ( \ 2046 (x == DRX_LDPC_0_4) ? "0.4" : \ 2047 (x == DRX_LDPC_0_6) ? "0.6" : \ 2048 (x == DRX_LDPC_0_8) ? "0.8" : \ 2049 (x == DRX_LDPC_AUTO) ? "Auto" : \ 2050 (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ 2051 "(Invalid)") 2052 2053 #define DRX_STR_CARRIER(x) ( \ 2054 (x == DRX_CARRIER_MULTI) ? "Multi" : \ 2055 (x == DRX_CARRIER_SINGLE) ? "Single" : \ 2056 (x == DRX_CARRIER_AUTO) ? "Auto" : \ 2057 (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ 2058 "(Invalid)") 2059 2060 #define DRX_STR_FRAMEMODE(x) ( \ 2061 (x == DRX_FRAMEMODE_420) ? "420" : \ 2062 (x == DRX_FRAMEMODE_595) ? "595" : \ 2063 (x == DRX_FRAMEMODE_945) ? "945" : \ 2064 (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ 2065 (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ 2066 (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ 2067 (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ 2068 "(Invalid)") 2069 2070 #define DRX_STR_PILOT(x) ( \ 2071 (x == DRX_PILOT_ON) ? "On" : \ 2072 (x == DRX_PILOT_OFF) ? "Off" : \ 2073 (x == DRX_PILOT_AUTO) ? "Auto" : \ 2074 (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ 2075 "(Invalid)") 2076 /* TPS */ 2077 2078 #define DRX_STR_TPS_FRAME(x) ( \ 2079 (x == DRX_TPS_FRAME1) ? "Frame1" : \ 2080 (x == DRX_TPS_FRAME2) ? "Frame2" : \ 2081 (x == DRX_TPS_FRAME3) ? "Frame3" : \ 2082 (x == DRX_TPS_FRAME4) ? "Frame4" : \ 2083 (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ 2084 "(Invalid)") 2085 2086 /* lock status */ 2087 2088 #define DRX_STR_LOCKSTATUS(x) ( \ 2089 (x == DRX_NEVER_LOCK) ? "Never" : \ 2090 (x == DRX_NOT_LOCKED) ? "No" : \ 2091 (x == DRX_LOCKED) ? "Locked" : \ 2092 (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ 2093 (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ 2094 (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ 2095 (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ 2096 (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ 2097 (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ 2098 (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ 2099 (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ 2100 (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ 2101 "(Invalid)") 2102 2103 /* version information , modules */ 2104 #define DRX_STR_MODULE(x) ( \ 2105 (x == DRX_MODULE_DEVICE) ? "Device" : \ 2106 (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ 2107 (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ 2108 (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ 2109 (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ 2110 (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ 2111 (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ 2112 (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ 2113 (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ 2114 "(Invalid)") 2115 2116 #define DRX_STR_POWER_MODE(x) ( \ 2117 (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ 2118 (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ 2119 (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ 2120 (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ 2121 (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ 2122 (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ 2123 (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ 2124 (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ 2125 (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ 2126 (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ 2127 (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ 2128 (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ 2129 (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ 2130 (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ 2131 (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ 2132 (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ 2133 (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ 2134 (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ 2135 "(Invalid)") 2136 2137 #define DRX_STR_OOB_STANDARD(x) ( \ 2138 (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ 2139 (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ 2140 (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ 2141 "(Invalid)") 2142 2143 #define DRX_STR_AUD_STANDARD(x) ( \ 2144 (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ 2145 (x == DRX_AUD_STANDARD_A2) ? "A2" : \ 2146 (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ 2147 (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ 2148 (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ 2149 (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ 2150 (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ 2151 (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ 2152 (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ 2153 (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ 2154 (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ 2155 (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ 2156 (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ 2157 (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ 2158 (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ 2159 (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ 2160 "(Invalid)") 2161 #define DRX_STR_AUD_STEREO(x) ( \ 2162 (x == true) ? "Stereo" : \ 2163 (x == false) ? "Mono" : \ 2164 "(Invalid)") 2165 2166 #define DRX_STR_AUD_SAP(x) ( \ 2167 (x == true) ? "Present" : \ 2168 (x == false) ? "Not present" : \ 2169 "(Invalid)") 2170 2171 #define DRX_STR_AUD_CARRIER(x) ( \ 2172 (x == true) ? "Present" : \ 2173 (x == false) ? "Not present" : \ 2174 "(Invalid)") 2175 2176 #define DRX_STR_AUD_RDS(x) ( \ 2177 (x == true) ? "Available" : \ 2178 (x == false) ? "Not Available" : \ 2179 "(Invalid)") 2180 2181 #define DRX_STR_AUD_NICAM_STATUS(x) ( \ 2182 (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ 2183 (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ 2184 (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ 2185 "(Invalid)") 2186 2187 #define DRX_STR_RDS_VALID(x) ( \ 2188 (x == true) ? "Valid" : \ 2189 (x == false) ? "Not Valid" : \ 2190 "(Invalid)") 2191 2192 /*------------------------------------------------------------------------- 2193 Access macros 2194 -------------------------------------------------------------------------*/ 2195 2196 /* 2197 * \brief Create a compilable reference to the microcode attribute 2198 * \param d pointer to demod instance 2199 * 2200 * Used as main reference to an attribute field. 2201 * Used by both macro implementation and function implementation. 2202 * These macros are defined to avoid duplication of code in macro and function 2203 * definitions that handle access of demod common or extended attributes. 2204 * 2205 */ 2206 2207 #define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) 2208 #define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) 2209 #define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) 2210 #define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) 2211 #define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) 2212 #define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) 2213 #define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) 2214 #define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) 2215 #define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) 2216 #define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) 2217 #define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) 2218 #define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) 2219 #define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) 2220 #define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) 2221 #define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) 2222 #define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) 2223 #define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) 2224 #define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) 2225 #define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) 2226 #define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) 2227 #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) 2228 #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) 2229 2230 /*************************/ 2231 2232 /* Macros with device-specific handling are converted to CFG functions */ 2233 2234 #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ 2235 do { \ 2236 struct drx_cfg config; \ 2237 data_type cfg_data; \ 2238 config.cfg_type = cfg_name; \ 2239 config.cfg_data = &cfg_data; \ 2240 cfg_data = value; \ 2241 drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ 2242 } while (0) 2243 2244 #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ 2245 do { \ 2246 int cfg_status; \ 2247 struct drx_cfg config; \ 2248 data_type cfg_data; \ 2249 config.cfg_type = cfg_name; \ 2250 config.cfg_data = &cfg_data; \ 2251 cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ 2252 if (cfg_status == 0) { \ 2253 value = cfg_data; \ 2254 } else { \ 2255 value = (data_type)error_value; \ 2256 } \ 2257 } while (0) 2258 2259 /* Configuration functions for usage by Access (XS) Macros */ 2260 2261 #ifndef DRX_XS_CFG_BASE 2262 #define DRX_XS_CFG_BASE (500) 2263 #endif 2264 2265 #define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) 2266 #define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) 2267 #define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) 2268 2269 /* Access Macros with device-specific handling */ 2270 2271 #define DRX_SET_PRESET(d, x) \ 2272 DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) 2273 #define DRX_GET_PRESET(d, x) \ 2274 DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") 2275 2276 #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ 2277 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) 2278 #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ 2279 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) 2280 2281 #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ 2282 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) 2283 #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ 2284 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) 2285 2286 /* 2287 * \brief Macro to check if std is an ATV standard 2288 * \retval true std is an ATV standard 2289 * \retval false std is an ATV standard 2290 */ 2291 #define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ 2292 ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ 2293 ((std) == DRX_STANDARD_PAL_SECAM_I) || \ 2294 ((std) == DRX_STANDARD_PAL_SECAM_L) || \ 2295 ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ 2296 ((std) == DRX_STANDARD_NTSC) || \ 2297 ((std) == DRX_STANDARD_FM)) 2298 2299 /* 2300 * \brief Macro to check if std is an QAM standard 2301 * \retval true std is an QAM standards 2302 * \retval false std is an QAM standards 2303 */ 2304 #define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ 2305 ((std) == DRX_STANDARD_ITU_B) || \ 2306 ((std) == DRX_STANDARD_ITU_C) || \ 2307 ((std) == DRX_STANDARD_ITU_D)) 2308 2309 /* 2310 * \brief Macro to check if std is VSB standard 2311 * \retval true std is VSB standard 2312 * \retval false std is not VSB standard 2313 */ 2314 #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) 2315 2316 /* 2317 * \brief Macro to check if std is DVBT standard 2318 * \retval true std is DVBT standard 2319 * \retval false std is not DVBT standard 2320 */ 2321 #define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) 2322 2323 /*------------------------------------------------------------------------- 2324 THE END 2325 -------------------------------------------------------------------------*/ 2326 #endif /* __DRXDRIVER_H__ */ 2327