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Searched refs:DRAMClockChangeSupport (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c284 …enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context-… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
290 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
296 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
298 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
301 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
1083 …} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_… in subvp_validate_static_schedulability()
1490 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) || in dcn32_full_validate_bw_helper()
1491 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || in dcn32_full_validate_bw_helper()
1531 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) { in dcn32_full_validate_bw_helper()
1563 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported; in dcn32_full_validate_bw_helper()
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H A Ddisplay_mode_vba_util_32.h827 enum clock_change_support *DRAMClockChangeSupport,
H A Ddisplay_mode_vba_32.c1711 || mode_lib->vba.DRAMClockChangeSupport[i][j] != dm_dram_clock_change_unsupported) in mode_support_configuration()
3608 &v->DRAMClockChangeSupport[i][j], in dml32_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c206 if (dml_result && s->evaluation_info.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive) { in calculate_lowest_supported_state_for_temp_read()
467 …out_clks.p_state_supported = s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_chan… in dml2_validate_and_build_resource()
555 …*dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport in dml2_extract_dram_and_fclk_change_support()
H A Ddisplay_mode_core.c3049 *p->DRAMClockChangeSupport = dml_dram_clock_change_vactive; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3051 *p->DRAMClockChangeSupport = dml_dram_clock_change_vblank; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3053 *p->DRAMClockChangeSupport = dml_dram_clock_change_vblank_drr; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3055 *p->DRAMClockChangeSupport = dml_dram_clock_change_unsupported; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3059 *p->DRAMClockChangeSupport = dml_dram_clock_change_vactive_w_mall_full_frame; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3061 *p->DRAMClockChangeSupport = dml_dram_clock_change_vblank_w_mall_full_frame; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3063 *p->DRAMClockChangeSupport = dml_dram_clock_change_vblank_drr_w_mall_full_frame; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3065 *p->DRAMClockChangeSupport = dml_dram_clock_change_unsupported; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3069 *p->DRAMClockChangeSupport = dml_dram_clock_change_vactive_w_mall_sub_vp; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3071 *p->DRAMClockChangeSupport = dml_dram_clock_change_vblank_w_mall_sub_vp; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
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H A Ddisplay_mode_util.c499 if (!fail_only || support->DRAMClockChangeSupport[j] == dml_dram_clock_change_unsupported) in dml_print_dml_mode_support_info()
500 …("DML: support: combine=%d, DRAMClockChangeSupport = %d\n", j, support->DRAMClockChangeSupport[j]); in dml_print_dml_mode_support_info()
H A Ddisplay_mode_core_structs.h773 enum dml_dram_clock_change_support DRAMClockChangeSupport[2]; member
1253 enum dml_dram_clock_change_support DRAMClockChangeSupport; member
1381 enum dml_dram_clock_change_support *DRAMClockChangeSupport; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h265 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; member
973 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; member
1756 enum dml2_pstate_change_support *DRAMClockChangeSupport; member
H A Ddml2_core_dcn4_calcs.c6897 p->DRAMClockChangeSupport[k] = dml2_pstate_change_unsupported; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6901 p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank_and_vactive; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6903 p->DRAMClockChangeSupport[k] = dml2_pstate_change_vactive; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6905 p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6907 p->DRAMClockChangeSupport[k] = dml2_pstate_change_vactive; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6909 p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6911 p->DRAMClockChangeSupport[k] = dml2_pstate_change_drr; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6913 p->DRAMClockChangeSupport[k] = dml2_pstate_change_mall_svp; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6915 p->DRAMClockChangeSupport[k] = dml2_pstate_change_mall_full_frame; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6917 if (p->DRAMClockChangeSupport[k] == dml2_pstate_change_unsupported) in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h847 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2]; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1683 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1709 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1164 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c649 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] != in set_p_state_switch_method()