| /linux/Documentation/hid/ |
| H A D | amd-sfh-hid.rst | 60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On
72 2. Data transfer via DRAM.
77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client
78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver
79 shall allocate minimum of 32 bytes DRAM space.
103 | | | Allocate the DRAM | Enable |
136 | | | Read the DRAM data for| | |
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| /linux/Documentation/driver-api/cxl/platform/acpi/ |
| H A D | hmat.rst | 24 Entry : 0080 <- DRAM LTC
31 Entry : 1200 <- DRAM BW
|
| /linux/drivers/memory/samsung/ |
| H A D | Kconfig | 19 Frequency Scaling in DMC and DRAM. It also supports changing timings
20 of DRAM running with different frequency. The timings are calculated
|
| /linux/Documentation/devicetree/bindings/firmware/ |
| H A D | nvidia,tegra210-bpmp.txt | 6 (suspend to ram), and also offloading DRAM memory clock scaling on
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
|
| /linux/Documentation/edac/ |
| H A D | memory_repair.rst | 30 in a DRAM device.
32 For example, a CXL memory device with DRAM components that support PPR
33 features implements maintenance operations. DRAM components support those
95 media or DRAM trace event to userspace, and userspace tools (e.g.
138 device with DRAM components that support memory sparing features may
146 For example, a CXL device with DRAM components that support PPR features
|
| H A D | scrub.rst | 19 Increasing DRAM size and cost have made memory subsystem reliability an
47 1. Background (patrol) scrubbing while the DRAM is otherwise idle.
131 allowing DRAM to internally read, correct single-bit errors, and write back
132 corrected data bits to the DRAM array while providing transparency to error
242 | reporting | Exception |media/DRAM |media/DRAM | notify and|
|
| /linux/arch/arm/configs/ |
| H A D | dram_0xc0000000.config | 1 # Help: DRAM base at 0xc0000000
|
| H A D | dram_0x00000000.config | 1 # Help: DRAM base at 0x00000000
|
| H A D | dram_0xd0000000.config | 1 # Help: DRAM base at 0xd0000000
|
| /linux/Documentation/translations/zh_CN/mm/damon/ |
| H A D | index.rst | 19 - *准确度* （监测输出对DRAM级别的内存管理足够有用；但可能不适合CPU Cache级别），
|
| /linux/Documentation/admin-guide/perf/ |
| H A D | meson-ddr-pmu.rst | 7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller.
9 DRAM. The channel can count up to 3 AXI port simultaneously. It can be helpful
|
| H A D | imx-ddr.rst | 5 There are no performance counters inside the DRAM controller, so performance
30 from different DRAM controller implementations, which is distinguished by quirks
|
| /linux/arch/arm/ |
| H A D | Kconfig-nommu | 14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
18 hex '(S)DRAM SIZE' if SET_MEM_PARAM
|
| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 18 The individual DRAM chips on a memory stick. These devices commonly
69 This is the name of the DRAM signal used to select the DRAM ranks to be
112 communication lanes. It uses vertically stacked memory chips (DRAM dies)
202 of 4096-bits of DRAM data bus.
204 While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC
205 channel is interfacing 2GB of DRAM (represented as rank).
|
| /linux/Documentation/hwmon/ |
| H A D | asus_wmi_sensors.rst | 37 * DRAM Voltage,
48 * DRAM Voltage,
|
| /linux/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | stingray-board-base.dtsi | 22 &memory { /* Default DRAM banks */
|
| /linux/Documentation/driver-api/cxl/allocation/ |
| H A D | page-allocator.rst | 21 Generally, we expect to see local DRAM and CXL memory on separate NUMA nodes,
23 for a compute node to have no local DRAM, and for CXL memory to be the
|
| /linux/arch/arm/mach-lpc32xx/ |
| H A D | suspend.S | 51 @ This guarantees a small windows where DRAM isn't busy
|
| /linux/Documentation/arch/arm/sa1100/ |
| H A D | lart.rst | 6 applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
|
| /linux/arch/x86/ras/ |
| H A D | Kconfig | 13 have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS.
|
| /linux/Documentation/translations/zh_CN/arch/riscv/ |
| H A D | boot.rst | 130 映射地址转换为物理地址，它们需要知道DRAM的起始位置。这发生在步骤1之后，
|
| /linux/arch/arm/boot/dts/synaptics/ |
| H A D | berlin2cd-valve-steamlink.dts | 43 * DRAM (providing 1.35V). The other regulator on the opposite side
|
| /linux/Documentation/admin-guide/media/ |
| H A D | raspberrypi-pisp-be.rst | 11 image data from DRAM memory and performs image processing as specified by the
25 in DRAM memory and processing them in the PiSP Back End to obtain images usable
|
| /linux/arch/arm/mach-tegra/ |
| H A D | sleep-tegra20.S | 243 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
354 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
|
| /linux/arch/arm/mach-sa1100/ |
| H A D | sleep.S | 133 @ Step 5 clear DRAM refresh control register
|