xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c (revision ec8c17e5ecb4a5a74069687ccb6d2cfe1851302e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
5  * Copyright (C) 2013 Red Hat
6  * Author: Rob Clark <robdclark@gmail.com>
7  */
8 
9 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
10 #include <linux/sort.h>
11 #include <linux/debugfs.h>
12 #include <linux/ktime.h>
13 #include <linux/bits.h>
14 
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_blend.h>
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_flip_work.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_mode.h>
21 #include <drm/drm_probe_helper.h>
22 #include <drm/drm_rect.h>
23 #include <drm/drm_vblank.h>
24 #include <drm/drm_self_refresh_helper.h>
25 
26 #include "dpu_kms.h"
27 #include "dpu_hw_lm.h"
28 #include "dpu_hw_ctl.h"
29 #include "dpu_hw_dspp.h"
30 #include "dpu_crtc.h"
31 #include "dpu_plane.h"
32 #include "dpu_encoder.h"
33 #include "dpu_vbif.h"
34 #include "dpu_core_perf.h"
35 #include "dpu_trace.h"
36 
37 /* layer mixer index on dpu_crtc */
38 #define LEFT_MIXER 0
39 #define RIGHT_MIXER 1
40 
41 /* timeout in ms waiting for frame done */
42 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS	60
43 
44 #define	CONVERT_S3_15(val) \
45 	(((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))
46 
_dpu_crtc_get_kms(struct drm_crtc * crtc)47 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
48 {
49 	struct msm_drm_private *priv = crtc->dev->dev_private;
50 
51 	return to_dpu_kms(priv->kms);
52 }
53 
get_encoder_from_crtc(struct drm_crtc * crtc)54 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
55 {
56 	struct drm_device *dev = crtc->dev;
57 	struct drm_encoder *encoder;
58 
59 	drm_for_each_encoder(encoder, dev)
60 		if (encoder->crtc == crtc)
61 			return encoder;
62 
63 	return NULL;
64 }
65 
dpu_crtc_parse_crc_source(const char * src_name)66 static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name)
67 {
68 	if (!src_name ||
69 	    !strcmp(src_name, "none"))
70 		return DPU_CRTC_CRC_SOURCE_NONE;
71 	if (!strcmp(src_name, "auto") ||
72 	    !strcmp(src_name, "lm"))
73 		return DPU_CRTC_CRC_SOURCE_LAYER_MIXER;
74 	if (!strcmp(src_name, "encoder"))
75 		return DPU_CRTC_CRC_SOURCE_ENCODER;
76 
77 	return DPU_CRTC_CRC_SOURCE_INVALID;
78 }
79 
dpu_crtc_verify_crc_source(struct drm_crtc * crtc,const char * src_name,size_t * values_cnt)80 static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc,
81 		const char *src_name, size_t *values_cnt)
82 {
83 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
84 	struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
85 
86 	if (source < 0) {
87 		DRM_DEBUG_DRIVER("Invalid source %s for CRTC%d\n", src_name, crtc->index);
88 		return -EINVAL;
89 	}
90 
91 	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) {
92 		*values_cnt = crtc_state->num_mixers;
93 	} else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) {
94 		struct drm_encoder *drm_enc;
95 
96 		*values_cnt = 0;
97 
98 		drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
99 			*values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc);
100 	}
101 
102 	return 0;
103 }
104 
dpu_crtc_setup_lm_misr(struct dpu_crtc_state * crtc_state)105 static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
106 {
107 	struct dpu_crtc_mixer *m;
108 	int i;
109 
110 	for (i = 0; i < crtc_state->num_mixers; ++i) {
111 		m = &crtc_state->mixers[i];
112 
113 		if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
114 			continue;
115 
116 		/* Calculate MISR over 1 frame */
117 		m->hw_lm->ops.setup_misr(m->hw_lm);
118 	}
119 }
120 
dpu_crtc_setup_encoder_misr(struct drm_crtc * crtc)121 static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc)
122 {
123 	struct drm_encoder *drm_enc;
124 
125 	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
126 		dpu_encoder_setup_misr(drm_enc);
127 }
128 
dpu_crtc_set_crc_source(struct drm_crtc * crtc,const char * src_name)129 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
130 {
131 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
132 	enum dpu_crtc_crc_source current_source;
133 	struct dpu_crtc_state *crtc_state;
134 	struct drm_device *drm_dev = crtc->dev;
135 
136 	bool was_enabled;
137 	bool enable = false;
138 	int ret = 0;
139 
140 	if (source < 0) {
141 		DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index);
142 		return -EINVAL;
143 	}
144 
145 	ret = drm_modeset_lock(&crtc->mutex, NULL);
146 
147 	if (ret)
148 		return ret;
149 
150 	enable = (source != DPU_CRTC_CRC_SOURCE_NONE);
151 	crtc_state = to_dpu_crtc_state(crtc->state);
152 
153 	spin_lock_irq(&drm_dev->event_lock);
154 	current_source = crtc_state->crc_source;
155 	spin_unlock_irq(&drm_dev->event_lock);
156 
157 	was_enabled = (current_source != DPU_CRTC_CRC_SOURCE_NONE);
158 
159 	if (!was_enabled && enable) {
160 		ret = drm_crtc_vblank_get(crtc);
161 
162 		if (ret)
163 			goto cleanup;
164 
165 	} else if (was_enabled && !enable) {
166 		drm_crtc_vblank_put(crtc);
167 	}
168 
169 	spin_lock_irq(&drm_dev->event_lock);
170 	crtc_state->crc_source = source;
171 	spin_unlock_irq(&drm_dev->event_lock);
172 
173 	crtc_state->crc_frame_skip_count = 0;
174 
175 	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
176 		dpu_crtc_setup_lm_misr(crtc_state);
177 	else if (source == DPU_CRTC_CRC_SOURCE_ENCODER)
178 		dpu_crtc_setup_encoder_misr(crtc);
179 	else
180 		ret = -EINVAL;
181 
182 cleanup:
183 	drm_modeset_unlock(&crtc->mutex);
184 
185 	return ret;
186 }
187 
dpu_crtc_get_vblank_counter(struct drm_crtc * crtc)188 static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
189 {
190 	struct drm_encoder *encoder = get_encoder_from_crtc(crtc);
191 	if (!encoder) {
192 		DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
193 		return 0;
194 	}
195 
196 	return dpu_encoder_get_vsync_count(encoder);
197 }
198 
dpu_crtc_get_lm_crc(struct drm_crtc * crtc,struct dpu_crtc_state * crtc_state)199 static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
200 		struct dpu_crtc_state *crtc_state)
201 {
202 	struct dpu_crtc_mixer *m;
203 	u32 crcs[CRTC_DUAL_MIXERS];
204 
205 	int rc = 0;
206 	int i;
207 
208 	BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers));
209 
210 	for (i = 0; i < crtc_state->num_mixers; ++i) {
211 
212 		m = &crtc_state->mixers[i];
213 
214 		if (!m->hw_lm || !m->hw_lm->ops.collect_misr)
215 			continue;
216 
217 		rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]);
218 
219 		if (rc) {
220 			if (rc != -ENODATA)
221 				DRM_DEBUG_DRIVER("MISR read failed\n");
222 			return rc;
223 		}
224 	}
225 
226 	return drm_crtc_add_crc_entry(crtc, true,
227 			drm_crtc_accurate_vblank_count(crtc), crcs);
228 }
229 
dpu_crtc_get_encoder_crc(struct drm_crtc * crtc)230 static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc)
231 {
232 	struct drm_encoder *drm_enc;
233 	int rc, pos = 0;
234 	u32 crcs[INTF_MAX];
235 
236 	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) {
237 		rc = dpu_encoder_get_crc(drm_enc, crcs, pos);
238 		if (rc < 0) {
239 			if (rc != -ENODATA)
240 				DRM_DEBUG_DRIVER("MISR read failed\n");
241 
242 			return rc;
243 		}
244 
245 		pos += rc;
246 	}
247 
248 	return drm_crtc_add_crc_entry(crtc, true,
249 			drm_crtc_accurate_vblank_count(crtc), crcs);
250 }
251 
dpu_crtc_get_crc(struct drm_crtc * crtc)252 static int dpu_crtc_get_crc(struct drm_crtc *crtc)
253 {
254 	struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
255 
256 	/* Skip first 2 frames in case of "uncooked" CRCs */
257 	if (crtc_state->crc_frame_skip_count < 2) {
258 		crtc_state->crc_frame_skip_count++;
259 		return 0;
260 	}
261 
262 	if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
263 		return dpu_crtc_get_lm_crc(crtc, crtc_state);
264 	else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER)
265 		return dpu_crtc_get_encoder_crc(crtc);
266 
267 	return -EINVAL;
268 }
269 
dpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)270 static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
271 					   bool in_vblank_irq,
272 					   int *vpos, int *hpos,
273 					   ktime_t *stime, ktime_t *etime,
274 					   const struct drm_display_mode *mode)
275 {
276 	unsigned int pipe = crtc->index;
277 	struct drm_encoder *encoder;
278 	int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
279 
280 	encoder = get_encoder_from_crtc(crtc);
281 	if (!encoder) {
282 		DRM_ERROR("no encoder found for crtc %d\n", pipe);
283 		return false;
284 	}
285 
286 	vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
287 	vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
288 
289 	/*
290 	 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
291 	 * the end of VFP. Translate the porch values relative to the line
292 	 * counter positions.
293 	 */
294 
295 	vactive_start = vsw + vbp + 1;
296 	vactive_end = vactive_start + mode->crtc_vdisplay;
297 
298 	/* last scan line before VSYNC */
299 	vfp_end = mode->crtc_vtotal;
300 
301 	if (stime)
302 		*stime = ktime_get();
303 
304 	line = dpu_encoder_get_linecount(encoder);
305 
306 	if (line < vactive_start)
307 		line -= vactive_start;
308 	else if (line > vactive_end)
309 		line = line - vfp_end - vactive_start;
310 	else
311 		line -= vactive_start;
312 
313 	*vpos = line;
314 	*hpos = 0;
315 
316 	if (etime)
317 		*etime = ktime_get();
318 
319 	return true;
320 }
321 
_dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer * mixer,struct dpu_plane_state * pstate,const struct msm_format * format)322 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
323 		struct dpu_plane_state *pstate, const struct msm_format *format)
324 {
325 	struct dpu_hw_mixer *lm = mixer->hw_lm;
326 	uint32_t blend_op;
327 	uint32_t fg_alpha, bg_alpha;
328 
329 	fg_alpha = pstate->base.alpha >> 8;
330 	bg_alpha = 0xff - fg_alpha;
331 
332 	/* default to opaque blending */
333 	if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
334 	    !format->alpha_enable) {
335 		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
336 			DPU_BLEND_BG_ALPHA_BG_CONST;
337 	} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
338 		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
339 			DPU_BLEND_BG_ALPHA_FG_PIXEL;
340 		if (fg_alpha != 0xff) {
341 			bg_alpha = fg_alpha;
342 			blend_op |= DPU_BLEND_BG_MOD_ALPHA |
343 				    DPU_BLEND_BG_INV_MOD_ALPHA;
344 		} else {
345 			blend_op |= DPU_BLEND_BG_INV_ALPHA;
346 		}
347 	} else {
348 		/* coverage blending */
349 		blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
350 			DPU_BLEND_BG_ALPHA_FG_PIXEL;
351 		if (fg_alpha != 0xff) {
352 			bg_alpha = fg_alpha;
353 			blend_op |= DPU_BLEND_FG_MOD_ALPHA |
354 				    DPU_BLEND_FG_INV_MOD_ALPHA |
355 				    DPU_BLEND_BG_MOD_ALPHA |
356 				    DPU_BLEND_BG_INV_MOD_ALPHA;
357 		} else {
358 			blend_op |= DPU_BLEND_BG_INV_ALPHA;
359 		}
360 	}
361 
362 	lm->ops.setup_blend_config(lm, pstate->stage,
363 				fg_alpha, bg_alpha, blend_op);
364 
365 	DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
366 		  &format->pixel_format, format->alpha_enable, blend_op);
367 }
368 
_dpu_crtc_program_lm_output_roi(struct drm_crtc * crtc)369 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
370 {
371 	struct dpu_crtc_state *crtc_state;
372 	int lm_idx, lm_horiz_position;
373 
374 	crtc_state = to_dpu_crtc_state(crtc->state);
375 
376 	lm_horiz_position = 0;
377 	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
378 		const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
379 		struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
380 		struct dpu_hw_mixer_cfg cfg;
381 
382 		if (!lm_roi || !drm_rect_visible(lm_roi))
383 			continue;
384 
385 		cfg.out_width = drm_rect_width(lm_roi);
386 		cfg.out_height = drm_rect_height(lm_roi);
387 		cfg.right_mixer = lm_horiz_position++;
388 		cfg.flags = 0;
389 		hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
390 	}
391 }
392 
_dpu_crtc_blend_setup_pipe(struct drm_crtc * crtc,struct drm_plane * plane,struct dpu_crtc_mixer * mixer,u32 num_mixers,enum dpu_stage stage,const struct msm_format * format,uint64_t modifier,struct dpu_sw_pipe * pipe,unsigned int stage_idx,struct dpu_hw_stage_cfg * stage_cfg)393 static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
394 				       struct drm_plane *plane,
395 				       struct dpu_crtc_mixer *mixer,
396 				       u32 num_mixers,
397 				       enum dpu_stage stage,
398 				       const struct msm_format *format,
399 				       uint64_t modifier,
400 				       struct dpu_sw_pipe *pipe,
401 				       unsigned int stage_idx,
402 				       struct dpu_hw_stage_cfg *stage_cfg
403 				      )
404 {
405 	uint32_t lm_idx;
406 	enum dpu_sspp sspp_idx;
407 	struct drm_plane_state *state;
408 
409 	sspp_idx = pipe->sspp->idx;
410 
411 	state = plane->state;
412 
413 	trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
414 				   state, to_dpu_plane_state(state), stage_idx,
415 				   format->pixel_format,
416 				   modifier);
417 
418 	DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
419 			 crtc->base.id,
420 			 stage,
421 			 plane->base.id,
422 			 sspp_idx - SSPP_NONE,
423 			 state->fb ? state->fb->base.id : -1,
424 			 pipe->multirect_index);
425 
426 	stage_cfg->stage[stage][stage_idx] = sspp_idx;
427 	stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;
428 
429 	/* blend config update */
430 	for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
431 		mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);
432 }
433 
_dpu_crtc_blend_setup_mixer(struct drm_crtc * crtc,struct dpu_crtc * dpu_crtc,struct dpu_crtc_mixer * mixer,struct dpu_hw_stage_cfg * stage_cfg)434 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
435 	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
436 	struct dpu_hw_stage_cfg *stage_cfg)
437 {
438 	struct drm_plane *plane;
439 	struct drm_framebuffer *fb;
440 	struct drm_plane_state *state;
441 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
442 	struct dpu_plane_state *pstate = NULL;
443 	const struct msm_format *format;
444 	struct dpu_hw_ctl *ctl = mixer->lm_ctl;
445 
446 	uint32_t lm_idx;
447 	bool bg_alpha_enable = false;
448 	DECLARE_BITMAP(fetch_active, SSPP_MAX);
449 
450 	memset(fetch_active, 0, sizeof(fetch_active));
451 	drm_atomic_crtc_for_each_plane(plane, crtc) {
452 		state = plane->state;
453 		if (!state)
454 			continue;
455 
456 		if (!state->visible)
457 			continue;
458 
459 		pstate = to_dpu_plane_state(state);
460 		fb = state->fb;
461 
462 		format = msm_framebuffer_format(pstate->base.fb);
463 
464 		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
465 			bg_alpha_enable = true;
466 
467 		set_bit(pstate->pipe.sspp->idx, fetch_active);
468 		_dpu_crtc_blend_setup_pipe(crtc, plane,
469 					   mixer, cstate->num_mixers,
470 					   pstate->stage,
471 					   format, fb ? fb->modifier : 0,
472 					   &pstate->pipe, 0, stage_cfg);
473 
474 		if (pstate->r_pipe.sspp) {
475 			set_bit(pstate->r_pipe.sspp->idx, fetch_active);
476 			_dpu_crtc_blend_setup_pipe(crtc, plane,
477 						   mixer, cstate->num_mixers,
478 						   pstate->stage,
479 						   format, fb ? fb->modifier : 0,
480 						   &pstate->r_pipe, 1, stage_cfg);
481 		}
482 
483 		/* blend config update */
484 		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
485 			_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
486 
487 			if (bg_alpha_enable && !format->alpha_enable)
488 				mixer[lm_idx].mixer_op_mode = 0;
489 			else
490 				mixer[lm_idx].mixer_op_mode |=
491 						1 << pstate->stage;
492 		}
493 	}
494 
495 	if (ctl->ops.set_active_pipes)
496 		ctl->ops.set_active_pipes(ctl, fetch_active);
497 
498 	_dpu_crtc_program_lm_output_roi(crtc);
499 }
500 
501 /**
502  * _dpu_crtc_blend_setup - configure crtc mixers
503  * @crtc: Pointer to drm crtc structure
504  */
_dpu_crtc_blend_setup(struct drm_crtc * crtc)505 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
506 {
507 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
508 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
509 	struct dpu_crtc_mixer *mixer = cstate->mixers;
510 	struct dpu_hw_ctl *ctl;
511 	struct dpu_hw_mixer *lm;
512 	struct dpu_hw_stage_cfg stage_cfg;
513 	int i;
514 
515 	DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
516 
517 	for (i = 0; i < cstate->num_mixers; i++) {
518 		mixer[i].mixer_op_mode = 0;
519 		if (mixer[i].lm_ctl->ops.clear_all_blendstages)
520 			mixer[i].lm_ctl->ops.clear_all_blendstages(
521 					mixer[i].lm_ctl);
522 	}
523 
524 	/* initialize stage cfg */
525 	memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
526 
527 	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
528 
529 	for (i = 0; i < cstate->num_mixers; i++) {
530 		ctl = mixer[i].lm_ctl;
531 		lm = mixer[i].hw_lm;
532 
533 		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
534 
535 		/* stage config flush mask */
536 		ctl->ops.update_pending_flush_mixer(ctl,
537 			mixer[i].hw_lm->idx);
538 
539 		DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n",
540 			mixer[i].hw_lm->idx - LM_0,
541 			mixer[i].mixer_op_mode,
542 			ctl->idx - CTL_0);
543 
544 		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
545 			&stage_cfg);
546 	}
547 }
548 
549 /**
550  *  _dpu_crtc_complete_flip - signal pending page_flip events
551  * Any pending vblank events are added to the vblank_event_list
552  * so that the next vblank interrupt shall signal them.
553  * However PAGE_FLIP events are not handled through the vblank_event_list.
554  * This API signals any pending PAGE_FLIP events requested through
555  * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event.
556  * @crtc: Pointer to drm crtc structure
557  */
_dpu_crtc_complete_flip(struct drm_crtc * crtc)558 static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
559 {
560 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
561 	struct drm_device *dev = crtc->dev;
562 	unsigned long flags;
563 
564 	spin_lock_irqsave(&dev->event_lock, flags);
565 	if (dpu_crtc->event) {
566 		DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name,
567 			      dpu_crtc->event);
568 		trace_dpu_crtc_complete_flip(DRMID(crtc));
569 		drm_crtc_send_vblank_event(crtc, dpu_crtc->event);
570 		dpu_crtc->event = NULL;
571 	}
572 	spin_unlock_irqrestore(&dev->event_lock, flags);
573 }
574 
575 /**
576  * dpu_crtc_get_intf_mode - get interface mode of the given crtc
577  * @crtc: Pointert to crtc
578  */
dpu_crtc_get_intf_mode(struct drm_crtc * crtc)579 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
580 {
581 	struct drm_encoder *encoder;
582 
583 	/*
584 	 * TODO: This function is called from dpu debugfs and as part of atomic
585 	 * check. When called from debugfs, the crtc->mutex must be held to
586 	 * read crtc->state. However reading crtc->state from atomic check isn't
587 	 * allowed (unless you have a good reason, a big comment, and a deep
588 	 * understanding of how the atomic/modeset locks work (<- and this is
589 	 * probably not possible)). So we'll keep the WARN_ON here for now, but
590 	 * really we need to figure out a better way to track our operating mode
591 	 */
592 	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
593 
594 	/* TODO: Returns the first INTF_MODE, could there be multiple values? */
595 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
596 		return dpu_encoder_get_intf_mode(encoder);
597 
598 	return INTF_MODE_NONE;
599 }
600 
601 /**
602  * dpu_crtc_vblank_callback - called on vblank irq, issues completion events
603  * @crtc: Pointer to drm crtc object
604  */
dpu_crtc_vblank_callback(struct drm_crtc * crtc)605 void dpu_crtc_vblank_callback(struct drm_crtc *crtc)
606 {
607 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
608 
609 	/* keep statistics on vblank callback - with auto reset via debugfs */
610 	if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
611 		dpu_crtc->vblank_cb_time = ktime_get();
612 	else
613 		dpu_crtc->vblank_cb_count++;
614 
615 	dpu_crtc_get_crc(crtc);
616 
617 	drm_crtc_handle_vblank(crtc);
618 	trace_dpu_crtc_vblank_cb(DRMID(crtc));
619 }
620 
dpu_crtc_frame_event_work(struct kthread_work * work)621 static void dpu_crtc_frame_event_work(struct kthread_work *work)
622 {
623 	struct dpu_crtc_frame_event *fevent = container_of(work,
624 			struct dpu_crtc_frame_event, work);
625 	struct drm_crtc *crtc = fevent->crtc;
626 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
627 	unsigned long flags;
628 	bool frame_done = false;
629 
630 	DPU_ATRACE_BEGIN("crtc_frame_event");
631 
632 	DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
633 			ktime_to_ns(fevent->ts));
634 
635 	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
636 				| DPU_ENCODER_FRAME_EVENT_ERROR
637 				| DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
638 
639 		if (atomic_read(&dpu_crtc->frame_pending) < 1) {
640 			/* ignore vblank when not pending */
641 		} else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) {
642 			/* release bandwidth and other resources */
643 			trace_dpu_crtc_frame_event_done(DRMID(crtc),
644 							fevent->event);
645 			dpu_core_perf_crtc_release_bw(crtc);
646 		} else {
647 			trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
648 								fevent->event);
649 		}
650 
651 		if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
652 					| DPU_ENCODER_FRAME_EVENT_ERROR))
653 			frame_done = true;
654 	}
655 
656 	if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)
657 		DPU_ERROR("crtc%d ts:%lld received panel dead event\n",
658 				crtc->base.id, ktime_to_ns(fevent->ts));
659 
660 	if (frame_done)
661 		complete_all(&dpu_crtc->frame_done_comp);
662 
663 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
664 	list_add_tail(&fevent->list, &dpu_crtc->frame_event_list);
665 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
666 	DPU_ATRACE_END("crtc_frame_event");
667 }
668 
669 /**
670  * dpu_crtc_frame_event_cb - crtc frame event callback API
671  * @crtc: Pointer to crtc
672  * @event: Event to process
673  *
674  * Encoder may call this for different events from different context - IRQ,
675  * user thread, commit_thread, etc. Each event should be carefully reviewed and
676  * should be processed in proper task context to avoid schedulin delay or
677  * properly manage the irq context's bottom half processing.
678  */
dpu_crtc_frame_event_cb(struct drm_crtc * crtc,u32 event)679 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event)
680 {
681 	struct dpu_crtc *dpu_crtc;
682 	struct msm_drm_private *priv;
683 	struct dpu_crtc_frame_event *fevent;
684 	unsigned long flags;
685 	u32 crtc_id;
686 
687 	/* Nothing to do on idle event */
688 	if (event & DPU_ENCODER_FRAME_EVENT_IDLE)
689 		return;
690 
691 	dpu_crtc = to_dpu_crtc(crtc);
692 	priv = crtc->dev->dev_private;
693 	crtc_id = drm_crtc_index(crtc);
694 
695 	trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
696 
697 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
698 	fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list,
699 			struct dpu_crtc_frame_event, list);
700 	if (fevent)
701 		list_del_init(&fevent->list);
702 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
703 
704 	if (!fevent) {
705 		DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event);
706 		return;
707 	}
708 
709 	fevent->event = event;
710 	fevent->crtc = crtc;
711 	fevent->ts = ktime_get();
712 	kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work);
713 }
714 
715 /**
716  * dpu_crtc_complete_commit - callback signalling completion of current commit
717  * @crtc: Pointer to drm crtc object
718  */
dpu_crtc_complete_commit(struct drm_crtc * crtc)719 void dpu_crtc_complete_commit(struct drm_crtc *crtc)
720 {
721 	trace_dpu_crtc_complete_commit(DRMID(crtc));
722 	dpu_core_perf_crtc_update(crtc, 0);
723 	_dpu_crtc_complete_flip(crtc);
724 }
725 
_dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc * crtc,struct drm_crtc_state * state)726 static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
727 		struct drm_crtc_state *state)
728 {
729 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
730 	struct drm_display_mode *adj_mode = &state->adjusted_mode;
731 	u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
732 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
733 	int i;
734 
735 	for (i = 0; i < cstate->num_mixers; i++) {
736 		struct drm_rect *r = &cstate->lm_bounds[i];
737 		r->x1 = crtc_split_width * i;
738 		r->y1 = 0;
739 		r->x2 = r->x1 + crtc_split_width;
740 		r->y2 = adj_mode->vdisplay;
741 
742 		trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
743 
744 		if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width)
745 			return -E2BIG;
746 	}
747 
748 	return 0;
749 }
750 
_dpu_crtc_get_pcc_coeff(struct drm_crtc_state * state,struct dpu_hw_pcc_cfg * cfg)751 static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state,
752 		struct dpu_hw_pcc_cfg *cfg)
753 {
754 	struct drm_color_ctm *ctm;
755 
756 	memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg));
757 
758 	ctm = (struct drm_color_ctm *)state->ctm->data;
759 
760 	if (!ctm)
761 		return;
762 
763 	cfg->r.r = CONVERT_S3_15(ctm->matrix[0]);
764 	cfg->g.r = CONVERT_S3_15(ctm->matrix[1]);
765 	cfg->b.r = CONVERT_S3_15(ctm->matrix[2]);
766 
767 	cfg->r.g = CONVERT_S3_15(ctm->matrix[3]);
768 	cfg->g.g = CONVERT_S3_15(ctm->matrix[4]);
769 	cfg->b.g = CONVERT_S3_15(ctm->matrix[5]);
770 
771 	cfg->r.b = CONVERT_S3_15(ctm->matrix[6]);
772 	cfg->g.b = CONVERT_S3_15(ctm->matrix[7]);
773 	cfg->b.b = CONVERT_S3_15(ctm->matrix[8]);
774 }
775 
_dpu_crtc_setup_cp_blocks(struct drm_crtc * crtc)776 static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
777 {
778 	struct drm_crtc_state *state = crtc->state;
779 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
780 	struct dpu_crtc_mixer *mixer = cstate->mixers;
781 	struct dpu_hw_pcc_cfg cfg;
782 	struct dpu_hw_ctl *ctl;
783 	struct dpu_hw_dspp *dspp;
784 	int i;
785 
786 
787 	if (!state->color_mgmt_changed && !drm_atomic_crtc_needs_modeset(state))
788 		return;
789 
790 	for (i = 0; i < cstate->num_mixers; i++) {
791 		ctl = mixer[i].lm_ctl;
792 		dspp = mixer[i].hw_dspp;
793 
794 		if (!dspp || !dspp->ops.setup_pcc)
795 			continue;
796 
797 		if (!state->ctm) {
798 			dspp->ops.setup_pcc(dspp, NULL);
799 		} else {
800 			_dpu_crtc_get_pcc_coeff(state, &cfg);
801 			dspp->ops.setup_pcc(dspp, &cfg);
802 		}
803 
804 		/* stage config flush mask */
805 		ctl->ops.update_pending_flush_dspp(ctl,
806 			mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
807 	}
808 }
809 
dpu_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)810 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
811 		struct drm_atomic_state *state)
812 {
813 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
814 	struct drm_encoder *encoder;
815 
816 	if (!crtc->state->enable) {
817 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
818 				crtc->base.id, crtc->state->enable);
819 		return;
820 	}
821 
822 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
823 
824 	_dpu_crtc_check_and_setup_lm_bounds(crtc, crtc->state);
825 
826 	/* encoder will trigger pending mask now */
827 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
828 		dpu_encoder_trigger_kickoff_pending(encoder);
829 
830 	/*
831 	 * If no mixers have been allocated in dpu_crtc_atomic_check(),
832 	 * it means we are trying to flush a CRTC whose state is disabled:
833 	 * nothing else needs to be done.
834 	 */
835 	if (unlikely(!cstate->num_mixers))
836 		return;
837 
838 	_dpu_crtc_blend_setup(crtc);
839 
840 	_dpu_crtc_setup_cp_blocks(crtc);
841 
842 	/*
843 	 * PP_DONE irq is only used by command mode for now.
844 	 * It is better to request pending before FLUSH and START trigger
845 	 * to make sure no pp_done irq missed.
846 	 * This is safe because no pp_done will happen before SW trigger
847 	 * in command mode.
848 	 */
849 }
850 
dpu_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)851 static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
852 		struct drm_atomic_state *state)
853 {
854 	struct dpu_crtc *dpu_crtc;
855 	struct drm_device *dev;
856 	struct drm_plane *plane;
857 	struct msm_drm_private *priv;
858 	unsigned long flags;
859 	struct dpu_crtc_state *cstate;
860 
861 	if (!crtc->state->enable) {
862 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
863 				crtc->base.id, crtc->state->enable);
864 		return;
865 	}
866 
867 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
868 
869 	dpu_crtc = to_dpu_crtc(crtc);
870 	cstate = to_dpu_crtc_state(crtc->state);
871 	dev = crtc->dev;
872 	priv = dev->dev_private;
873 
874 	if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
875 		DPU_ERROR("invalid crtc index[%d]\n", crtc->index);
876 		return;
877 	}
878 
879 	WARN_ON(dpu_crtc->event);
880 	spin_lock_irqsave(&dev->event_lock, flags);
881 	dpu_crtc->event = crtc->state->event;
882 	crtc->state->event = NULL;
883 	spin_unlock_irqrestore(&dev->event_lock, flags);
884 
885 	/*
886 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
887 	 * it means we are trying to flush a CRTC whose state is disabled:
888 	 * nothing else needs to be done.
889 	 */
890 	if (unlikely(!cstate->num_mixers))
891 		return;
892 
893 	/* update performance setting before crtc kickoff */
894 	dpu_core_perf_crtc_update(crtc, 1);
895 
896 	/*
897 	 * Final plane updates: Give each plane a chance to complete all
898 	 *                      required writes/flushing before crtc's "flush
899 	 *                      everything" call below.
900 	 */
901 	drm_atomic_crtc_for_each_plane(plane, crtc) {
902 		if (dpu_crtc->smmu_state.transition_error)
903 			dpu_plane_set_error(plane, true);
904 		dpu_plane_flush(plane);
905 	}
906 
907 	/* Kickoff will be scheduled by outer layer */
908 }
909 
910 /**
911  * dpu_crtc_destroy_state - state destroy hook
912  * @crtc: drm CRTC
913  * @state: CRTC state object to release
914  */
dpu_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)915 static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
916 		struct drm_crtc_state *state)
917 {
918 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
919 
920 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
921 
922 	__drm_atomic_helper_crtc_destroy_state(state);
923 
924 	kfree(cstate);
925 }
926 
_dpu_crtc_wait_for_frame_done(struct drm_crtc * crtc)927 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
928 {
929 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
930 	int ret, rc = 0;
931 
932 	if (!atomic_read(&dpu_crtc->frame_pending)) {
933 		DRM_DEBUG_ATOMIC("no frames pending\n");
934 		return 0;
935 	}
936 
937 	DPU_ATRACE_BEGIN("frame done completion wait");
938 	ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp,
939 			msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS));
940 	if (!ret) {
941 		DRM_ERROR("frame done wait timed out, ret:%d\n", ret);
942 		rc = -ETIMEDOUT;
943 	}
944 	DPU_ATRACE_END("frame done completion wait");
945 
946 	return rc;
947 }
948 
949 /**
950  * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc
951  * @crtc: Pointer to drm crtc object
952  */
dpu_crtc_commit_kickoff(struct drm_crtc * crtc)953 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
954 {
955 	struct drm_encoder *encoder;
956 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
957 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
958 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
959 
960 	/*
961 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
962 	 * it means we are trying to start a CRTC whose state is disabled:
963 	 * nothing else needs to be done.
964 	 */
965 	if (unlikely(!cstate->num_mixers))
966 		return;
967 
968 	DPU_ATRACE_BEGIN("crtc_commit");
969 
970 	drm_for_each_encoder_mask(encoder, crtc->dev,
971 			crtc->state->encoder_mask) {
972 		if (!dpu_encoder_is_valid_for_commit(encoder)) {
973 			DRM_DEBUG_ATOMIC("invalid FB not kicking off crtc\n");
974 			goto end;
975 		}
976 	}
977 	/*
978 	 * Encoder will flush/start now, unless it has a tx pending. If so, it
979 	 * may delay and flush at an irq event (e.g. ppdone)
980 	 */
981 	drm_for_each_encoder_mask(encoder, crtc->dev,
982 				  crtc->state->encoder_mask)
983 		dpu_encoder_prepare_for_kickoff(encoder);
984 
985 	if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
986 		/* acquire bandwidth and other resources */
987 		DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
988 	} else
989 		DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
990 
991 	dpu_crtc->play_count++;
992 
993 	dpu_vbif_clear_errors(dpu_kms);
994 
995 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
996 		dpu_encoder_kickoff(encoder);
997 
998 	reinit_completion(&dpu_crtc->frame_done_comp);
999 
1000 end:
1001 	DPU_ATRACE_END("crtc_commit");
1002 }
1003 
dpu_crtc_reset(struct drm_crtc * crtc)1004 static void dpu_crtc_reset(struct drm_crtc *crtc)
1005 {
1006 	struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
1007 
1008 	if (crtc->state)
1009 		dpu_crtc_destroy_state(crtc, crtc->state);
1010 
1011 	if (cstate)
1012 		__drm_atomic_helper_crtc_reset(crtc, &cstate->base);
1013 	else
1014 		__drm_atomic_helper_crtc_reset(crtc, NULL);
1015 }
1016 
1017 /**
1018  * dpu_crtc_duplicate_state - state duplicate hook
1019  * @crtc: Pointer to drm crtc structure
1020  */
dpu_crtc_duplicate_state(struct drm_crtc * crtc)1021 static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
1022 {
1023 	struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state);
1024 
1025 	cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
1026 	if (!cstate) {
1027 		DPU_ERROR("failed to allocate state\n");
1028 		return NULL;
1029 	}
1030 
1031 	/* duplicate base helper */
1032 	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
1033 
1034 	return &cstate->base;
1035 }
1036 
dpu_crtc_atomic_print_state(struct drm_printer * p,const struct drm_crtc_state * state)1037 static void dpu_crtc_atomic_print_state(struct drm_printer *p,
1038 					const struct drm_crtc_state *state)
1039 {
1040 	const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
1041 	int i;
1042 
1043 	for (i = 0; i < cstate->num_mixers; i++) {
1044 		drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0);
1045 		drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0);
1046 		if (cstate->mixers[i].hw_dspp)
1047 			drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0);
1048 	}
1049 }
1050 
dpu_crtc_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)1051 static void dpu_crtc_disable(struct drm_crtc *crtc,
1052 			     struct drm_atomic_state *state)
1053 {
1054 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1055 									      crtc);
1056 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1057 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
1058 	struct drm_encoder *encoder;
1059 	unsigned long flags;
1060 	bool release_bandwidth = false;
1061 
1062 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
1063 
1064 	/* If disable is triggered while in self refresh mode,
1065 	 * reset the encoder software state so that in enable
1066 	 * it won't trigger a warn while assigning crtc.
1067 	 */
1068 	if (old_crtc_state->self_refresh_active) {
1069 		drm_for_each_encoder_mask(encoder, crtc->dev,
1070 					old_crtc_state->encoder_mask) {
1071 			dpu_encoder_assign_crtc(encoder, NULL);
1072 		}
1073 		return;
1074 	}
1075 
1076 	/* Disable/save vblank irq handling */
1077 	drm_crtc_vblank_off(crtc);
1078 
1079 	drm_for_each_encoder_mask(encoder, crtc->dev,
1080 				  old_crtc_state->encoder_mask) {
1081 		/* in video mode, we hold an extra bandwidth reference
1082 		 * as we cannot drop bandwidth at frame-done if any
1083 		 * crtc is being used in video mode.
1084 		 */
1085 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1086 			release_bandwidth = true;
1087 
1088 		/*
1089 		 * If disable is triggered during psr active(e.g: screen dim in PSR),
1090 		 * we will need encoder->crtc connection to process the device sleep &
1091 		 * preserve it during psr sequence.
1092 		 */
1093 		if (!crtc->state->self_refresh_active)
1094 			dpu_encoder_assign_crtc(encoder, NULL);
1095 	}
1096 
1097 	/* wait for frame_event_done completion */
1098 	if (_dpu_crtc_wait_for_frame_done(crtc))
1099 		DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
1100 				crtc->base.id,
1101 				atomic_read(&dpu_crtc->frame_pending));
1102 
1103 	trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
1104 	dpu_crtc->enabled = false;
1105 
1106 	if (atomic_read(&dpu_crtc->frame_pending)) {
1107 		trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
1108 				     atomic_read(&dpu_crtc->frame_pending));
1109 		if (release_bandwidth)
1110 			dpu_core_perf_crtc_release_bw(crtc);
1111 		atomic_set(&dpu_crtc->frame_pending, 0);
1112 	}
1113 
1114 	dpu_core_perf_crtc_update(crtc, 0);
1115 
1116 	/* disable clk & bw control until clk & bw properties are set */
1117 	cstate->bw_control = false;
1118 	cstate->bw_split_vote = false;
1119 
1120 	if (crtc->state->event && !crtc->state->active) {
1121 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
1122 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
1123 		crtc->state->event = NULL;
1124 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1125 	}
1126 
1127 	pm_runtime_put_sync(crtc->dev->dev);
1128 }
1129 
dpu_crtc_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1130 static void dpu_crtc_enable(struct drm_crtc *crtc,
1131 		struct drm_atomic_state *state)
1132 {
1133 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1134 	struct drm_encoder *encoder;
1135 	bool request_bandwidth = false;
1136 	struct drm_crtc_state *old_crtc_state;
1137 
1138 	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1139 
1140 	pm_runtime_get_sync(crtc->dev->dev);
1141 
1142 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
1143 
1144 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
1145 		/* in video mode, we hold an extra bandwidth reference
1146 		 * as we cannot drop bandwidth at frame-done if any
1147 		 * crtc is being used in video mode.
1148 		 */
1149 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1150 			request_bandwidth = true;
1151 	}
1152 
1153 	if (request_bandwidth)
1154 		atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1155 
1156 	trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
1157 	dpu_crtc->enabled = true;
1158 
1159 	if (!old_crtc_state->self_refresh_active) {
1160 		drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
1161 			dpu_encoder_assign_crtc(encoder, crtc);
1162 	}
1163 
1164 	/* Enable/restore vblank irq handling */
1165 	drm_crtc_vblank_on(crtc);
1166 }
1167 
dpu_crtc_needs_dirtyfb(struct drm_crtc_state * cstate)1168 static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
1169 {
1170 	struct drm_crtc *crtc = cstate->crtc;
1171 	struct drm_encoder *encoder;
1172 
1173 	if (cstate->self_refresh_active)
1174 		return true;
1175 
1176 	drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) {
1177 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) {
1178 			return true;
1179 		}
1180 	}
1181 
1182 	return false;
1183 }
1184 
dpu_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1185 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
1186 		struct drm_atomic_state *state)
1187 {
1188 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1189 									  crtc);
1190 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1191 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
1192 
1193 	const struct drm_plane_state *pstate;
1194 	struct drm_plane *plane;
1195 
1196 	int rc = 0;
1197 
1198 	bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
1199 
1200 	if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) {
1201 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
1202 				crtc->base.id, crtc_state->enable,
1203 				crtc_state->active);
1204 		memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
1205 		return 0;
1206 	}
1207 
1208 	DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
1209 
1210 	/* force a full mode set if active state changed */
1211 	if (crtc_state->active_changed)
1212 		crtc_state->mode_changed = true;
1213 
1214 	if (cstate->num_mixers) {
1215 		rc = _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc_state);
1216 		if (rc)
1217 			return rc;
1218 	}
1219 
1220 	/* FIXME: move this to dpu_plane_atomic_check? */
1221 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
1222 		struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
1223 
1224 		if (IS_ERR_OR_NULL(pstate)) {
1225 			rc = PTR_ERR(pstate);
1226 			DPU_ERROR("%s: failed to get plane%d state, %d\n",
1227 					dpu_crtc->name, plane->base.id, rc);
1228 			return rc;
1229 		}
1230 
1231 		if (!pstate->visible)
1232 			continue;
1233 
1234 		dpu_pstate->needs_dirtyfb = needs_dirtyfb;
1235 	}
1236 
1237 	atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1238 
1239 	rc = dpu_core_perf_crtc_check(crtc, crtc_state);
1240 	if (rc) {
1241 		DPU_ERROR("crtc%d failed performance check %d\n",
1242 				crtc->base.id, rc);
1243 		return rc;
1244 	}
1245 
1246 	return 0;
1247 }
1248 
dpu_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)1249 static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
1250 						const struct drm_display_mode *mode)
1251 {
1252 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
1253 
1254 	/*
1255 	 * max crtc width is equal to the max mixer width * 2 and max height is 4K
1256 	 */
1257 	return drm_mode_validate_size(mode,
1258 				      2 * dpu_kms->catalog->caps->max_mixer_width,
1259 				      4096);
1260 }
1261 
1262 /**
1263  * dpu_crtc_vblank - enable or disable vblanks for this crtc
1264  * @crtc: Pointer to drm crtc object
1265  * @en: true to enable vblanks, false to disable
1266  */
dpu_crtc_vblank(struct drm_crtc * crtc,bool en)1267 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
1268 {
1269 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1270 	struct drm_encoder *enc;
1271 
1272 	trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
1273 
1274 	/*
1275 	 * Normally we would iterate through encoder_mask in crtc state to find
1276 	 * attached encoders. In this case, we might be disabling vblank _after_
1277 	 * encoder_mask has been cleared.
1278 	 *
1279 	 * Instead, we "assign" a crtc to the encoder in enable and clear it in
1280 	 * disable (which is also after encoder_mask is cleared). So instead of
1281 	 * using encoder mask, we'll ask the encoder to toggle itself iff it's
1282 	 * currently assigned to our crtc.
1283 	 *
1284 	 * Note also that this function cannot be called while crtc is disabled
1285 	 * since we use drm_crtc_vblank_on/off. So we don't need to worry
1286 	 * about the assigned crtcs being inconsistent with the current state
1287 	 * (which means no need to worry about modeset locks).
1288 	 */
1289 	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
1290 		trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en,
1291 					     dpu_crtc);
1292 
1293 		dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en);
1294 	}
1295 
1296 	return 0;
1297 }
1298 
1299 #ifdef CONFIG_DEBUG_FS
_dpu_debugfs_status_show(struct seq_file * s,void * data)1300 static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
1301 {
1302 	struct dpu_crtc *dpu_crtc;
1303 	struct dpu_plane_state *pstate = NULL;
1304 	struct dpu_crtc_mixer *m;
1305 
1306 	struct drm_crtc *crtc;
1307 	struct drm_plane *plane;
1308 	struct drm_display_mode *mode;
1309 	struct drm_framebuffer *fb;
1310 	struct drm_plane_state *state;
1311 	struct dpu_crtc_state *cstate;
1312 
1313 	int i, out_width;
1314 
1315 	dpu_crtc = s->private;
1316 	crtc = &dpu_crtc->base;
1317 
1318 	drm_modeset_lock_all(crtc->dev);
1319 	cstate = to_dpu_crtc_state(crtc->state);
1320 
1321 	mode = &crtc->state->adjusted_mode;
1322 	out_width = mode->hdisplay / cstate->num_mixers;
1323 
1324 	seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
1325 				mode->hdisplay, mode->vdisplay);
1326 
1327 	seq_puts(s, "\n");
1328 
1329 	for (i = 0; i < cstate->num_mixers; ++i) {
1330 		m = &cstate->mixers[i];
1331 		seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
1332 			m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
1333 			out_width, mode->vdisplay);
1334 	}
1335 
1336 	seq_puts(s, "\n");
1337 
1338 	drm_atomic_crtc_for_each_plane(plane, crtc) {
1339 		pstate = to_dpu_plane_state(plane->state);
1340 		state = plane->state;
1341 
1342 		if (!pstate || !state)
1343 			continue;
1344 
1345 		seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
1346 			pstate->stage);
1347 
1348 		if (plane->state->fb) {
1349 			fb = plane->state->fb;
1350 
1351 			seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
1352 				fb->base.id, (char *) &fb->format->format,
1353 				fb->width, fb->height);
1354 			for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
1355 				seq_printf(s, "cpp[%d]:%u ",
1356 						i, fb->format->cpp[i]);
1357 			seq_puts(s, "\n\t");
1358 
1359 			seq_printf(s, "modifier:%8llu ", fb->modifier);
1360 			seq_puts(s, "\n");
1361 
1362 			seq_puts(s, "\t");
1363 			for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
1364 				seq_printf(s, "pitches[%d]:%8u ", i,
1365 							fb->pitches[i]);
1366 			seq_puts(s, "\n");
1367 
1368 			seq_puts(s, "\t");
1369 			for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
1370 				seq_printf(s, "offsets[%d]:%8u ", i,
1371 							fb->offsets[i]);
1372 			seq_puts(s, "\n");
1373 		}
1374 
1375 		seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
1376 			state->src_x, state->src_y, state->src_w, state->src_h);
1377 
1378 		seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
1379 			state->crtc_x, state->crtc_y, state->crtc_w,
1380 			state->crtc_h);
1381 		seq_printf(s, "\tsspp[0]:%s\n",
1382 			   pstate->pipe.sspp->cap->name);
1383 		seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
1384 			pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
1385 		if (pstate->r_pipe.sspp) {
1386 			seq_printf(s, "\tsspp[1]:%s\n",
1387 				   pstate->r_pipe.sspp->cap->name);
1388 			seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
1389 				   pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
1390 		}
1391 
1392 		seq_puts(s, "\n");
1393 	}
1394 	if (dpu_crtc->vblank_cb_count) {
1395 		ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time);
1396 		s64 diff_ms = ktime_to_ms(diff);
1397 		s64 fps = diff_ms ? div_s64(
1398 				dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0;
1399 
1400 		seq_printf(s,
1401 			"vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
1402 				fps, dpu_crtc->vblank_cb_count,
1403 				ktime_to_ms(diff), dpu_crtc->play_count);
1404 
1405 		/* reset time & count for next measurement */
1406 		dpu_crtc->vblank_cb_count = 0;
1407 		dpu_crtc->vblank_cb_time = ktime_set(0, 0);
1408 	}
1409 
1410 	drm_modeset_unlock_all(crtc->dev);
1411 
1412 	return 0;
1413 }
1414 
1415 DEFINE_SHOW_ATTRIBUTE(_dpu_debugfs_status);
1416 
dpu_crtc_debugfs_state_show(struct seq_file * s,void * v)1417 static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
1418 {
1419 	struct drm_crtc *crtc = s->private;
1420 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1421 
1422 	seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
1423 	seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
1424 	seq_printf(s, "core_clk_rate: %llu\n",
1425 			dpu_crtc->cur_perf.core_clk_rate);
1426 	seq_printf(s, "bw_ctl: %llu\n", dpu_crtc->cur_perf.bw_ctl);
1427 	seq_printf(s, "max_per_pipe_ib: %llu\n",
1428 				dpu_crtc->cur_perf.max_per_pipe_ib);
1429 
1430 	return 0;
1431 }
1432 DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state);
1433 
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)1434 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1435 {
1436 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1437 
1438 	debugfs_create_file("status", 0400,
1439 			crtc->debugfs_entry,
1440 			dpu_crtc, &_dpu_debugfs_status_fops);
1441 	debugfs_create_file("state", 0600,
1442 			crtc->debugfs_entry,
1443 			&dpu_crtc->base,
1444 			&dpu_crtc_debugfs_state_fops);
1445 
1446 	return 0;
1447 }
1448 #else
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)1449 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1450 {
1451 	return 0;
1452 }
1453 #endif /* CONFIG_DEBUG_FS */
1454 
dpu_crtc_late_register(struct drm_crtc * crtc)1455 static int dpu_crtc_late_register(struct drm_crtc *crtc)
1456 {
1457 	return _dpu_crtc_init_debugfs(crtc);
1458 }
1459 
1460 static const struct drm_crtc_funcs dpu_crtc_funcs = {
1461 	.set_config = drm_atomic_helper_set_config,
1462 	.page_flip = drm_atomic_helper_page_flip,
1463 	.reset = dpu_crtc_reset,
1464 	.atomic_duplicate_state = dpu_crtc_duplicate_state,
1465 	.atomic_destroy_state = dpu_crtc_destroy_state,
1466 	.atomic_print_state = dpu_crtc_atomic_print_state,
1467 	.late_register = dpu_crtc_late_register,
1468 	.verify_crc_source = dpu_crtc_verify_crc_source,
1469 	.set_crc_source = dpu_crtc_set_crc_source,
1470 	.enable_vblank  = msm_crtc_enable_vblank,
1471 	.disable_vblank = msm_crtc_disable_vblank,
1472 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1473 	.get_vblank_counter = dpu_crtc_get_vblank_counter,
1474 };
1475 
1476 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
1477 	.atomic_disable = dpu_crtc_disable,
1478 	.atomic_enable = dpu_crtc_enable,
1479 	.atomic_check = dpu_crtc_atomic_check,
1480 	.atomic_begin = dpu_crtc_atomic_begin,
1481 	.atomic_flush = dpu_crtc_atomic_flush,
1482 	.mode_valid = dpu_crtc_mode_valid,
1483 	.get_scanout_position = dpu_crtc_get_scanout_position,
1484 };
1485 
1486 /**
1487  * dpu_crtc_init - create a new crtc object
1488  * @dev: dpu device
1489  * @plane: base plane
1490  * @cursor: cursor plane
1491  * @return: new crtc object or error
1492  *
1493  * initialize CRTC
1494  */
dpu_crtc_init(struct drm_device * dev,struct drm_plane * plane,struct drm_plane * cursor)1495 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
1496 				struct drm_plane *cursor)
1497 {
1498 	struct msm_drm_private *priv = dev->dev_private;
1499 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1500 	struct drm_crtc *crtc = NULL;
1501 	struct dpu_crtc *dpu_crtc;
1502 	int i, ret;
1503 
1504 	dpu_crtc = drmm_crtc_alloc_with_planes(dev, struct dpu_crtc, base,
1505 					       plane, cursor,
1506 					       &dpu_crtc_funcs,
1507 					       NULL);
1508 
1509 	if (IS_ERR(dpu_crtc))
1510 		return ERR_CAST(dpu_crtc);
1511 
1512 	crtc = &dpu_crtc->base;
1513 	crtc->dev = dev;
1514 
1515 	spin_lock_init(&dpu_crtc->spin_lock);
1516 	atomic_set(&dpu_crtc->frame_pending, 0);
1517 
1518 	init_completion(&dpu_crtc->frame_done_comp);
1519 
1520 	INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
1521 
1522 	for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
1523 		INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
1524 		list_add(&dpu_crtc->frame_events[i].list,
1525 				&dpu_crtc->frame_event_list);
1526 		kthread_init_work(&dpu_crtc->frame_events[i].work,
1527 				dpu_crtc_frame_event_work);
1528 	}
1529 
1530 	drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
1531 
1532 	if (dpu_kms->catalog->dspp_count)
1533 		drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
1534 
1535 	/* save user friendly CRTC name for later */
1536 	snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
1537 
1538 	/* initialize event handling */
1539 	spin_lock_init(&dpu_crtc->event_lock);
1540 
1541 	ret = drm_self_refresh_helper_init(crtc);
1542 	if (ret) {
1543 		DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
1544 			crtc->name, ret);
1545 		return ERR_PTR(ret);
1546 	}
1547 
1548 	DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
1549 	return crtc;
1550 }
1551