1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2014-2016 Freescale Semiconductor Inc. 4 * Copyright 2017-2021 NXP 5 * 6 */ 7 8 #ifndef __FSL_DPSW_CMD_H 9 #define __FSL_DPSW_CMD_H 10 11 #include "dpsw.h" 12 13 /* DPSW Version */ 14 #define DPSW_VER_MAJOR 8 15 #define DPSW_VER_MINOR 13 16 17 #define DPSW_CMD_BASE_VERSION 1 18 #define DPSW_CMD_VERSION_2 2 19 #define DPSW_CMD_ID_OFFSET 4 20 21 #define DPSW_CMD_ID(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_BASE_VERSION) 22 #define DPSW_CMD_V2(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_VERSION_2) 23 24 /* Command IDs */ 25 #define DPSW_CMDID_CLOSE DPSW_CMD_ID(0x800) 26 #define DPSW_CMDID_OPEN DPSW_CMD_ID(0x802) 27 28 #define DPSW_CMDID_GET_API_VERSION DPSW_CMD_ID(0xa02) 29 30 #define DPSW_CMDID_ENABLE DPSW_CMD_ID(0x002) 31 #define DPSW_CMDID_DISABLE DPSW_CMD_ID(0x003) 32 #define DPSW_CMDID_GET_ATTR DPSW_CMD_V2(0x004) 33 #define DPSW_CMDID_RESET DPSW_CMD_ID(0x005) 34 35 #define DPSW_CMDID_SET_IRQ_ENABLE DPSW_CMD_ID(0x012) 36 37 #define DPSW_CMDID_SET_IRQ_MASK DPSW_CMD_ID(0x014) 38 39 #define DPSW_CMDID_GET_IRQ_STATUS DPSW_CMD_ID(0x016) 40 #define DPSW_CMDID_CLEAR_IRQ_STATUS DPSW_CMD_ID(0x017) 41 42 #define DPSW_CMDID_SET_REFLECTION_IF DPSW_CMD_ID(0x022) 43 44 #define DPSW_CMDID_IF_SET_TCI DPSW_CMD_ID(0x030) 45 #define DPSW_CMDID_IF_SET_STP DPSW_CMD_ID(0x031) 46 47 #define DPSW_CMDID_IF_GET_COUNTER DPSW_CMD_V2(0x034) 48 49 #define DPSW_CMDID_IF_ADD_REFLECTION DPSW_CMD_ID(0x037) 50 #define DPSW_CMDID_IF_REMOVE_REFLECTION DPSW_CMD_ID(0x038) 51 52 #define DPSW_CMDID_IF_ENABLE DPSW_CMD_ID(0x03D) 53 #define DPSW_CMDID_IF_DISABLE DPSW_CMD_ID(0x03E) 54 55 #define DPSW_CMDID_IF_GET_ATTR DPSW_CMD_ID(0x042) 56 57 #define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH DPSW_CMD_ID(0x044) 58 59 #define DPSW_CMDID_IF_GET_LINK_STATE DPSW_CMD_ID(0x046) 60 61 #define DPSW_CMDID_IF_GET_TCI DPSW_CMD_ID(0x04A) 62 63 #define DPSW_CMDID_IF_SET_LINK_CFG DPSW_CMD_ID(0x04C) 64 65 #define DPSW_CMDID_VLAN_ADD DPSW_CMD_ID(0x060) 66 #define DPSW_CMDID_VLAN_ADD_IF DPSW_CMD_V2(0x061) 67 #define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED DPSW_CMD_ID(0x062) 68 69 #define DPSW_CMDID_VLAN_REMOVE_IF DPSW_CMD_ID(0x064) 70 #define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED DPSW_CMD_ID(0x065) 71 #define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING DPSW_CMD_ID(0x066) 72 #define DPSW_CMDID_VLAN_REMOVE DPSW_CMD_ID(0x067) 73 74 #define DPSW_CMDID_FDB_ADD DPSW_CMD_ID(0x082) 75 #define DPSW_CMDID_FDB_REMOVE DPSW_CMD_ID(0x083) 76 #define DPSW_CMDID_FDB_ADD_UNICAST DPSW_CMD_ID(0x084) 77 #define DPSW_CMDID_FDB_REMOVE_UNICAST DPSW_CMD_ID(0x085) 78 #define DPSW_CMDID_FDB_ADD_MULTICAST DPSW_CMD_ID(0x086) 79 #define DPSW_CMDID_FDB_REMOVE_MULTICAST DPSW_CMD_ID(0x087) 80 #define DPSW_CMDID_FDB_DUMP DPSW_CMD_ID(0x08A) 81 82 #define DPSW_CMDID_ACL_ADD DPSW_CMD_ID(0x090) 83 #define DPSW_CMDID_ACL_REMOVE DPSW_CMD_ID(0x091) 84 #define DPSW_CMDID_ACL_ADD_ENTRY DPSW_CMD_ID(0x092) 85 #define DPSW_CMDID_ACL_REMOVE_ENTRY DPSW_CMD_ID(0x093) 86 #define DPSW_CMDID_ACL_ADD_IF DPSW_CMD_ID(0x094) 87 #define DPSW_CMDID_ACL_REMOVE_IF DPSW_CMD_ID(0x095) 88 89 #define DPSW_CMDID_IF_GET_PORT_MAC_ADDR DPSW_CMD_ID(0x0A7) 90 91 #define DPSW_CMDID_CTRL_IF_GET_ATTR DPSW_CMD_ID(0x0A0) 92 #define DPSW_CMDID_CTRL_IF_SET_POOLS DPSW_CMD_ID(0x0A1) 93 #define DPSW_CMDID_CTRL_IF_ENABLE DPSW_CMD_ID(0x0A2) 94 #define DPSW_CMDID_CTRL_IF_DISABLE DPSW_CMD_ID(0x0A3) 95 #define DPSW_CMDID_SET_LAG DPSW_CMD_V2(0x0A4) 96 #define DPSW_CMDID_CTRL_IF_SET_QUEUE DPSW_CMD_ID(0x0A6) 97 98 #define DPSW_CMDID_SET_EGRESS_FLOOD DPSW_CMD_ID(0x0AC) 99 #define DPSW_CMDID_IF_SET_LEARNING_MODE DPSW_CMD_ID(0x0AD) 100 101 #define DPSW_CMDID_IF_SET_LAG_STATE DPSW_CMD_ID(0x0B0) 102 103 /* Macros for accessing command fields smaller than 1byte */ 104 #define DPSW_MASK(field) \ 105 GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \ 106 DPSW_##field##_SHIFT) 107 #define dpsw_set_field(var, field, val) \ 108 ((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field))) 109 #define dpsw_get_field(var, field) \ 110 (((var) & DPSW_MASK(field)) >> DPSW_##field##_SHIFT) 111 #define dpsw_get_bit(var, bit) \ 112 (((var) >> (bit)) & GENMASK(0, 0)) 113 114 #pragma pack(push, 1) 115 struct dpsw_cmd_open { 116 __le32 dpsw_id; 117 }; 118 119 #define DPSW_COMPONENT_TYPE_SHIFT 0 120 #define DPSW_COMPONENT_TYPE_SIZE 4 121 122 struct dpsw_cmd_create { 123 /* cmd word 0 */ 124 __le16 num_ifs; 125 u8 max_fdbs; 126 u8 max_meters_per_if; 127 /* from LSB: only the first 4 bits */ 128 u8 component_type; 129 u8 pad[3]; 130 /* cmd word 1 */ 131 __le16 max_vlans; 132 __le16 max_fdb_entries; 133 __le16 fdb_aging_time; 134 __le16 max_fdb_mc_groups; 135 /* cmd word 2 */ 136 __le64 options; 137 }; 138 139 struct dpsw_cmd_destroy { 140 __le32 dpsw_id; 141 }; 142 143 #define DPSW_ENABLE_SHIFT 0 144 #define DPSW_ENABLE_SIZE 1 145 146 struct dpsw_rsp_is_enabled { 147 /* from LSB: enable:1 */ 148 u8 enabled; 149 }; 150 151 struct dpsw_cmd_set_irq_enable { 152 u8 enable_state; 153 u8 pad[3]; 154 u8 irq_index; 155 }; 156 157 struct dpsw_cmd_get_irq_enable { 158 __le32 pad; 159 u8 irq_index; 160 }; 161 162 struct dpsw_rsp_get_irq_enable { 163 u8 enable_state; 164 }; 165 166 struct dpsw_cmd_set_irq_mask { 167 __le32 mask; 168 u8 irq_index; 169 }; 170 171 struct dpsw_cmd_get_irq_mask { 172 __le32 pad; 173 u8 irq_index; 174 }; 175 176 struct dpsw_rsp_get_irq_mask { 177 __le32 mask; 178 }; 179 180 struct dpsw_cmd_get_irq_status { 181 __le32 status; 182 u8 irq_index; 183 }; 184 185 struct dpsw_rsp_get_irq_status { 186 __le32 status; 187 }; 188 189 struct dpsw_cmd_clear_irq_status { 190 __le32 status; 191 u8 irq_index; 192 }; 193 194 #define DPSW_COMPONENT_TYPE_SHIFT 0 195 #define DPSW_COMPONENT_TYPE_SIZE 4 196 197 #define DPSW_FLOODING_CFG_SHIFT 0 198 #define DPSW_FLOODING_CFG_SIZE 4 199 200 #define DPSW_BROADCAST_CFG_SHIFT 4 201 #define DPSW_BROADCAST_CFG_SIZE 4 202 203 struct dpsw_rsp_get_attr { 204 /* cmd word 0 */ 205 __le16 num_ifs; 206 u8 max_fdbs; 207 u8 num_fdbs; 208 __le16 max_vlans; 209 __le16 num_vlans; 210 /* cmd word 1 */ 211 __le16 max_fdb_entries; 212 __le16 fdb_aging_time; 213 __le32 dpsw_id; 214 /* cmd word 2 */ 215 __le16 mem_size; 216 __le16 max_fdb_mc_groups; 217 u8 max_meters_per_if; 218 /* from LSB only the first 4 bits */ 219 u8 component_type; 220 /* [0:3] - flooding configuration 221 * [4:7] - broadcast configuration 222 */ 223 u8 repl_cfg; 224 u8 pad; 225 /* cmd word 3 */ 226 __le64 options; 227 }; 228 229 #define DPSW_VLAN_ID_SHIFT 0 230 #define DPSW_VLAN_ID_SIZE 12 231 #define DPSW_DEI_SHIFT 12 232 #define DPSW_DEI_SIZE 1 233 #define DPSW_PCP_SHIFT 13 234 #define DPSW_PCP_SIZE 3 235 236 struct dpsw_cmd_if_set_tci { 237 __le16 if_id; 238 /* from LSB: VLAN_ID:12 DEI:1 PCP:3 */ 239 __le16 conf; 240 }; 241 242 struct dpsw_cmd_if_get_tci { 243 __le16 if_id; 244 }; 245 246 struct dpsw_rsp_if_get_tci { 247 __le16 pad; 248 __le16 vlan_id; 249 u8 dei; 250 u8 pcp; 251 }; 252 253 #define DPSW_STATE_SHIFT 0 254 #define DPSW_STATE_SIZE 4 255 256 struct dpsw_cmd_if_set_stp { 257 __le16 if_id; 258 __le16 vlan_id; 259 /* only the first LSB 4 bits */ 260 u8 state; 261 }; 262 263 #define DPSW_COUNTER_TYPE_SHIFT 0 264 #define DPSW_COUNTER_TYPE_SIZE 5 265 266 struct dpsw_cmd_if_get_counter { 267 __le16 if_id; 268 /* from LSB: type:5 */ 269 u8 type; 270 }; 271 272 struct dpsw_rsp_if_get_counter { 273 __le64 pad; 274 __le64 counter; 275 }; 276 277 struct dpsw_cmd_if { 278 __le16 if_id; 279 }; 280 281 #define DPSW_ADMIT_UNTAGGED_SHIFT 0 282 #define DPSW_ADMIT_UNTAGGED_SIZE 4 283 #define DPSW_ENABLED_SHIFT 5 284 #define DPSW_ENABLED_SIZE 1 285 #define DPSW_ACCEPT_ALL_VLAN_SHIFT 6 286 #define DPSW_ACCEPT_ALL_VLAN_SIZE 1 287 288 struct dpsw_rsp_if_get_attr { 289 /* cmd word 0 */ 290 /* from LSB: admit_untagged:4 enabled:1 accept_all_vlan:1 */ 291 u8 conf; 292 u8 pad1; 293 u8 num_tcs; 294 u8 pad2; 295 __le16 qdid; 296 /* cmd word 1 */ 297 __le32 options; 298 __le32 pad3; 299 /* cmd word 2 */ 300 __le32 rate; 301 }; 302 303 struct dpsw_cmd_if_set_max_frame_length { 304 __le16 if_id; 305 __le16 frame_length; 306 }; 307 308 struct dpsw_cmd_if_set_link_cfg { 309 /* cmd word 0 */ 310 __le16 if_id; 311 u8 pad[6]; 312 /* cmd word 1 */ 313 __le32 rate; 314 __le32 pad1; 315 /* cmd word 2 */ 316 __le64 options; 317 }; 318 319 struct dpsw_cmd_if_get_link_state { 320 __le16 if_id; 321 }; 322 323 #define DPSW_UP_SHIFT 0 324 #define DPSW_UP_SIZE 1 325 326 struct dpsw_rsp_if_get_link_state { 327 /* cmd word 0 */ 328 __le32 pad0; 329 u8 up; 330 u8 pad1[3]; 331 /* cmd word 1 */ 332 __le32 rate; 333 __le32 pad2; 334 /* cmd word 2 */ 335 __le64 options; 336 }; 337 338 struct dpsw_vlan_add { 339 __le16 fdb_id; 340 __le16 vlan_id; 341 }; 342 343 struct dpsw_cmd_vlan_add_if { 344 /* cmd word 0 */ 345 __le16 options; 346 __le16 vlan_id; 347 __le16 fdb_id; 348 __le16 pad0; 349 /* cmd word 1-4 */ 350 __le64 if_id; 351 }; 352 353 struct dpsw_cmd_vlan_manage_if { 354 /* cmd word 0 */ 355 __le16 pad0; 356 __le16 vlan_id; 357 __le32 pad1; 358 /* cmd word 1-4 */ 359 __le64 if_id; 360 }; 361 362 struct dpsw_cmd_vlan_remove { 363 __le16 pad; 364 __le16 vlan_id; 365 }; 366 367 struct dpsw_cmd_fdb_add { 368 __le32 pad; 369 __le16 fdb_ageing_time; 370 __le16 num_fdb_entries; 371 }; 372 373 struct dpsw_rsp_fdb_add { 374 __le16 fdb_id; 375 }; 376 377 struct dpsw_cmd_fdb_remove { 378 __le16 fdb_id; 379 }; 380 381 #define DPSW_ENTRY_TYPE_SHIFT 0 382 #define DPSW_ENTRY_TYPE_SIZE 4 383 384 struct dpsw_cmd_fdb_unicast_op { 385 /* cmd word 0 */ 386 __le16 fdb_id; 387 u8 mac_addr[6]; 388 /* cmd word 1 */ 389 __le16 if_egress; 390 /* only the first 4 bits from LSB */ 391 u8 type; 392 }; 393 394 struct dpsw_cmd_fdb_multicast_op { 395 /* cmd word 0 */ 396 __le16 fdb_id; 397 __le16 num_ifs; 398 /* only the first 4 bits from LSB */ 399 u8 type; 400 u8 pad[3]; 401 /* cmd word 1 */ 402 u8 mac_addr[6]; 403 __le16 pad2; 404 /* cmd word 2-5 */ 405 __le64 if_id; 406 }; 407 408 struct dpsw_cmd_fdb_dump { 409 __le16 fdb_id; 410 __le16 pad0; 411 __le32 pad1; 412 __le64 iova_addr; 413 __le32 iova_size; 414 }; 415 416 struct dpsw_rsp_fdb_dump { 417 __le16 num_entries; 418 }; 419 420 struct dpsw_rsp_ctrl_if_get_attr { 421 __le64 pad; 422 __le32 rx_fqid; 423 __le32 rx_err_fqid; 424 __le32 tx_err_conf_fqid; 425 }; 426 427 #define DPSW_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) 428 struct dpsw_cmd_ctrl_if_set_pools { 429 u8 num_dpbp; 430 u8 backup_pool_mask; 431 __le16 pad; 432 __le32 dpbp_id[DPSW_MAX_DPBP]; 433 __le16 buffer_size[DPSW_MAX_DPBP]; 434 }; 435 436 #define DPSW_DEST_TYPE_SHIFT 0 437 #define DPSW_DEST_TYPE_SIZE 4 438 439 struct dpsw_cmd_ctrl_if_set_queue { 440 __le32 dest_id; 441 u8 dest_priority; 442 u8 pad; 443 /* from LSB: dest_type:4 */ 444 u8 dest_type; 445 u8 qtype; 446 __le64 user_ctx; 447 __le32 options; 448 }; 449 450 struct dpsw_rsp_get_api_version { 451 __le16 version_major; 452 __le16 version_minor; 453 }; 454 455 struct dpsw_rsp_if_get_mac_addr { 456 __le16 pad; 457 u8 mac_addr[6]; 458 }; 459 460 struct dpsw_cmd_set_egress_flood { 461 __le16 fdb_id; 462 u8 flood_type; 463 u8 pad[5]; 464 __le64 if_id; 465 }; 466 467 #define DPSW_LEARNING_MODE_SHIFT 0 468 #define DPSW_LEARNING_MODE_SIZE 4 469 470 struct dpsw_cmd_if_set_learning_mode { 471 __le16 if_id; 472 /* only the first 4 bits from LSB */ 473 u8 mode; 474 }; 475 476 struct dpsw_cmd_acl_add { 477 __le16 pad; 478 __le16 max_entries; 479 }; 480 481 struct dpsw_rsp_acl_add { 482 __le16 acl_id; 483 }; 484 485 struct dpsw_cmd_acl_remove { 486 __le16 acl_id; 487 }; 488 489 struct dpsw_cmd_acl_if { 490 __le16 acl_id; 491 __le16 num_ifs; 492 __le32 pad; 493 __le64 if_id; 494 }; 495 496 struct dpsw_prep_acl_entry { 497 u8 match_l2_dest_mac[6]; 498 __le16 match_l2_tpid; 499 500 u8 match_l2_source_mac[6]; 501 __le16 match_l2_vlan_id; 502 503 __le32 match_l3_dest_ip; 504 __le32 match_l3_source_ip; 505 506 __le16 match_l4_dest_port; 507 __le16 match_l4_source_port; 508 __le16 match_l2_ether_type; 509 u8 match_l2_pcp_dei; 510 u8 match_l3_dscp; 511 512 u8 mask_l2_dest_mac[6]; 513 __le16 mask_l2_tpid; 514 515 u8 mask_l2_source_mac[6]; 516 __le16 mask_l2_vlan_id; 517 518 __le32 mask_l3_dest_ip; 519 __le32 mask_l3_source_ip; 520 521 __le16 mask_l4_dest_port; 522 __le16 mask_l4_source_port; 523 __le16 mask_l2_ether_type; 524 u8 mask_l2_pcp_dei; 525 u8 mask_l3_dscp; 526 527 u8 match_l3_protocol; 528 u8 mask_l3_protocol; 529 }; 530 531 #define DPSW_RESULT_ACTION_SHIFT 0 532 #define DPSW_RESULT_ACTION_SIZE 4 533 534 struct dpsw_cmd_acl_entry { 535 __le16 acl_id; 536 __le16 result_if_id; 537 __le32 precedence; 538 /* from LSB only the first 4 bits */ 539 u8 result_action; 540 u8 pad[7]; 541 __le64 pad2[4]; 542 __le64 key_iova; 543 }; 544 545 struct dpsw_cmd_set_reflection_if { 546 __le16 if_id; 547 }; 548 549 #define DPSW_FILTER_SHIFT 0 550 #define DPSW_FILTER_SIZE 2 551 552 struct dpsw_cmd_if_reflection { 553 __le16 if_id; 554 __le16 vlan_id; 555 /* only 2 bits from the LSB */ 556 u8 filter; 557 }; 558 559 struct dpsw_cmd_lag { 560 u8 group_id; 561 u8 num_ifs; 562 u8 pad[6]; 563 u8 if_id[DPSW_MAX_LAG_IFS]; 564 u8 phase; 565 }; 566 567 struct dpsw_cmd_if_set_lag_state { 568 __le16 if_id; 569 u8 tx_enabled; 570 }; 571 #pragma pack(pop) 572 #endif /* __FSL_DPSW_CMD_H */ 573