1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 */
6
7 #include <linux/ethtool.h>
8 #include <linux/kernel.h>
9 #include <linux/mii.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/delay.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/bitfield.h>
17 #include <linux/nvmem-consumer.h>
18
19 #include <dt-bindings/net/ti-dp83867.h>
20
21 #define DP83867_PHY_ID 0x2000a231
22 #define DP83867_DEVADDR 0x1f
23
24 #define MII_DP83867_PHYCTRL 0x10
25 #define MII_DP83867_PHYSTS 0x11
26 #define MII_DP83867_MICR 0x12
27 #define MII_DP83867_ISR 0x13
28 #define DP83867_CFG2 0x14
29 #define DP83867_LEDCR1 0x18
30 #define DP83867_LEDCR2 0x19
31 #define DP83867_CFG3 0x1e
32 #define DP83867_CTRL 0x1f
33
34 /* Extended Registers */
35 #define DP83867_FLD_THR_CFG 0x002e
36 #define DP83867_CFG4 0x0031
37 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
38 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
39 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
40 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
41 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
42
43 #define DP83867_RGMIICTL 0x0032
44 #define DP83867_STRAP_STS1 0x006E
45 #define DP83867_STRAP_STS2 0x006f
46 #define DP83867_RGMIIDCTL 0x0086
47 #define DP83867_DSP_FFE_CFG 0x012c
48 #define DP83867_RXFCFG 0x0134
49 #define DP83867_RXFPMD1 0x0136
50 #define DP83867_RXFPMD2 0x0137
51 #define DP83867_RXFPMD3 0x0138
52 #define DP83867_RXFSOP1 0x0139
53 #define DP83867_RXFSOP2 0x013A
54 #define DP83867_RXFSOP3 0x013B
55 #define DP83867_IO_MUX_CFG 0x0170
56 #define DP83867_SGMIICTL 0x00D3
57 #define DP83867_10M_SGMII_CFG 0x016F
58 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
59
60 #define DP83867_SW_RESET BIT(15)
61 #define DP83867_SW_RESTART BIT(14)
62
63 /* MICR Interrupt bits */
64 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
65 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
66 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
67 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
68 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
69 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
70 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
71 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
72 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
73 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
74 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
75 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
76
77 /* RGMIICTL bits */
78 #define DP83867_RGMII_EN BIT(7)
79 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
80 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
81
82 /* SGMIICTL bits */
83 #define DP83867_SGMII_TYPE BIT(14)
84
85 /* RXFCFG bits*/
86 #define DP83867_WOL_MAGIC_EN BIT(0)
87 #define DP83867_WOL_BCAST_EN BIT(2)
88 #define DP83867_WOL_UCAST_EN BIT(4)
89 #define DP83867_WOL_SEC_EN BIT(5)
90 #define DP83867_WOL_ENH_MAC BIT(7)
91
92 /* STRAP_STS1 bits */
93 #define DP83867_STRAP_STS1_RESERVED BIT(11)
94
95 /* STRAP_STS2 bits */
96 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
97
98 /* PHY CTRL bits */
99 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
100 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
101 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
102 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
103 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
104 #define DP83867_PHYCR_SGMII_EN BIT(11)
105 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
106 #define DP83867_PHYCR_MDIX_MASK GENMASK(6, 5)
107 #define DP83867_PHYCR_MDIX_MDI (0x0 << 5)
108 #define DP83867_PHYCR_MDIX_MDIX (0x1 << 5)
109 #define DP83867_PHYCR_MDIX_AUTO (0x3 << 5)
110
111 /* RGMIIDCTL bits */
112 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
113 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
114 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
115 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
116
117 /* IO_MUX_CFG bits */
118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
119 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
120 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
121 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
122 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
123 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
124
125 /* PHY STS bits */
126 #define DP83867_PHYSTS_1000 BIT(15)
127 #define DP83867_PHYSTS_100 BIT(14)
128 #define DP83867_PHYSTS_DUPLEX BIT(13)
129 #define DP83867_PHYSTS_LINK BIT(10)
130 #define DP83867_PHYSTS_MDIX_CD BIT(9)
131 #define DP83867_PHYSTS_MDIX_AB BIT(8)
132 #define DP83867_PHYSTS_MDIX_MASK (DP83867_PHYSTS_MDIX_AB | \
133 DP83867_PHYSTS_MDIX_CD)
134
135 /* CFG2 bits */
136 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
137 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
138 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0
139 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1
140 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2
141 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3
142 #define DP83867_DOWNSHIFT_1_COUNT 1
143 #define DP83867_DOWNSHIFT_2_COUNT 2
144 #define DP83867_DOWNSHIFT_4_COUNT 4
145 #define DP83867_DOWNSHIFT_8_COUNT 8
146 #define DP83867_SGMII_AUTONEG_EN BIT(7)
147
148 /* CFG3 bits */
149 #define DP83867_CFG3_INT_OE BIT(7)
150 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
151
152 /* CFG4 bits */
153 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
154
155 /* FLD_THR_CFG */
156 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
157
158 #define DP83867_LED_COUNT 4
159
160 /* LED_DRV bits */
161 #define DP83867_LED_DRV_EN(x) BIT((x) * 4)
162 #define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1)
163 #define DP83867_LED_POLARITY(x) BIT((x) * 4 + 2)
164
165 #define DP83867_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4))
166 #define DP83867_LED_FN_MASK(idx) (0xf << ((idx) * 4))
167 #define DP83867_LED_FN_RX_ERR 0xe /* Receive Error */
168 #define DP83867_LED_FN_RX_TX_ERR 0xd /* Receive Error or Transmit Error */
169 #define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
170 #define DP83867_LED_FN_FULL_DUPLEX 0xa /* Full duplex */
171 #define DP83867_LED_FN_LINK_100_1000_BT 0x9 /* 100/1000BT link established */
172 #define DP83867_LED_FN_LINK_10_100_BT 0x8 /* 10/100BT link established */
173 #define DP83867_LED_FN_LINK_10_BT 0x7 /* 10BT link established */
174 #define DP83867_LED_FN_LINK_100_BTX 0x6 /* 100 BTX link established */
175 #define DP83867_LED_FN_LINK_1000_BT 0x5 /* 1000 BT link established */
176 #define DP83867_LED_FN_COLLISION 0x4 /* Collision detected */
177 #define DP83867_LED_FN_RX 0x3 /* Receive activity */
178 #define DP83867_LED_FN_TX 0x2 /* Transmit activity */
179 #define DP83867_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
180 #define DP83867_LED_FN_LINK 0x0 /* Link established */
181
182 enum {
183 DP83867_PORT_MIRROING_KEEP,
184 DP83867_PORT_MIRROING_EN,
185 DP83867_PORT_MIRROING_DIS,
186 };
187
188 struct dp83867_private {
189 u32 rx_id_delay;
190 u32 tx_id_delay;
191 u32 tx_fifo_depth;
192 u32 rx_fifo_depth;
193 int io_impedance;
194 int port_mirroring;
195 bool rxctrl_strap_quirk;
196 bool set_clk_output;
197 u32 clk_output_sel;
198 bool sgmii_ref_clk_en;
199 };
200
dp83867_ack_interrupt(struct phy_device * phydev)201 static int dp83867_ack_interrupt(struct phy_device *phydev)
202 {
203 int err = phy_read(phydev, MII_DP83867_ISR);
204
205 if (err < 0)
206 return err;
207
208 return 0;
209 }
210
dp83867_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)211 static int dp83867_set_wol(struct phy_device *phydev,
212 struct ethtool_wolinfo *wol)
213 {
214 struct net_device *ndev = phydev->attached_dev;
215 u16 val_rxcfg, val_micr;
216 const u8 *mac;
217
218 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
219 val_micr = phy_read(phydev, MII_DP83867_MICR);
220
221 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
222 WAKE_BCAST)) {
223 val_rxcfg |= DP83867_WOL_ENH_MAC;
224 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
225
226 if (wol->wolopts & WAKE_MAGIC) {
227 mac = (const u8 *)ndev->dev_addr;
228
229 if (!is_valid_ether_addr(mac))
230 return -EINVAL;
231
232 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
233 (mac[1] << 8 | mac[0]));
234 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
235 (mac[3] << 8 | mac[2]));
236 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
237 (mac[5] << 8 | mac[4]));
238
239 val_rxcfg |= DP83867_WOL_MAGIC_EN;
240 } else {
241 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
242 }
243
244 if (wol->wolopts & WAKE_MAGICSECURE) {
245 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
246 (wol->sopass[1] << 8) | wol->sopass[0]);
247 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
248 (wol->sopass[3] << 8) | wol->sopass[2]);
249 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
250 (wol->sopass[5] << 8) | wol->sopass[4]);
251
252 val_rxcfg |= DP83867_WOL_SEC_EN;
253 } else {
254 val_rxcfg &= ~DP83867_WOL_SEC_EN;
255 }
256
257 if (wol->wolopts & WAKE_UCAST)
258 val_rxcfg |= DP83867_WOL_UCAST_EN;
259 else
260 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
261
262 if (wol->wolopts & WAKE_BCAST)
263 val_rxcfg |= DP83867_WOL_BCAST_EN;
264 else
265 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
266 } else {
267 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
268 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
269 }
270
271 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
272 phy_write(phydev, MII_DP83867_MICR, val_micr);
273
274 return 0;
275 }
276
dp83867_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)277 static void dp83867_get_wol(struct phy_device *phydev,
278 struct ethtool_wolinfo *wol)
279 {
280 u16 value, sopass_val;
281
282 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
283 WAKE_MAGICSECURE);
284 wol->wolopts = 0;
285
286 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
287
288 if (value & DP83867_WOL_UCAST_EN)
289 wol->wolopts |= WAKE_UCAST;
290
291 if (value & DP83867_WOL_BCAST_EN)
292 wol->wolopts |= WAKE_BCAST;
293
294 if (value & DP83867_WOL_MAGIC_EN)
295 wol->wolopts |= WAKE_MAGIC;
296
297 if (value & DP83867_WOL_SEC_EN) {
298 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
299 DP83867_RXFSOP1);
300 wol->sopass[0] = (sopass_val & 0xff);
301 wol->sopass[1] = (sopass_val >> 8);
302
303 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
304 DP83867_RXFSOP2);
305 wol->sopass[2] = (sopass_val & 0xff);
306 wol->sopass[3] = (sopass_val >> 8);
307
308 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
309 DP83867_RXFSOP3);
310 wol->sopass[4] = (sopass_val & 0xff);
311 wol->sopass[5] = (sopass_val >> 8);
312
313 wol->wolopts |= WAKE_MAGICSECURE;
314 }
315
316 if (!(value & DP83867_WOL_ENH_MAC))
317 wol->wolopts = 0;
318 }
319
dp83867_config_intr(struct phy_device * phydev)320 static int dp83867_config_intr(struct phy_device *phydev)
321 {
322 int micr_status, err;
323
324 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
325 err = dp83867_ack_interrupt(phydev);
326 if (err)
327 return err;
328
329 micr_status = phy_read(phydev, MII_DP83867_MICR);
330 if (micr_status < 0)
331 return micr_status;
332
333 micr_status |=
334 (MII_DP83867_MICR_AN_ERR_INT_EN |
335 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
336 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
337 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
338 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
339 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
340
341 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
342 } else {
343 micr_status = 0x0;
344 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
345 if (err)
346 return err;
347
348 err = dp83867_ack_interrupt(phydev);
349 }
350
351 return err;
352 }
353
dp83867_handle_interrupt(struct phy_device * phydev)354 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
355 {
356 int irq_status, irq_enabled;
357
358 irq_status = phy_read(phydev, MII_DP83867_ISR);
359 if (irq_status < 0) {
360 phy_error(phydev);
361 return IRQ_NONE;
362 }
363
364 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
365 if (irq_enabled < 0) {
366 phy_error(phydev);
367 return IRQ_NONE;
368 }
369
370 if (!(irq_status & irq_enabled))
371 return IRQ_NONE;
372
373 phy_trigger_machine(phydev);
374
375 return IRQ_HANDLED;
376 }
377
dp83867_read_status(struct phy_device * phydev)378 static int dp83867_read_status(struct phy_device *phydev)
379 {
380 int status = phy_read(phydev, MII_DP83867_PHYSTS);
381 int ret;
382
383 ret = genphy_read_status(phydev);
384 if (ret)
385 return ret;
386
387 if (status < 0)
388 return status;
389
390 if (status & DP83867_PHYSTS_DUPLEX)
391 phydev->duplex = DUPLEX_FULL;
392 else
393 phydev->duplex = DUPLEX_HALF;
394
395 if (status & DP83867_PHYSTS_1000)
396 phydev->speed = SPEED_1000;
397 else if (status & DP83867_PHYSTS_100)
398 phydev->speed = SPEED_100;
399 else
400 phydev->speed = SPEED_10;
401
402 if (!(status & DP83867_PHYSTS_LINK)) {
403 phydev->mdix = ETH_TP_MDI_INVALID;
404 } else {
405 switch (status & DP83867_PHYSTS_MDIX_MASK) {
406 case 0:
407 phydev->mdix = ETH_TP_MDI;
408 break;
409 case DP83867_PHYSTS_MDIX_MASK:
410 phydev->mdix = ETH_TP_MDI_X;
411 break;
412 default:
413 phydev->mdix = ETH_TP_MDI_INVALID;
414 break;
415 }
416 }
417
418 return 0;
419 }
420
dp83867_get_downshift(struct phy_device * phydev,u8 * data)421 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
422 {
423 int val, cnt, enable, count;
424
425 val = phy_read(phydev, DP83867_CFG2);
426 if (val < 0)
427 return val;
428
429 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
430 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
431
432 switch (cnt) {
433 case DP83867_DOWNSHIFT_1_COUNT_VAL:
434 count = DP83867_DOWNSHIFT_1_COUNT;
435 break;
436 case DP83867_DOWNSHIFT_2_COUNT_VAL:
437 count = DP83867_DOWNSHIFT_2_COUNT;
438 break;
439 case DP83867_DOWNSHIFT_4_COUNT_VAL:
440 count = DP83867_DOWNSHIFT_4_COUNT;
441 break;
442 case DP83867_DOWNSHIFT_8_COUNT_VAL:
443 count = DP83867_DOWNSHIFT_8_COUNT;
444 break;
445 default:
446 return -EINVAL;
447 }
448
449 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
450
451 return 0;
452 }
453
dp83867_set_downshift(struct phy_device * phydev,u8 cnt)454 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
455 {
456 int val, count;
457
458 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
459 return -E2BIG;
460
461 if (!cnt)
462 return phy_clear_bits(phydev, DP83867_CFG2,
463 DP83867_DOWNSHIFT_EN);
464
465 switch (cnt) {
466 case DP83867_DOWNSHIFT_1_COUNT:
467 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
468 break;
469 case DP83867_DOWNSHIFT_2_COUNT:
470 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
471 break;
472 case DP83867_DOWNSHIFT_4_COUNT:
473 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
474 break;
475 case DP83867_DOWNSHIFT_8_COUNT:
476 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
477 break;
478 default:
479 phydev_err(phydev,
480 "Downshift count must be 1, 2, 4 or 8\n");
481 return -EINVAL;
482 }
483
484 val = DP83867_DOWNSHIFT_EN;
485 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
486
487 return phy_modify(phydev, DP83867_CFG2,
488 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
489 val);
490 }
491
dp83867_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)492 static int dp83867_get_tunable(struct phy_device *phydev,
493 struct ethtool_tunable *tuna, void *data)
494 {
495 switch (tuna->id) {
496 case ETHTOOL_PHY_DOWNSHIFT:
497 return dp83867_get_downshift(phydev, data);
498 default:
499 return -EOPNOTSUPP;
500 }
501 }
502
dp83867_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)503 static int dp83867_set_tunable(struct phy_device *phydev,
504 struct ethtool_tunable *tuna, const void *data)
505 {
506 switch (tuna->id) {
507 case ETHTOOL_PHY_DOWNSHIFT:
508 return dp83867_set_downshift(phydev, *(const u8 *)data);
509 default:
510 return -EOPNOTSUPP;
511 }
512 }
513
dp83867_config_port_mirroring(struct phy_device * phydev)514 static int dp83867_config_port_mirroring(struct phy_device *phydev)
515 {
516 struct dp83867_private *dp83867 = phydev->priv;
517
518 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
519 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
520 DP83867_CFG4_PORT_MIRROR_EN);
521 else
522 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
523 DP83867_CFG4_PORT_MIRROR_EN);
524 return 0;
525 }
526
527 #if IS_ENABLED(CONFIG_OF_MDIO)
dp83867_of_init_io_impedance(struct phy_device * phydev)528 static int dp83867_of_init_io_impedance(struct phy_device *phydev)
529 {
530 struct dp83867_private *dp83867 = phydev->priv;
531 struct device *dev = &phydev->mdio.dev;
532 struct device_node *of_node = dev->of_node;
533 struct nvmem_cell *cell;
534 u8 *buf, val;
535 int ret;
536
537 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
538 if (IS_ERR(cell)) {
539 ret = PTR_ERR(cell);
540 if (ret != -ENOENT && ret != -EOPNOTSUPP)
541 return phydev_err_probe(phydev, ret,
542 "failed to get nvmem cell io_impedance_ctrl\n");
543
544 /* If no nvmem cell, check for the boolean properties. */
545 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
546 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
547 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
548 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
549 else
550 dp83867->io_impedance = -1; /* leave at default */
551
552 return 0;
553 }
554
555 buf = nvmem_cell_read(cell, NULL);
556 nvmem_cell_put(cell);
557
558 if (IS_ERR(buf))
559 return PTR_ERR(buf);
560
561 val = *buf;
562 kfree(buf);
563
564 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
565 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
566 return -ERANGE;
567 }
568 dp83867->io_impedance = val;
569
570 return 0;
571 }
572
dp83867_of_init(struct phy_device * phydev)573 static int dp83867_of_init(struct phy_device *phydev)
574 {
575 struct dp83867_private *dp83867 = phydev->priv;
576 struct device *dev = &phydev->mdio.dev;
577 struct device_node *of_node = dev->of_node;
578 int ret;
579
580 if (!of_node)
581 return -ENODEV;
582
583 /* Optional configuration */
584 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
585 &dp83867->clk_output_sel);
586 /* If not set, keep default */
587 if (!ret) {
588 dp83867->set_clk_output = true;
589 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
590 * DP83867_CLK_O_SEL_OFF.
591 */
592 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
593 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
594 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
595 dp83867->clk_output_sel);
596 return -EINVAL;
597 }
598 }
599
600 ret = dp83867_of_init_io_impedance(phydev);
601 if (ret)
602 return ret;
603
604 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
605 "ti,dp83867-rxctrl-strap-quirk");
606
607 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
608 "ti,sgmii-ref-clock-output-enable");
609
610 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_00_NS;
611 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
612 &dp83867->rx_id_delay);
613 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
614 phydev_err(phydev,
615 "ti,rx-internal-delay value of %u out of range\n",
616 dp83867->rx_id_delay);
617 return -EINVAL;
618 }
619
620 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_00_NS;
621 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
622 &dp83867->tx_id_delay);
623 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
624 phydev_err(phydev,
625 "ti,tx-internal-delay value of %u out of range\n",
626 dp83867->tx_id_delay);
627 return -EINVAL;
628 }
629
630 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
631 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
632
633 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
634 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
635
636 ret = of_property_read_u32(of_node, "ti,fifo-depth",
637 &dp83867->tx_fifo_depth);
638 if (ret) {
639 ret = of_property_read_u32(of_node, "tx-fifo-depth",
640 &dp83867->tx_fifo_depth);
641 if (ret)
642 dp83867->tx_fifo_depth =
643 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
644 }
645
646 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
647 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
648 dp83867->tx_fifo_depth);
649 return -EINVAL;
650 }
651
652 ret = of_property_read_u32(of_node, "rx-fifo-depth",
653 &dp83867->rx_fifo_depth);
654 if (ret)
655 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
656
657 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
658 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
659 dp83867->rx_fifo_depth);
660 return -EINVAL;
661 }
662
663 return 0;
664 }
665 #else
dp83867_of_init(struct phy_device * phydev)666 static int dp83867_of_init(struct phy_device *phydev)
667 {
668 struct dp83867_private *dp83867 = phydev->priv;
669 u16 delay;
670
671 /* For non-OF device, the RX and TX ID values are either strapped
672 * or take from default value. So, we init RX & TX ID values here
673 * so that the RGMIIDCTL is configured correctly later in
674 * dp83867_config_init();
675 */
676 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
677 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
678 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
679 DP83867_RGMII_TX_CLK_DELAY_MAX;
680
681 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
682 * same here or else the default '0' means highest IO impedance
683 * which is wrong.
684 */
685 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
686
687 /* For non-OF device, the RX and TX FIFO depths are taken from
688 * default value. So, we init RX & TX FIFO depths here
689 * so that it is configured correctly later in dp83867_config_init();
690 */
691 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
692 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
693
694 return 0;
695 }
696 #endif /* CONFIG_OF_MDIO */
697
dp83867_suspend(struct phy_device * phydev)698 static int dp83867_suspend(struct phy_device *phydev)
699 {
700 /* Disable PHY Interrupts */
701 if (phy_interrupt_is_valid(phydev)) {
702 phydev->interrupts = PHY_INTERRUPT_DISABLED;
703 dp83867_config_intr(phydev);
704 }
705
706 return genphy_suspend(phydev);
707 }
708
dp83867_resume(struct phy_device * phydev)709 static int dp83867_resume(struct phy_device *phydev)
710 {
711 /* Enable PHY Interrupts */
712 if (phy_interrupt_is_valid(phydev)) {
713 phydev->interrupts = PHY_INTERRUPT_ENABLED;
714 dp83867_config_intr(phydev);
715 }
716
717 genphy_resume(phydev);
718
719 return 0;
720 }
721
dp83867_probe(struct phy_device * phydev)722 static int dp83867_probe(struct phy_device *phydev)
723 {
724 struct dp83867_private *dp83867;
725
726 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
727 GFP_KERNEL);
728 if (!dp83867)
729 return -ENOMEM;
730
731 phydev->priv = dp83867;
732
733 return dp83867_of_init(phydev);
734 }
735
dp83867_config_init(struct phy_device * phydev)736 static int dp83867_config_init(struct phy_device *phydev)
737 {
738 struct dp83867_private *dp83867 = phydev->priv;
739 int ret, val, bs;
740
741 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
742
743 /* Force speed optimization for the PHY even if it strapped */
744 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
745 DP83867_DOWNSHIFT_EN);
746 if (ret)
747 return ret;
748
749 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
750 if (dp83867->rxctrl_strap_quirk)
751 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
752 BIT(7));
753
754 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
755 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
756 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
757 * be set to 0x2. This may causes the PHY link to be unstable -
758 * the default value 0x1 need to be restored.
759 */
760 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
761 DP83867_FLD_THR_CFG,
762 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
763 0x1);
764 if (ret)
765 return ret;
766 }
767
768 /* Although the DP83867 reports EEE capability through the
769 * MDIO_PCS_EEE_ABLE and MDIO_AN_EEE_ADV registers, the feature
770 * is not actually implemented in hardware.
771 */
772 phy_disable_eee(phydev);
773
774 val = phy_read(phydev, MII_DP83867_PHYCTRL);
775 if (val < 0)
776 return val;
777
778 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
779 val |= (dp83867->tx_fifo_depth <<
780 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
781
782 val &= ~DP83867_PHYCR_SGMII_EN;
783 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
784 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
785 val |= (dp83867->rx_fifo_depth <<
786 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) |
787 DP83867_PHYCR_SGMII_EN;
788 }
789
790 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
791 if (ret)
792 return ret;
793
794 if (phy_interface_is_rgmii(phydev)) {
795 /* Set up RGMII delays */
796 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
797
798 val |= DP83867_RGMII_EN;
799 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
800 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
801 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
802
803 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
804 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
805
806 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
807 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
808
809 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
810
811 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
812 dp83867->rx_id_delay |
813 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
814 } else {
815 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
816 val &= ~DP83867_RGMII_EN;
817 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
818 }
819
820 /* If specified, set io impedance */
821 if (dp83867->io_impedance >= 0)
822 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
823 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
824 dp83867->io_impedance);
825
826 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
827 /* For support SPEED_10 in SGMII mode
828 * DP83867_10M_SGMII_RATE_ADAPT bit
829 * has to be cleared by software. That
830 * does not affect SPEED_100 and
831 * SPEED_1000.
832 */
833 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
834 DP83867_10M_SGMII_CFG,
835 DP83867_10M_SGMII_RATE_ADAPT_MASK,
836 0);
837 if (ret)
838 return ret;
839
840 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
841 * are 01). That is not enough to finalize autoneg on some
842 * devices. Increase this timer duration to maximum 16ms.
843 */
844 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
845 DP83867_CFG4,
846 DP83867_CFG4_SGMII_ANEG_MASK,
847 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
848
849 if (ret)
850 return ret;
851
852 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
853 /* SGMII type is set to 4-wire mode by default.
854 * If we place appropriate property in dts (see above)
855 * switch on 6-wire mode.
856 */
857 if (dp83867->sgmii_ref_clk_en)
858 val |= DP83867_SGMII_TYPE;
859 else
860 val &= ~DP83867_SGMII_TYPE;
861 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
862
863 /* This is a SW workaround for link instability if RX_CTRL is
864 * not strapped to mode 3 or 4 in HW. This is required for SGMII
865 * in addition to clearing bit 7, handled above.
866 */
867 if (dp83867->rxctrl_strap_quirk)
868 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
869 BIT(8));
870 }
871
872 val = phy_read(phydev, DP83867_CFG3);
873 /* Enable Interrupt output INT_OE in CFG3 register */
874 if (phy_interrupt_is_valid(phydev))
875 val |= DP83867_CFG3_INT_OE;
876
877 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
878 phy_write(phydev, DP83867_CFG3, val);
879
880 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
881 dp83867_config_port_mirroring(phydev);
882
883 /* Clock output selection if muxing property is set */
884 if (dp83867->set_clk_output) {
885 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
886
887 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
888 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
889 } else {
890 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
891 val = dp83867->clk_output_sel <<
892 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
893 }
894
895 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
896 mask, val);
897 }
898
899 return 0;
900 }
901
dp83867_config_mdix(struct phy_device * phydev,u8 ctrl)902 static int dp83867_config_mdix(struct phy_device *phydev, u8 ctrl)
903 {
904 int val;
905
906 switch (ctrl) {
907 case ETH_TP_MDI:
908 val = DP83867_PHYCR_MDIX_MDI;
909 break;
910 case ETH_TP_MDI_X:
911 val = DP83867_PHYCR_MDIX_MDIX;
912 break;
913 case ETH_TP_MDI_AUTO:
914 val = DP83867_PHYCR_MDIX_AUTO;
915 break;
916 default:
917 return -EINVAL;
918 }
919
920 return phy_modify(phydev, MII_DP83867_PHYCTRL,
921 DP83867_PHYCR_MDIX_MASK, val);
922 }
923
dp83867_config_aneg(struct phy_device * phydev)924 static int dp83867_config_aneg(struct phy_device *phydev)
925 {
926 int ret;
927
928 ret = dp83867_config_mdix(phydev, phydev->mdix_ctrl);
929 if (ret)
930 return ret;
931
932 return genphy_config_aneg(phydev);
933 }
934
dp83867_phy_reset(struct phy_device * phydev)935 static int dp83867_phy_reset(struct phy_device *phydev)
936 {
937 int err;
938
939 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
940 if (err < 0)
941 return err;
942
943 usleep_range(10, 20);
944
945 err = phy_modify(phydev, MII_DP83867_PHYCTRL,
946 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
947 if (err < 0)
948 return err;
949
950 /* Configure the DSP Feedforward Equalizer Configuration register to
951 * improve short cable (< 1 meter) performance. This will not affect
952 * long cable performance.
953 */
954 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,
955 0x0e81);
956 if (err < 0)
957 return err;
958
959 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
960 if (err < 0)
961 return err;
962
963 usleep_range(10, 20);
964
965 return 0;
966 }
967
dp83867_link_change_notify(struct phy_device * phydev)968 static void dp83867_link_change_notify(struct phy_device *phydev)
969 {
970 /* There is a limitation in DP83867 PHY device where SGMII AN is
971 * only triggered once after the device is booted up. Even after the
972 * PHY TPI is down and up again, SGMII AN is not triggered and
973 * hence no new in-band message from PHY to MAC side SGMII.
974 * This could cause an issue during power up, when PHY is up prior
975 * to MAC. At this condition, once MAC side SGMII is up, MAC side
976 * SGMII wouldn`t receive new in-band message from TI PHY with
977 * correct link status, speed and duplex info.
978 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
979 * whenever there is a link change.
980 */
981 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
982 int val;
983
984 val = phy_modify_changed(phydev, DP83867_CFG2,
985 DP83867_SGMII_AUTONEG_EN, 0);
986
987 /* Keep the in-band setting made by dp83867_config_inband() */
988 if (val != 0)
989 phy_set_bits(phydev, DP83867_CFG2,
990 DP83867_SGMII_AUTONEG_EN);
991 }
992 }
993
dp83867_loopback(struct phy_device * phydev,bool enable,int speed)994 static int dp83867_loopback(struct phy_device *phydev, bool enable, int speed)
995 {
996 if (enable && speed)
997 return -EOPNOTSUPP;
998
999 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
1000 enable ? BMCR_LOOPBACK : 0);
1001 }
1002
1003 static int
dp83867_led_brightness_set(struct phy_device * phydev,u8 index,enum led_brightness brightness)1004 dp83867_led_brightness_set(struct phy_device *phydev,
1005 u8 index, enum led_brightness brightness)
1006 {
1007 u32 val;
1008
1009 if (index >= DP83867_LED_COUNT)
1010 return -EINVAL;
1011
1012 /* DRV_EN==1: output is DRV_VAL */
1013 val = DP83867_LED_DRV_EN(index);
1014
1015 if (brightness)
1016 val |= DP83867_LED_DRV_VAL(index);
1017
1018 return phy_modify(phydev, DP83867_LEDCR2,
1019 DP83867_LED_DRV_VAL(index) |
1020 DP83867_LED_DRV_EN(index),
1021 val);
1022 }
1023
dp83867_led_mode(u8 index,unsigned long rules)1024 static int dp83867_led_mode(u8 index, unsigned long rules)
1025 {
1026 if (index >= DP83867_LED_COUNT)
1027 return -EINVAL;
1028
1029 switch (rules) {
1030 case BIT(TRIGGER_NETDEV_LINK):
1031 return DP83867_LED_FN_LINK;
1032 case BIT(TRIGGER_NETDEV_LINK_10):
1033 return DP83867_LED_FN_LINK_10_BT;
1034 case BIT(TRIGGER_NETDEV_LINK_100):
1035 return DP83867_LED_FN_LINK_100_BTX;
1036 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
1037 return DP83867_LED_FN_FULL_DUPLEX;
1038 case BIT(TRIGGER_NETDEV_TX):
1039 return DP83867_LED_FN_TX;
1040 case BIT(TRIGGER_NETDEV_RX):
1041 return DP83867_LED_FN_RX;
1042 case BIT(TRIGGER_NETDEV_LINK_1000):
1043 return DP83867_LED_FN_LINK_1000_BT;
1044 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1045 return DP83867_LED_FN_RX_TX;
1046 case BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000):
1047 return DP83867_LED_FN_LINK_100_1000_BT;
1048 case BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100):
1049 return DP83867_LED_FN_LINK_10_100_BT;
1050 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1051 return DP83867_LED_FN_LINK_RX_TX;
1052 default:
1053 return -EOPNOTSUPP;
1054 }
1055 }
1056
dp83867_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)1057 static int dp83867_led_hw_is_supported(struct phy_device *phydev, u8 index,
1058 unsigned long rules)
1059 {
1060 int ret;
1061
1062 ret = dp83867_led_mode(index, rules);
1063 if (ret < 0)
1064 return ret;
1065
1066 return 0;
1067 }
1068
dp83867_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)1069 static int dp83867_led_hw_control_set(struct phy_device *phydev, u8 index,
1070 unsigned long rules)
1071 {
1072 int mode, ret;
1073
1074 mode = dp83867_led_mode(index, rules);
1075 if (mode < 0)
1076 return mode;
1077
1078 ret = phy_modify(phydev, DP83867_LEDCR1, DP83867_LED_FN_MASK(index),
1079 DP83867_LED_FN(index, mode));
1080 if (ret)
1081 return ret;
1082
1083 return phy_modify(phydev, DP83867_LEDCR2, DP83867_LED_DRV_EN(index), 0);
1084 }
1085
dp83867_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)1086 static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index,
1087 unsigned long *rules)
1088 {
1089 int val;
1090
1091 val = phy_read(phydev, DP83867_LEDCR1);
1092 if (val < 0)
1093 return val;
1094
1095 val &= DP83867_LED_FN_MASK(index);
1096 val >>= index * 4;
1097
1098 switch (val) {
1099 case DP83867_LED_FN_LINK:
1100 *rules = BIT(TRIGGER_NETDEV_LINK);
1101 break;
1102 case DP83867_LED_FN_LINK_10_BT:
1103 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1104 break;
1105 case DP83867_LED_FN_LINK_100_BTX:
1106 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1107 break;
1108 case DP83867_LED_FN_FULL_DUPLEX:
1109 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1110 break;
1111 case DP83867_LED_FN_TX:
1112 *rules = BIT(TRIGGER_NETDEV_TX);
1113 break;
1114 case DP83867_LED_FN_RX:
1115 *rules = BIT(TRIGGER_NETDEV_RX);
1116 break;
1117 case DP83867_LED_FN_LINK_1000_BT:
1118 *rules = BIT(TRIGGER_NETDEV_LINK_1000);
1119 break;
1120 case DP83867_LED_FN_RX_TX:
1121 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1122 break;
1123 case DP83867_LED_FN_LINK_100_1000_BT:
1124 *rules = BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000);
1125 break;
1126 case DP83867_LED_FN_LINK_10_100_BT:
1127 *rules = BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100);
1128 break;
1129 case DP83867_LED_FN_LINK_RX_TX:
1130 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1131 BIT(TRIGGER_NETDEV_RX);
1132 break;
1133 default:
1134 *rules = 0;
1135 break;
1136 }
1137
1138 return 0;
1139 }
1140
dp83867_led_polarity_set(struct phy_device * phydev,int index,unsigned long modes)1141 static int dp83867_led_polarity_set(struct phy_device *phydev, int index,
1142 unsigned long modes)
1143 {
1144 /* Default active high */
1145 u16 polarity = DP83867_LED_POLARITY(index);
1146 u32 mode;
1147
1148 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
1149 switch (mode) {
1150 case PHY_LED_ACTIVE_LOW:
1151 polarity = 0;
1152 break;
1153 case PHY_LED_ACTIVE_HIGH:
1154 polarity = DP83867_LED_POLARITY(index);
1155 break;
1156 default:
1157 return -EINVAL;
1158 }
1159 }
1160 return phy_modify(phydev, DP83867_LEDCR2,
1161 DP83867_LED_POLARITY(index), polarity);
1162 }
1163
dp83867_inband_caps(struct phy_device * phydev,phy_interface_t interface)1164 static unsigned int dp83867_inband_caps(struct phy_device *phydev,
1165 phy_interface_t interface)
1166 {
1167 if (interface == PHY_INTERFACE_MODE_SGMII)
1168 return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
1169
1170 return 0;
1171 }
1172
dp83867_config_inband(struct phy_device * phydev,unsigned int modes)1173 static int dp83867_config_inband(struct phy_device *phydev, unsigned int modes)
1174 {
1175 int val = 0;
1176
1177 if (modes == LINK_INBAND_ENABLE)
1178 val = DP83867_SGMII_AUTONEG_EN;
1179
1180 return phy_modify(phydev, DP83867_CFG2, DP83867_SGMII_AUTONEG_EN, val);
1181 }
1182
1183 static struct phy_driver dp83867_driver[] = {
1184 {
1185 .phy_id = DP83867_PHY_ID,
1186 .phy_id_mask = 0xfffffff0,
1187 .name = "TI DP83867",
1188 /* PHY_GBIT_FEATURES */
1189
1190 .probe = dp83867_probe,
1191 .config_init = dp83867_config_init,
1192 .config_aneg = dp83867_config_aneg,
1193 .soft_reset = dp83867_phy_reset,
1194
1195 .read_status = dp83867_read_status,
1196 .get_tunable = dp83867_get_tunable,
1197 .set_tunable = dp83867_set_tunable,
1198
1199 .get_wol = dp83867_get_wol,
1200 .set_wol = dp83867_set_wol,
1201
1202 /* IRQ related */
1203 .config_intr = dp83867_config_intr,
1204 .handle_interrupt = dp83867_handle_interrupt,
1205
1206 .suspend = dp83867_suspend,
1207 .resume = dp83867_resume,
1208
1209 .link_change_notify = dp83867_link_change_notify,
1210 .set_loopback = dp83867_loopback,
1211
1212 .led_brightness_set = dp83867_led_brightness_set,
1213 .led_hw_is_supported = dp83867_led_hw_is_supported,
1214 .led_hw_control_set = dp83867_led_hw_control_set,
1215 .led_hw_control_get = dp83867_led_hw_control_get,
1216 .led_polarity_set = dp83867_led_polarity_set,
1217
1218 .inband_caps = dp83867_inband_caps,
1219 .config_inband = dp83867_config_inband,
1220 },
1221 };
1222 module_phy_driver(dp83867_driver);
1223
1224 static const struct mdio_device_id __maybe_unused dp83867_tbl[] = {
1225 { DP83867_PHY_ID, 0xfffffff0 },
1226 { }
1227 };
1228
1229 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
1230
1231 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
1232 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1233 MODULE_LICENSE("GPL v2");
1234