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Searched refs:DMA_RB_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dni_dma.c165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
214 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
245 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); in cayman_dma_resume()
H A Dr600_dma.c100 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop()
106 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
135 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
169 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
H A Dni.c1824 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1826 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1831 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1833 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
H A Dsi.c3864 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3866 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3870 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3872 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4031 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4033 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4035 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4037 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
H A Dnid.h1304 #define DMA_RB_CNTL 0xd000 macro
H A Dr600.c1708 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1710 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1839 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1841 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
H A Devergreen.c3912 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
3914 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4021 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4023 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
H A Dsid.h1815 #define DMA_RB_CNTL 0xd000 macro
H A Devergreend.h2618 #define DMA_RB_CNTL 0xd000 macro
H A Dr600d.h613 #define DMA_RB_CNTL 0xd000 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_dma.c120 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
122 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
145 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
173 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()
H A Dsid.h1878 #define DMA_RB_CNTL 0x3400 macro