Searched refs:DMA1_REGISTER_OFFSET (Results 1 – 4 of 4) sorted by relevance
63 reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_rptr()87 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_wptr()108 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_set_wptr()170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()201 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
845 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in cayman_get_allowed_info_register()1107 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()1748 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()1831 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()1833 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1302 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
1785 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in gfx_v6_0_constants_init()