Searched refs:DMA0_REGISTER_OFFSET (Results 1 – 4 of 4) sorted by relevance
61 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_rptr()85 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_wptr()106 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_set_wptr()165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()197 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
844 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in cayman_get_allowed_info_register()1106 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()1743 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()1824 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()1826 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1301 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
1784 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in gfx_v6_0_constants_init()