Home
last modified time | relevance | path

Searched refs:DIV_F (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c60 DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
62 DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
64 DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
66 DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
74 DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
76 DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
78 DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
80 DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
231 DIV_F(PERIPH_CLK_IR_PRE_DIV, "ir_pre_div", "periph_sys", 0x11c, 7,
233 DIV_F(PERIPH_CLK_IR_DIV, "ir_div", "ir_pre_div", 0x120, 7,
[all …]
H A Dclk.h69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ macro
/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c382 DIV_F(0, "div_mipi1_pre", "div_mipi1",
396 DIV_F(0, "div_mmc_pre0", "div_mmc0",
399 DIV_F(0, "div_mmc_pre1", "div_mmc1",
403 DIV_F(0, "div_mmc_pre2", "div_mmc2",
406 DIV_F(0, "div_mmc_pre3", "div_mmc3",
415 DIV_F(0, "div_spi_pre0", "div_spi0",
418 DIV_F(0, "div_spi_pre1", "div_spi1",
422 DIV_F(0, "div_spi_pre2", "div_spi2",
H A Dclk-exynos3250.c369 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
376 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
379 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
384 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
389 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
392 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
397 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
407 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
410 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
H A Dclk-exynos5410.c149 DIV_F(0, "div_mmc_pre0", "div_mmc0",
151 DIV_F(0, "div_mmc_pre1", "div_mmc1",
153 DIV_F(0, "div_mmc_pre2", "div_mmc2",
H A Dclk-gs101.c3756 DIV_F(CLK_DOUT_PERIC0_USI14_USI,
3760 DIV_F(CLK_DOUT_PERIC0_USI1_USI,
3764 DIV_F(CLK_DOUT_PERIC0_USI2_USI,
3768 DIV_F(CLK_DOUT_PERIC0_USI3_USI,
3772 DIV_F(CLK_DOUT_PERIC0_USI4_USI,
3776 DIV_F(CLK_DOUT_PERIC0_USI5_USI,
3780 DIV_F(CLK_DOUT_PERIC0_USI6_USI,
3784 DIV_F(CLK_DOUT_PERIC0_USI7_USI,
3788 DIV_F(CLK_DOUT_PERIC0_USI8_USI,
4220 DIV_F(CLK_DOUT_PERIC1_USI0_USI,
[all …]
H A Dclk-exynos5433.c513 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
515 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
3319 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3610 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3613 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3616 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3619 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3622 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3625 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3627 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
[all …]
H A Dclk-exynos4.c644 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
660 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
662 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
664 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
666 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
668 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
689 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
H A Dclk-exynos5420.c817 DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
843 DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
845 DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
847 DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
850 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
924 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
926 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
H A Dclk.h196 #define DIV_F(_id, cname, pname, o, s, w, f, df) \ macro