1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
9 #define _ASM_X86_AMD_IOMMU_TYPES_H
10
11 #include <linux/bitfield.h>
12 #include <linux/iommu.h>
13 #include <linux/types.h>
14 #include <linux/mmu_notifier.h>
15 #include <linux/mutex.h>
16 #include <linux/msi.h>
17 #include <linux/list.h>
18 #include <linux/sizes.h>
19 #include <linux/spinlock.h>
20 #include <linux/pci.h>
21 #include <linux/iommufd.h>
22 #include <linux/irqreturn.h>
23 #include <linux/generic_pt/iommu.h>
24
25 #include <uapi/linux/iommufd.h>
26
27 /*
28 * Maximum number of IOMMUs supported
29 */
30 #define MAX_IOMMUS 32
31
32 /*
33 * some size calculation constants
34 */
35 #define DEV_TABLE_ENTRY_SIZE 32
36
37 /* Capability offsets used by the driver */
38 #define MMIO_CAP_HDR_OFFSET 0x00
39 #define MMIO_RANGE_OFFSET 0x0c
40 #define MMIO_MISC_OFFSET 0x10
41
42 /* Masks, shifts and macros to parse the device range capability */
43 #define MMIO_RANGE_LD_MASK 0xff000000
44 #define MMIO_RANGE_FD_MASK 0x00ff0000
45 #define MMIO_RANGE_BUS_MASK 0x0000ff00
46 #define MMIO_RANGE_LD_SHIFT 24
47 #define MMIO_RANGE_FD_SHIFT 16
48 #define MMIO_RANGE_BUS_SHIFT 8
49 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
50 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
51 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
52 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
53
54 /* Flag masks for the AMD IOMMU exclusion range */
55 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
56 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
57
58 /* Used offsets into the MMIO space */
59 #define MMIO_DEV_TABLE_OFFSET 0x0000
60 #define MMIO_CMD_BUF_OFFSET 0x0008
61 #define MMIO_EVT_BUF_OFFSET 0x0010
62 #define MMIO_CONTROL_OFFSET 0x0018
63 #define MMIO_EXCL_BASE_OFFSET 0x0020
64 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
65 #define MMIO_EXT_FEATURES 0x0030
66 #define MMIO_PPR_LOG_OFFSET 0x0038
67 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
68 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
69 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C
70 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160
71 #define MMIO_MSI_DATA_OFFSET 0x0164
72 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170
73 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178
74 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180
75 #define MMIO_EXT_FEATURES2 0x01A0
76 #define MMIO_CMD_HEAD_OFFSET 0x2000
77 #define MMIO_CMD_TAIL_OFFSET 0x2008
78 #define MMIO_EVT_HEAD_OFFSET 0x2010
79 #define MMIO_EVT_TAIL_OFFSET 0x2018
80 #define MMIO_STATUS_OFFSET 0x2020
81 #define MMIO_PPR_HEAD_OFFSET 0x2030
82 #define MMIO_PPR_TAIL_OFFSET 0x2038
83 #define MMIO_GA_HEAD_OFFSET 0x2040
84 #define MMIO_GA_TAIL_OFFSET 0x2048
85 #define MMIO_CNTR_CONF_OFFSET 0x4000
86 #define MMIO_CNTR_REG_OFFSET 0x40000
87 #define MMIO_REG_END_OFFSET 0x80000
88
89
90
91 /* Extended Feature Bits */
92 #define FEATURE_PREFETCH BIT_ULL(0)
93 #define FEATURE_PPR BIT_ULL(1)
94 #define FEATURE_X2APIC BIT_ULL(2)
95 #define FEATURE_NX BIT_ULL(3)
96 #define FEATURE_GT BIT_ULL(4)
97 #define FEATURE_IA BIT_ULL(6)
98 #define FEATURE_GA BIT_ULL(7)
99 #define FEATURE_HE BIT_ULL(8)
100 #define FEATURE_PC BIT_ULL(9)
101 #define FEATURE_HATS GENMASK_ULL(11, 10)
102 #define FEATURE_GATS GENMASK_ULL(13, 12)
103 #define FEATURE_GLX GENMASK_ULL(15, 14)
104 #define FEATURE_GAM_VAPIC BIT_ULL(21)
105 #define FEATURE_PASMAX GENMASK_ULL(36, 32)
106 #define FEATURE_GIOSUP BIT_ULL(48)
107 #define FEATURE_HASUP BIT_ULL(49)
108 #define FEATURE_EPHSUP BIT_ULL(50)
109 #define FEATURE_HDSUP BIT_ULL(52)
110 #define FEATURE_SNP BIT_ULL(63)
111
112
113 /* Extended Feature 2 Bits */
114 #define FEATURE_SEVSNPIO_SUP BIT_ULL(1)
115 #define FEATURE_GCR3TRPMODE BIT_ULL(3)
116 #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)
117 #define FEATURE_SNPAVICSUP_GAM(x) \
118 (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
119 #define FEATURE_HT_RANGE_IGNORE BIT_ULL(11)
120
121 #define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8)
122 #define FEATURE_NUM_INT_REMAP_SUP_2K(x) \
123 (FIELD_GET(FEATURE_NUM_INT_REMAP_SUP, x) == 0x1)
124
125 /* Note:
126 * The current driver only support 16-bit PASID.
127 * Currently, hardware only implement upto 16-bit PASID
128 * even though the spec says it could have upto 20 bits.
129 */
130 #define PASID_MASK 0x0000ffff
131
132 /* MMIO status bits */
133 #define MMIO_STATUS_EVT_OVERFLOW_MASK BIT(0)
134 #define MMIO_STATUS_EVT_INT_MASK BIT(1)
135 #define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2)
136 #define MMIO_STATUS_EVT_RUN_MASK BIT(3)
137 #define MMIO_STATUS_PPR_OVERFLOW_MASK BIT(5)
138 #define MMIO_STATUS_PPR_INT_MASK BIT(6)
139 #define MMIO_STATUS_PPR_RUN_MASK BIT(7)
140 #define MMIO_STATUS_GALOG_RUN_MASK BIT(8)
141 #define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9)
142 #define MMIO_STATUS_GALOG_INT_MASK BIT(10)
143
144 /* event logging constants */
145 #define EVENT_TYPE_SHIFT 28
146 #define EVENT_TYPE_MASK 0xf
147 #define EVENT_TYPE_ILL_DEV 0x1
148 #define EVENT_TYPE_IO_FAULT 0x2
149 #define EVENT_TYPE_DEV_TAB_ERR 0x3
150 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
151 #define EVENT_TYPE_ILL_CMD 0x5
152 #define EVENT_TYPE_CMD_HARD_ERR 0x6
153 #define EVENT_TYPE_IOTLB_INV_TO 0x7
154 #define EVENT_TYPE_INV_DEV_REQ 0x8
155 #define EVENT_TYPE_INV_PPR_REQ 0x9
156 #define EVENT_TYPE_RMP_FAULT 0xd
157 #define EVENT_TYPE_RMP_HW_ERR 0xe
158 #define EVENT_DEVID_MASK 0xffff
159 #define EVENT_DEVID_SHIFT 0
160 #define EVENT_DOMID_MASK_LO 0xffff
161 #define EVENT_DOMID_MASK_HI 0xf0000
162 #define EVENT_FLAGS_MASK 0xfff
163 #define EVENT_FLAGS_SHIFT 0x10
164 #define EVENT_FLAG_RW 0x020
165 #define EVENT_FLAG_I 0x008
166
167 /* feature control bits */
168 #define CONTROL_IOMMU_EN 0
169 #define CONTROL_HT_TUN_EN 1
170 #define CONTROL_EVT_LOG_EN 2
171 #define CONTROL_EVT_INT_EN 3
172 #define CONTROL_COMWAIT_EN 4
173 #define CONTROL_INV_TIMEOUT 5
174 #define CONTROL_PASSPW_EN 8
175 #define CONTROL_RESPASSPW_EN 9
176 #define CONTROL_COHERENT_EN 10
177 #define CONTROL_ISOC_EN 11
178 #define CONTROL_CMDBUF_EN 12
179 #define CONTROL_PPRLOG_EN 13
180 #define CONTROL_PPRINT_EN 14
181 #define CONTROL_PPR_EN 15
182 #define CONTROL_GT_EN 16
183 #define CONTROL_GA_EN 17
184 #define CONTROL_GAM_EN 25
185 #define CONTROL_GALOG_EN 28
186 #define CONTROL_GAINT_EN 29
187 #define CONTROL_NUM_INT_REMAP_MODE 43
188 #define CONTROL_NUM_INT_REMAP_MODE_MASK 0x03
189 #define CONTROL_NUM_INT_REMAP_MODE_2K 0x01
190 #define CONTROL_EPH_EN 45
191 #define CONTROL_XT_EN 50
192 #define CONTROL_INTCAPXT_EN 51
193 #define CONTROL_GCR3TRPMODE 58
194 #define CONTROL_IRTCACHEDIS 59
195 #define CONTROL_SNPAVIC_EN 61
196
197 #define CTRL_INV_TO_MASK 7
198 #define CTRL_INV_TO_NONE 0
199 #define CTRL_INV_TO_1MS 1
200 #define CTRL_INV_TO_10MS 2
201 #define CTRL_INV_TO_100MS 3
202 #define CTRL_INV_TO_1S 4
203 #define CTRL_INV_TO_10S 5
204 #define CTRL_INV_TO_100S 6
205
206 /* command specific defines */
207 #define CMD_COMPL_WAIT 0x01
208 #define CMD_INV_DEV_ENTRY 0x02
209 #define CMD_INV_IOMMU_PAGES 0x03
210 #define CMD_INV_IOTLB_PAGES 0x04
211 #define CMD_INV_IRT 0x05
212 #define CMD_COMPLETE_PPR 0x07
213 #define CMD_INV_ALL 0x08
214
215 #define CMD_COMPL_WAIT_STORE_MASK 0x01
216 #define CMD_COMPL_WAIT_INT_MASK 0x02
217 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
218 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
219 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
220
221 #define PPR_STATUS_MASK 0xf
222 #define PPR_STATUS_SHIFT 12
223
224 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
225
226 /* macros and definitions for device table entries */
227 #define DEV_ENTRY_VALID 0x00
228 #define DEV_ENTRY_TRANSLATION 0x01
229 #define DEV_ENTRY_HAD 0x07
230 #define DEV_ENTRY_PPR 0x34
231 #define DEV_ENTRY_IR 0x3d
232 #define DEV_ENTRY_IW 0x3e
233 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
234 #define DEV_ENTRY_EX 0x67
235 #define DEV_ENTRY_SYSMGT1 0x68
236 #define DEV_ENTRY_SYSMGT2 0x69
237 #define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40)
238
239 #define DEV_ENTRY_IRQ_TBL_EN 0x80
240 #define DEV_ENTRY_INIT_PASS 0xb8
241 #define DEV_ENTRY_EINT_PASS 0xb9
242 #define DEV_ENTRY_NMI_PASS 0xba
243 #define DEV_ENTRY_LINT0_PASS 0xbe
244 #define DEV_ENTRY_LINT1_PASS 0xbf
245 #define DEV_ENTRY_MODE_MASK 0x07
246 #define DEV_ENTRY_MODE_SHIFT 0x09
247
248 #define MAX_DEV_TABLE_ENTRIES 0xffff
249
250 /* constants to configure the command buffer */
251 #define CMD_BUFFER_SIZE 8192
252 #define CMD_BUFFER_UNINITIALIZED 1
253 #define CMD_BUFFER_ENTRIES 512
254 #define MMIO_CMD_SIZE_SHIFT 56
255 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
256 #define MMIO_CMD_HEAD_MASK GENMASK_ULL(18, 4) /* Command buffer head ptr field [18:4] */
257 #define MMIO_CMD_BUFFER_HEAD(x) FIELD_GET(MMIO_CMD_HEAD_MASK, (x))
258 #define MMIO_CMD_TAIL_MASK GENMASK_ULL(18, 4) /* Command buffer tail ptr field [18:4] */
259 #define MMIO_CMD_BUFFER_TAIL(x) FIELD_GET(MMIO_CMD_TAIL_MASK, (x))
260
261 /* constants for event buffer handling */
262 #define EVTLOG_ENTRY_SIZE 0x10
263 #define EVTLOG_SIZE_SHIFT 56
264 #define EVTLOG_SIZE_DEF SZ_8K /* 512 entries */
265 #define EVTLOG_LEN_MASK_DEF (0x9ULL << EVTLOG_SIZE_SHIFT)
266 #define EVTLOG_SIZE_MAX SZ_512K /* 32K entries */
267 #define EVTLOG_LEN_MASK_MAX (0xFULL << EVTLOG_SIZE_SHIFT)
268
269 /* Constants for PPR Log handling */
270 #define PPRLOG_ENTRY_SIZE 0x10
271 #define PPRLOG_SIZE_SHIFT 56
272 #define PPRLOG_SIZE_DEF SZ_8K /* 512 entries */
273 #define PPRLOG_LEN_MASK_DEF (0x9ULL << PPRLOG_SIZE_SHIFT)
274 #define PPRLOG_SIZE_MAX SZ_512K /* 32K entries */
275 #define PPRLOG_LEN_MASK_MAX (0xFULL << PPRLOG_SIZE_SHIFT)
276
277 /* PAGE_SERVICE_REQUEST PPR Log Buffer Entry flags */
278 #define PPR_FLAG_EXEC 0x002 /* Execute permission requested */
279 #define PPR_FLAG_READ 0x004 /* Read permission requested */
280 #define PPR_FLAG_WRITE 0x020 /* Write permission requested */
281 #define PPR_FLAG_US 0x040 /* 1: User, 0: Supervisor */
282 #define PPR_FLAG_RVSD 0x080 /* Reserved bit not zero */
283 #define PPR_FLAG_GN 0x100 /* GVA and PASID is valid */
284
285 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
286 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
287 #define PPR_DEVID(x) ((x) & 0xffffULL)
288 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
289 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
290 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
291 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
292
293 #define PPR_REQ_FAULT 0x01
294
295 /* Constants for GA Log handling */
296 #define GA_LOG_ENTRIES 512
297 #define GA_LOG_SIZE_SHIFT 56
298 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
299 #define GA_ENTRY_SIZE 8
300 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
301
302 #define GA_TAG(x) (u32)(x & 0xffffffffULL)
303 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
304 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
305
306 #define GA_GUEST_NR 0x1
307
308 #define IOMMU_IN_ADDR_BIT_SIZE 52
309 #define IOMMU_OUT_ADDR_BIT_SIZE 52
310
311 /*
312 * This bitmap is used to advertise the page sizes our hardware support
313 * to the IOMMU core, which will then use this information to split
314 * physically contiguous memory regions it is mapping into page sizes
315 * that we support.
316 *
317 * 512GB Pages are not supported due to a hardware bug
318 * Page sizes >= the 52 bit max physical address of the CPU are not supported.
319 */
320 #define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)
321
322 /* Special mode where page-sizes are limited to 4 KiB */
323 #define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE)
324
325 /* 4K, 2MB, 1G page sizes are supported */
326 #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
327
328 /* Bit value definition for dte irq remapping fields*/
329 #define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6)
330 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
331 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
332 #define DTE_IRQ_REMAP_ENABLE 1ULL
333
334 #define DTE_INTTAB_ALIGNMENT 128
335 #define DTE_INTTABLEN_MASK (0xfULL << 1)
336 #define DTE_INTTABLEN_VALUE_512 9ULL
337 #define DTE_INTTABLEN_512 (DTE_INTTABLEN_VALUE_512 << 1)
338 #define MAX_IRQS_PER_TABLE_512 BIT(DTE_INTTABLEN_VALUE_512)
339 #define DTE_INTTABLEN_VALUE_2K 11ULL
340 #define DTE_INTTABLEN_2K (DTE_INTTABLEN_VALUE_2K << 1)
341 #define MAX_IRQS_PER_TABLE_2K BIT(DTE_INTTABLEN_VALUE_2K)
342
343 #define PAGE_MODE_NONE 0x00
344 #define PAGE_MODE_1_LEVEL 0x01
345 #define PAGE_MODE_2_LEVEL 0x02
346 #define PAGE_MODE_3_LEVEL 0x03
347 #define PAGE_MODE_4_LEVEL 0x04
348 #define PAGE_MODE_5_LEVEL 0x05
349 #define PAGE_MODE_6_LEVEL 0x06
350 #define PAGE_MODE_7_LEVEL 0x07
351
352 #define GUEST_PGTABLE_4_LEVEL 0x00
353 #define GUEST_PGTABLE_5_LEVEL 0x01
354
355 #define PM_ADDR_MASK 0x000ffffffffff000ULL
356
357 /*
358 * Bit value definition for DTE fields
359 */
360 #define DTE_FLAG_V BIT_ULL(0)
361 #define DTE_FLAG_TV BIT_ULL(1)
362 #define DTE_FLAG_HAD (3ULL << 7)
363 #define DTE_MODE_MASK GENMASK_ULL(11, 9)
364 #define DTE_HOST_TRP GENMASK_ULL(51, 12)
365 #define DTE_FLAG_PPR BIT_ULL(52)
366 #define DTE_FLAG_GIOV BIT_ULL(54)
367 #define DTE_FLAG_GV BIT_ULL(55)
368 #define DTE_GLX GENMASK_ULL(57, 56)
369 #define DTE_FLAG_IR BIT_ULL(61)
370 #define DTE_FLAG_IW BIT_ULL(62)
371
372 #define DTE_FLAG_IOTLB BIT_ULL(32)
373 #define DTE_FLAG_MASK (0x3ffULL << 32)
374 #define DTE_DOMID_MASK GENMASK_ULL(15, 0)
375
376 #define DTE_GCR3_14_12 GENMASK_ULL(60, 58)
377 #define DTE_GCR3_30_15 GENMASK_ULL(31, 16)
378 #define DTE_GCR3_51_31 GENMASK_ULL(63, 43)
379
380 #define DTE_GPT_LEVEL_SHIFT 54
381 #define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54)
382
383 #define GCR3_VALID 0x01ULL
384
385 /* DTE[128:179] | DTE[184:191] */
386 #define DTE_DATA2_INTR_MASK ~GENMASK_ULL(55, 52)
387
388 #define IOMMU_PROT_MASK 0x03
389 #define IOMMU_PROT_IR 0x01
390 #define IOMMU_PROT_IW 0x02
391
392 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
393
394 /* IOMMU capabilities */
395 #define IOMMU_CAP_IOTLB 24
396 #define IOMMU_CAP_NPCACHE 26
397 #define IOMMU_CAP_EFR 27
398
399 /* IOMMU IVINFO */
400 #define IOMMU_IVINFO_OFFSET 36
401 #define IOMMU_IVINFO_EFRSUP BIT(0)
402 #define IOMMU_IVINFO_DMA_REMAP BIT(1)
403
404 /* IOMMU Feature Reporting Field (for IVHD type 10h */
405 #define IOMMU_FEAT_GASUP_SHIFT 6
406
407 /* IOMMU HATDIS for IVHD type 11h and 40h */
408 #define IOMMU_IVHD_ATTR_HATDIS_SHIFT 0
409
410 /* IOMMU Extended Feature Register (EFR) */
411 #define IOMMU_EFR_XTSUP_SHIFT 2
412 #define IOMMU_EFR_GASUP_SHIFT 7
413 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46
414
415 #define MAX_DOMAIN_ID 65536
416
417 /* Timeout stuff */
418 #define LOOP_TIMEOUT 100000
419 #define MMIO_STATUS_TIMEOUT 2000000
420
421 extern bool amd_iommu_dump;
422 #define DUMP_printk(format, arg...) \
423 do { \
424 if (amd_iommu_dump) \
425 pr_info(format, ## arg); \
426 } while(0);
427
428 /* global flag if IOMMUs cache non-present entries */
429 extern bool amd_iommu_np_cache;
430 /* Only true if all IOMMUs support device IOTLBs */
431 extern bool amd_iommu_iotlb_sup;
432
433 struct irq_remap_table {
434 raw_spinlock_t lock;
435 unsigned min_index;
436 u32 *table;
437 };
438
439 /* Interrupt remapping feature used? */
440 extern bool amd_iommu_irq_remap;
441
442 extern const struct iommu_ops amd_iommu_ops;
443
444 /* IVRS indicates that pre-boot remapping was enabled */
445 extern bool amdr_ivrs_remap_support;
446
447 #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff)
448 #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff)
449 #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) | \
450 ((devid) & 0xffff))
451
452 /* Make iterating over all pci segment easier */
453 #define for_each_pci_segment(pci_seg) \
454 list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list)
455 #define for_each_pci_segment_safe(pci_seg, next) \
456 list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list)
457 /*
458 * Make iterating over all IOMMUs easier
459 */
460 #define for_each_iommu(iommu) \
461 list_for_each_entry((iommu), &amd_iommu_list, list)
462 #define for_each_iommu_safe(iommu, next) \
463 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
464 /* Making iterating over protection_domain->dev_data_list easier */
465 #define for_each_pdom_dev_data(pdom_dev_data, pdom) \
466 list_for_each_entry(pdom_dev_data, &pdom->dev_data_list, list)
467 #define for_each_pdom_dev_data_safe(pdom_dev_data, next, pdom) \
468 list_for_each_entry_safe((pdom_dev_data), (next), &pdom->dev_data_list, list)
469
470 #define for_each_ivhd_dte_flags(entry) \
471 list_for_each_entry((entry), &amd_ivhd_dev_flags_list, list)
472
473 struct amd_iommu;
474 struct iommu_domain;
475 struct irq_domain;
476 struct amd_irte_ops;
477
478 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
479
480 struct gcr3_tbl_info {
481 u64 *gcr3_tbl; /* Guest CR3 table */
482 int glx; /* Number of levels for GCR3 table */
483 u32 pasid_cnt; /* Track attached PASIDs */
484 u16 domid; /* Per device domain ID */
485 };
486
487 enum protection_domain_mode {
488 PD_MODE_NONE,
489 PD_MODE_V1,
490 PD_MODE_V2,
491 };
492
493 /* Track dev_data/PASID list for the protection domain */
494 struct pdom_dev_data {
495 /* Points to attached device data */
496 struct iommu_dev_data *dev_data;
497 /* PASID attached to the protection domain */
498 ioasid_t pasid;
499 /* For protection_domain->dev_data_list */
500 struct list_head list;
501 };
502
503 /* Keeps track of the IOMMUs attached to protection domain */
504 struct pdom_iommu_info {
505 struct amd_iommu *iommu; /* IOMMUs attach to protection domain */
506 u32 refcnt; /* Count of attached dev/pasid per domain/IOMMU */
507 };
508
509 struct amd_iommu_viommu {
510 struct iommufd_viommu core;
511 struct protection_domain *parent; /* nest parent domain for this viommu */
512 struct list_head pdom_list; /* For protection_domain->viommu_list */
513
514 /*
515 * Per-vIOMMU guest domain ID to host domain ID mapping.
516 * Indexed by guest domain ID.
517 */
518 struct xarray gdomid_array;
519 };
520
521 /*
522 * Contains guest domain ID mapping info,
523 * which is stored in the struct xarray gdomid_array.
524 */
525 struct guest_domain_mapping_info {
526 refcount_t users;
527 u32 hdom_id; /* Host domain ID */
528 };
529
530 /*
531 * Nested domain is specifically used for nested translation
532 */
533 struct nested_domain {
534 struct iommu_domain domain; /* generic domain handle used by iommu core code */
535 u16 gdom_id; /* domain ID from gDTE */
536 struct guest_domain_mapping_info *gdom_info;
537 struct iommu_hwpt_amd_guest gdte; /* Guest vIOMMU DTE */
538 struct amd_iommu_viommu *viommu; /* AMD hw-viommu this nested domain belong to */
539 };
540
541 /*
542 * This structure contains generic data for IOMMU protection domains
543 * independent of their use.
544 */
545 struct protection_domain {
546 union {
547 struct iommu_domain domain;
548 struct pt_iommu iommu;
549 struct pt_iommu_amdv1 amdv1;
550 struct pt_iommu_x86_64 amdv2;
551 };
552 struct list_head dev_list; /* List of all devices in this domain */
553 spinlock_t lock; /* mostly used to lock the page table*/
554 u16 id; /* the domain id written to the device table */
555 enum protection_domain_mode pd_mode; /* Track page table type */
556 bool dirty_tracking; /* dirty tracking is enabled in the domain */
557 struct xarray iommu_array; /* per-IOMMU reference count */
558
559 struct mmu_notifier mn; /* mmu notifier for the SVA domain */
560 struct list_head dev_data_list; /* List of pdom_dev_data */
561
562 /*
563 * Store reference to list of vIOMMUs, which use this protection domain.
564 * This will be used to look up host domain ID when flushing this domain.
565 */
566 struct list_head viommu_list;
567 };
568 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, iommu, domain);
569 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv1.iommu, domain);
570 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv2.iommu, domain);
571
572 /*
573 * This structure contains information about one PCI segment in the system.
574 */
575 struct amd_iommu_pci_seg {
576 /* List with all PCI segments in the system */
577 struct list_head list;
578
579 /* List of all available dev_data structures */
580 struct llist_head dev_data_list;
581
582 /* PCI segment number */
583 u16 id;
584
585 /* Largest PCI device id we expect translation requests for */
586 u16 last_bdf;
587
588 /* Size of the device table */
589 u32 dev_table_size;
590
591 /*
592 * device table virtual address
593 *
594 * Pointer to the per PCI segment device table.
595 * It is indexed by the PCI device id or the HT unit id and contains
596 * information about the domain the device belongs to as well as the
597 * page table root pointer.
598 */
599 struct dev_table_entry *dev_table;
600
601 /*
602 * The rlookup iommu table is used to find the IOMMU which is
603 * responsible for a specific device. It is indexed by the PCI
604 * device id.
605 */
606 struct amd_iommu **rlookup_table;
607
608 /*
609 * This table is used to find the irq remapping table for a given
610 * device id quickly.
611 */
612 struct irq_remap_table **irq_lookup_table;
613
614 /*
615 * Pointer to a device table which the content of old device table
616 * will be copied to. It's only be used in kdump kernel.
617 */
618 struct dev_table_entry *old_dev_tbl_cpy;
619
620 /*
621 * The alias table is a driver specific data structure which contains the
622 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
623 * More than one device can share the same requestor id.
624 */
625 u16 *alias_table;
626
627 /*
628 * A list of required unity mappings we find in ACPI. It is not locked
629 * because as runtime it is only read. It is created at ACPI table
630 * parsing time.
631 */
632 struct list_head unity_map;
633 };
634
635 /*
636 * Structure where we save information about one hardware AMD IOMMU in the
637 * system.
638 */
639 struct amd_iommu {
640 struct list_head list;
641
642 /* Index within the IOMMU array */
643 int index;
644
645 /* locks the accesses to the hardware */
646 raw_spinlock_t lock;
647
648 /* Pointer to PCI device of this IOMMU */
649 struct pci_dev *dev;
650
651 /* Cache pdev to root device for resume quirks */
652 struct pci_dev *root_pdev;
653
654 /* physical address of MMIO space */
655 u64 mmio_phys;
656
657 /* physical end address of MMIO space */
658 u64 mmio_phys_end;
659
660 /* virtual address of MMIO space */
661 u8 __iomem *mmio_base;
662
663 /* capabilities of that IOMMU read from ACPI */
664 u32 cap;
665
666 /* flags read from acpi table */
667 u8 acpi_flags;
668
669 /* Extended features */
670 u64 features;
671
672 /* Extended features 2 */
673 u64 features2;
674
675 /* PCI device id of the IOMMU device */
676 u16 devid;
677
678 /*
679 * Capability pointer. There could be more than one IOMMU per PCI
680 * device function if there are more than one AMD IOMMU capability
681 * pointers.
682 */
683 u16 cap_ptr;
684
685 /* pci domain of this IOMMU */
686 struct amd_iommu_pci_seg *pci_seg;
687
688 /* start of exclusion range of that IOMMU */
689 u64 exclusion_start;
690 /* length of exclusion range of that IOMMU */
691 u64 exclusion_length;
692
693 /* command buffer virtual address */
694 u8 *cmd_buf;
695 u32 cmd_buf_head;
696 u32 cmd_buf_tail;
697
698 /* event buffer virtual address */
699 u8 *evt_buf;
700
701 /* Name for event log interrupt */
702 unsigned char evt_irq_name[16];
703
704 /* Base of the PPR log, if present */
705 u8 *ppr_log;
706
707 /* Name for PPR log interrupt */
708 unsigned char ppr_irq_name[16];
709
710 /* Base of the GA log, if present */
711 u8 *ga_log;
712
713 /* Name for GA log interrupt */
714 unsigned char ga_irq_name[16];
715
716 /* Tail of the GA log, if present */
717 u8 *ga_log_tail;
718
719 /* true if interrupts for this IOMMU are already enabled */
720 bool int_enabled;
721
722 /* if one, we need to send a completion wait command */
723 bool need_sync;
724
725 /* true if disable irte caching */
726 bool irtcachedis_enabled;
727
728 /* Handle for IOMMU core code */
729 struct iommu_device iommu;
730
731 /*
732 * We can't rely on the BIOS to restore all values on reinit, so we
733 * need to stash them
734 */
735
736 /* The iommu BAR */
737 u32 stored_addr_lo;
738 u32 stored_addr_hi;
739
740 /*
741 * Each iommu has 6 l1s, each of which is documented as having 0x12
742 * registers
743 */
744 u32 stored_l1[6][0x12];
745
746 /* The l2 indirect registers */
747 u32 stored_l2[0x83];
748
749 /* The maximum PC banks and counters/bank (PCSup=1) */
750 u8 max_banks;
751 u8 max_counters;
752 #ifdef CONFIG_IRQ_REMAP
753 struct irq_domain *ir_domain;
754
755 struct amd_irte_ops *irte_ops;
756 #endif
757
758 u32 flags;
759 volatile u64 *cmd_sem;
760 u64 cmd_sem_val;
761 /*
762 * Track physical address to directly use it in build_completion_wait()
763 * and avoid adding any special checks and handling for kdump.
764 */
765 u64 cmd_sem_paddr;
766
767 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
768 /* DebugFS Info */
769 struct dentry *debugfs;
770 int dbg_mmio_offset;
771 int dbg_cap_offset;
772 #endif
773
774 /* IOPF support */
775 struct iopf_queue *iopf_queue;
776 unsigned char iopfq_name[32];
777 };
778
dev_to_amd_iommu(struct device * dev)779 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
780 {
781 struct iommu_device *iommu = dev_to_iommu_device(dev);
782
783 return container_of(iommu, struct amd_iommu, iommu);
784 }
785
786 #define ACPIHID_UID_LEN 256
787 #define ACPIHID_HID_LEN 9
788
789 struct acpihid_map_entry {
790 struct list_head list;
791 u8 uid[ACPIHID_UID_LEN];
792 u8 hid[ACPIHID_HID_LEN];
793 u32 devid;
794 u32 root_devid;
795 bool cmd_line;
796 struct iommu_group *group;
797 };
798
799 struct devid_map {
800 struct list_head list;
801 u8 id;
802 u32 devid;
803 bool cmd_line;
804 };
805
806 #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
807 #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
808 #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
809 /* Device may request execution on memory pages */
810 #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8
811 /* Device may request super-user privileges */
812 #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10
813
814 /*
815 * This struct contains device specific data for the IOMMU
816 */
817 struct iommu_dev_data {
818 /*Protect against attach/detach races */
819 struct mutex mutex;
820 spinlock_t dte_lock; /* DTE lock for 256-bit access */
821
822 struct list_head list; /* For domain->dev_list */
823 struct llist_node dev_data_list; /* For global dev_data_list */
824 struct protection_domain *domain; /* Domain the device is bound to */
825 struct gcr3_tbl_info gcr3_info; /* Per-device GCR3 table */
826 struct device *dev;
827 u16 devid; /* PCI Device ID */
828
829 unsigned int max_irqs; /* Maximum IRQs supported by device */
830 u32 max_pasids; /* Max supported PASIDs */
831 u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */
832 int ats_qdep;
833 u8 ats_enabled :1; /* ATS state */
834 u8 pri_enabled :1; /* PRI state */
835 u8 pasid_enabled:1; /* PASID state */
836 u8 pri_tlp :1; /* PASID TLB required for
837 PPR completions */
838 u8 ppr :1; /* Enable device PPR support */
839 bool use_vapic; /* Enable device to use vapic mode */
840 bool defer_attach;
841
842 struct ratelimit_state rs; /* Ratelimit IOPF messages */
843 };
844
845 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
846 extern struct list_head ioapic_map;
847 extern struct list_head hpet_map;
848 extern struct list_head acpihid_map;
849
850 /*
851 * List with all PCI segments in the system. This list is not locked because
852 * it is only written at driver initialization time
853 */
854 extern struct list_head amd_iommu_pci_seg_list;
855
856 /*
857 * List with all IOMMUs in the system. This list is not locked because it is
858 * only written and read at driver initialization or suspend time
859 */
860 extern struct list_head amd_iommu_list;
861
862 /*
863 * Structure defining one entry in the device table
864 */
865 struct dev_table_entry {
866 union {
867 u64 data[4];
868 u128 data128[2];
869 };
870 };
871
872 /*
873 * Structure defining one entry in the command buffer
874 */
875 struct iommu_cmd {
876 u32 data[4];
877 };
878
879 /*
880 * Structure to sture persistent DTE flags from IVHD
881 */
882 struct ivhd_dte_flags {
883 struct list_head list;
884 u16 segid;
885 u16 devid_first;
886 u16 devid_last;
887 struct dev_table_entry dte;
888 };
889
890 /*
891 * One entry for unity mappings parsed out of the ACPI table.
892 */
893 struct unity_map_entry {
894 struct list_head list;
895
896 /* starting device id this entry is used for (including) */
897 u16 devid_start;
898 /* end device id this entry is used for (including) */
899 u16 devid_end;
900
901 /* start address to unity map (including) */
902 u64 address_start;
903 /* end address to unity map (including) */
904 u64 address_end;
905
906 /* required protection */
907 int prot;
908 };
909
910 /*
911 * Data structures for device handling
912 */
913
914 extern bool amd_iommu_force_isolation;
915
916 /* Max levels of glxval supported */
917 extern int amd_iommu_max_glx_val;
918
919 /* IDA to track protection domain IDs */
920 extern struct ida pdom_ids;
921
922 /* Global EFR and EFR2 registers */
923 extern u64 amd_iommu_efr;
924 extern u64 amd_iommu_efr2;
925
get_ioapic_devid(int id)926 static inline int get_ioapic_devid(int id)
927 {
928 struct devid_map *entry;
929
930 list_for_each_entry(entry, &ioapic_map, list) {
931 if (entry->id == id)
932 return entry->devid;
933 }
934
935 return -EINVAL;
936 }
937
get_hpet_devid(int id)938 static inline int get_hpet_devid(int id)
939 {
940 struct devid_map *entry;
941
942 list_for_each_entry(entry, &hpet_map, list) {
943 if (entry->id == id)
944 return entry->devid;
945 }
946
947 return -EINVAL;
948 }
949
950 enum amd_iommu_intr_mode_type {
951 AMD_IOMMU_GUEST_IR_LEGACY,
952
953 /* This mode is not visible to users. It is used when
954 * we cannot fully enable vAPIC and fallback to only support
955 * legacy interrupt remapping via 128-bit IRTE.
956 */
957 AMD_IOMMU_GUEST_IR_LEGACY_GA,
958 AMD_IOMMU_GUEST_IR_VAPIC,
959 };
960
961 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
962 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
963
964 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
965
966 union irte {
967 u32 val;
968 struct {
969 u32 valid : 1,
970 no_fault : 1,
971 int_type : 3,
972 rq_eoi : 1,
973 dm : 1,
974 rsvd_1 : 1,
975 destination : 8,
976 vector : 8,
977 rsvd_2 : 8;
978 } fields;
979 };
980
981 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
982 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
983
984 union irte_ga_lo {
985 u64 val;
986
987 /* For int remapping */
988 struct {
989 u64 valid : 1,
990 no_fault : 1,
991 /* ------ */
992 int_type : 3,
993 rq_eoi : 1,
994 dm : 1,
995 /* ------ */
996 guest_mode : 1,
997 destination : 24,
998 ga_tag : 32;
999 } fields_remap;
1000
1001 /* For guest vAPIC */
1002 struct {
1003 u64 valid : 1,
1004 no_fault : 1,
1005 /* ------ */
1006 ga_log_intr : 1,
1007 rsvd1 : 3,
1008 is_run : 1,
1009 /* ------ */
1010 guest_mode : 1,
1011 destination : 24,
1012 ga_tag : 32;
1013 } fields_vapic;
1014 };
1015
1016 union irte_ga_hi {
1017 u64 val;
1018 struct {
1019 u64 vector : 8,
1020 rsvd_1 : 4,
1021 ga_root_ptr : 40,
1022 rsvd_2 : 4,
1023 destination : 8;
1024 } fields;
1025 };
1026
1027 struct irte_ga {
1028 union {
1029 struct {
1030 union irte_ga_lo lo;
1031 union irte_ga_hi hi;
1032 };
1033 u128 irte;
1034 };
1035 };
1036
1037 struct irq_2_irte {
1038 u16 devid; /* Device ID for IRTE table */
1039 u16 index; /* Index into IRTE table*/
1040 };
1041
1042 struct amd_ir_data {
1043 struct amd_iommu *iommu;
1044 struct irq_2_irte irq_2_irte;
1045 struct msi_msg msi_entry;
1046 void *entry; /* Pointer to union irte or struct irte_ga */
1047
1048 /**
1049 * Store information for activate/de-activate
1050 * Guest virtual APIC mode during runtime.
1051 */
1052 struct irq_cfg *cfg;
1053 int ga_vector;
1054 u64 ga_root_ptr;
1055 u32 ga_tag;
1056 };
1057
1058 struct amd_irte_ops {
1059 void (*prepare)(void *, u32, bool, u8, u32, int);
1060 void (*activate)(struct amd_iommu *iommu, void *, u16, u16);
1061 void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16);
1062 void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32);
1063 void *(*get)(struct irq_remap_table *, int);
1064 void (*set_allocated)(struct irq_remap_table *, int);
1065 bool (*is_allocated)(struct irq_remap_table *, int);
1066 void (*clear_allocated)(struct irq_remap_table *, int);
1067 };
1068
1069 #ifdef CONFIG_IRQ_REMAP
1070 extern struct amd_irte_ops irte_32_ops;
1071 extern struct amd_irte_ops irte_128_ops;
1072 #endif
1073
1074 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
1075