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Searched refs:DEF_RST (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/renesas/
H A Dr9a09g057-cpg.c470 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
471 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
472 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
473 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
474 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
475 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
476 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
477 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
478 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
479 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
[all …]
H A Dr9a09g047-cpg.c444 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
445 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
446 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
447 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
448 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
449 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
450 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
451 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
452 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
453 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
[all …]
H A Dr9a09g056-cpg.c403 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
404 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
405 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
406 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
407 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
408 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
409 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
410 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
411 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
412 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
[all …]
H A Dr9a07g044-cpg.c420 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
421 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
422 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
423 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
424 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
425 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
426 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
427 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
428 DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
429 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
[all …]
H A Dr9a07g043-cpg.c309 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
310 DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
311 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
314 DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
316 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
317 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
318 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
319 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
320 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
321 DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
[all …]
H A Dr9a08g045-cpg.c309 DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
310 DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
311 DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
312 DEF_RST(R9A08G045_DMAC_ARESETN, 0x82c, 0),
313 DEF_RST(R9A08G045_DMAC_RST_ASYNC, 0x82c, 1),
314 DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0),
315 DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
316 DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
317 DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
318 DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0),
[all …]
H A Drzg2l-cpg.h258 #define DEF_RST(_id, _off, _bit) \ macro
H A Drzv2h-cpg.h324 #define DEF_RST(_resindex, _resbit, _monindex, _monbit) \ macro