1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Nuvoton NPCM7xx I2C Controller driver
4 *
5 * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
6 */
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/debugfs.h>
10 #include <linux/errno.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22
23 enum i2c_mode {
24 I2C_MASTER,
25 I2C_SLAVE,
26 };
27
28 /*
29 * External I2C Interface driver xfer indication values, which indicate status
30 * of the bus.
31 */
32 enum i2c_state_ind {
33 I2C_NO_STATUS_IND = 0,
34 I2C_SLAVE_RCV_IND,
35 I2C_SLAVE_XMIT_IND,
36 I2C_SLAVE_XMIT_MISSING_DATA_IND,
37 I2C_SLAVE_RESTART_IND,
38 I2C_SLAVE_DONE_IND,
39 I2C_MASTER_DONE_IND,
40 I2C_NACK_IND,
41 I2C_BUS_ERR_IND,
42 I2C_WAKE_UP_IND,
43 I2C_BLOCK_BYTES_ERR_IND,
44 I2C_SLAVE_RCV_MISSING_DATA_IND,
45 };
46
47 /*
48 * Operation type values (used to define the operation currently running)
49 * module is interrupt driven, on each interrupt the current operation is
50 * checked to see if the module is currently reading or writing.
51 */
52 enum i2c_oper {
53 I2C_NO_OPER = 0,
54 I2C_WRITE_OPER,
55 I2C_READ_OPER,
56 };
57
58 /* I2C Bank (module had 2 banks of registers) */
59 enum i2c_bank {
60 I2C_BANK_0 = 0,
61 I2C_BANK_1,
62 };
63
64 /* Internal I2C states values (for the I2C module state machine). */
65 enum i2c_state {
66 I2C_DISABLE = 0,
67 I2C_IDLE,
68 I2C_MASTER_START,
69 I2C_SLAVE_MATCH,
70 I2C_OPER_STARTED,
71 I2C_STOP_PENDING,
72 };
73
74 #if IS_ENABLED(CONFIG_I2C_SLAVE)
75 /* Module supports setting multiple own slave addresses */
76 enum i2c_addr {
77 I2C_SLAVE_ADDR1 = 0,
78 I2C_SLAVE_ADDR2,
79 I2C_SLAVE_ADDR3,
80 I2C_SLAVE_ADDR4,
81 I2C_SLAVE_ADDR5,
82 I2C_SLAVE_ADDR6,
83 I2C_SLAVE_ADDR7,
84 I2C_SLAVE_ADDR8,
85 I2C_SLAVE_ADDR9,
86 I2C_SLAVE_ADDR10,
87 I2C_GC_ADDR,
88 I2C_ARP_ADDR,
89 };
90 #endif
91
92 /* init register and default value required to enable module */
93 #define NPCM_I2CSEGCTL 0xE4
94
95 /* Common regs */
96 #define NPCM_I2CSDA 0x00
97 #define NPCM_I2CST 0x02
98 #define NPCM_I2CCST 0x04
99 #define NPCM_I2CCTL1 0x06
100 #define NPCM_I2CADDR1 0x08
101 #define NPCM_I2CCTL2 0x0A
102 #define NPCM_I2CADDR2 0x0C
103 #define NPCM_I2CCTL3 0x0E
104 #define NPCM_I2CCST2 0x18
105 #define NPCM_I2CCST3 0x19
106 #define I2C_VER 0x1F
107
108 /* BANK 0 regs */
109 #define NPCM_I2CADDR3 0x10
110 #define NPCM_I2CADDR7 0x11
111 #define NPCM_I2CADDR4 0x12
112 #define NPCM_I2CADDR8 0x13
113 #define NPCM_I2CADDR5 0x14
114 #define NPCM_I2CADDR9 0x15
115 #define NPCM_I2CADDR6 0x16
116 #define NPCM_I2CADDR10 0x17
117 #define NPCM_I2CCTL4 0x1A
118 #define NPCM_I2CCTL5 0x1B
119 #define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
120 #define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */
121 #define NPCM_I2CSCLHT 0x1E /* SCL High Time */
122
123 /* BANK 1 regs */
124 #define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */
125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
126 #define NPCM_I2CT_OUT 0x14 /* Bus T.O. */
127 #define NPCM_I2CPEC 0x16 /* PEC Data */
128 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
129 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
130 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
131
132 #if IS_ENABLED(CONFIG_I2C_SLAVE)
133 /*
134 * npcm_i2caddr array:
135 * The module supports having multiple own slave addresses.
136 * Since the addr regs are sprinkled all over the address space,
137 * use this array to get the address or each register.
138 */
139 #define I2C_NUM_OWN_ADDR 10
140 #define I2C_NUM_OWN_ADDR_SUPPORTED 2
141
142 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
143 NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4,
144 NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8,
145 NPCM_I2CADDR9, NPCM_I2CADDR10,
146 };
147 #endif
148
149 /* NPCM_I2CST reg fields */
150 #define NPCM_I2CST_XMIT BIT(0) /* Transmit mode */
151 #define NPCM_I2CST_MASTER BIT(1) /* Master mode */
152 #define NPCM_I2CST_NMATCH BIT(2) /* New match */
153 #define NPCM_I2CST_STASTR BIT(3) /* Stall after start */
154 #define NPCM_I2CST_NEGACK BIT(4) /* Negative ACK */
155 #define NPCM_I2CST_BER BIT(5) /* Bus error */
156 #define NPCM_I2CST_SDAST BIT(6) /* SDA status */
157 #define NPCM_I2CST_SLVSTP BIT(7) /* Slave stop */
158
159 /* NPCM_I2CCST reg fields */
160 #define NPCM_I2CCST_BUSY BIT(0) /* Busy */
161 #define NPCM_I2CCST_BB BIT(1) /* Bus busy */
162 #define NPCM_I2CCST_MATCH BIT(2) /* Address match */
163 #define NPCM_I2CCST_GCMATCH BIT(3) /* Global call match */
164 #define NPCM_I2CCST_TSDA BIT(4) /* Test SDA line */
165 #define NPCM_I2CCST_TGSCL BIT(5) /* Toggle SCL line */
166 #define NPCM_I2CCST_MATCHAF BIT(6) /* Match address field */
167 #define NPCM_I2CCST_ARPMATCH BIT(7) /* ARP address match */
168
169 /* NPCM_I2CCTL1 reg fields */
170 #define NPCM_I2CCTL1_START BIT(0) /* Generate start condition */
171 #define NPCM_I2CCTL1_STOP BIT(1) /* Generate stop condition */
172 #define NPCM_I2CCTL1_INTEN BIT(2) /* Interrupt enable */
173 #define NPCM_I2CCTL1_EOBINTE BIT(3)
174 #define NPCM_I2CCTL1_ACK BIT(4)
175 #define NPCM_I2CCTL1_GCMEN BIT(5) /* Global call match enable */
176 #define NPCM_I2CCTL1_NMINTE BIT(6) /* New match interrupt enable */
177 #define NPCM_I2CCTL1_STASTRE BIT(7) /* Stall after start enable */
178
179 /* RW1S fields (inside a RW reg): */
180 #define NPCM_I2CCTL1_RWS \
181 (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
182
183 /* npcm_i2caddr reg fields */
184 #define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */
185 #define NPCM_I2CADDR_SAEN BIT(7) /* Slave address enable */
186
187 /* NPCM_I2CCTL2 reg fields */
188 #define I2CCTL2_ENABLE BIT(0) /* Module enable */
189 #define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */
190
191 /* NPCM_I2CCTL3 reg fields */
192 #define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */
193 #define I2CCTL3_ARPMEN BIT(2) /* ARP match enable */
194 #define I2CCTL3_IDL_START BIT(3)
195 #define I2CCTL3_400K_MODE BIT(4)
196 #define I2CCTL3_BNK_SEL BIT(5)
197 #define I2CCTL3_SDA_LVL BIT(6)
198 #define I2CCTL3_SCL_LVL BIT(7)
199
200 /* NPCM_I2CCST2 reg fields */
201 #define NPCM_I2CCST2_MATCHA1F BIT(0)
202 #define NPCM_I2CCST2_MATCHA2F BIT(1)
203 #define NPCM_I2CCST2_MATCHA3F BIT(2)
204 #define NPCM_I2CCST2_MATCHA4F BIT(3)
205 #define NPCM_I2CCST2_MATCHA5F BIT(4)
206 #define NPCM_I2CCST2_MATCHA6F BIT(5)
207 #define NPCM_I2CCST2_MATCHA7F BIT(5)
208 #define NPCM_I2CCST2_INTSTS BIT(7)
209
210 /* NPCM_I2CCST3 reg fields */
211 #define NPCM_I2CCST3_MATCHA8F BIT(0)
212 #define NPCM_I2CCST3_MATCHA9F BIT(1)
213 #define NPCM_I2CCST3_MATCHA10F BIT(2)
214 #define NPCM_I2CCST3_EO_BUSY BIT(7)
215
216 /* NPCM_I2CCTL4 reg fields */
217 #define I2CCTL4_HLDT GENMASK(5, 0)
218 #define I2CCTL4_LVL_WE BIT(7)
219
220 /* NPCM_I2CCTL5 reg fields */
221 #define I2CCTL5_DBNCT GENMASK(3, 0)
222
223 /* NPCM_I2CFIF_CTS reg fields */
224 #define NPCM_I2CFIF_CTS_RXF_TXE BIT(1)
225 #define NPCM_I2CFIF_CTS_RFTE_IE BIT(3)
226 #define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6)
227 #define NPCM_I2CFIF_CTS_SLVRSTR BIT(7)
228
229 /* NPCM_I2CTXF_CTL reg field */
230 #define NPCM_I2CTXF_CTL_THR_TXIE BIT(6)
231
232 /* NPCM_I2CT_OUT reg fields */
233 #define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0)
234 #define NPCM_I2CT_OUT_T_OUTIE BIT(6)
235 #define NPCM_I2CT_OUT_T_OUTST BIT(7)
236
237 /* NPCM_I2CTXF_STS reg fields */
238 #define NPCM_I2CTXF_STS_TX_THST BIT(6)
239
240 /* NPCM_I2CRXF_STS reg fields */
241 #define NPCM_I2CRXF_STS_RX_THST BIT(6)
242
243 /* NPCM_I2CFIF_CTL reg fields */
244 #define NPCM_I2CFIF_CTL_FIFO_EN BIT(4)
245
246 /* NPCM_I2CRXF_CTL reg fields */
247 #define NPCM_I2CRXF_CTL_THR_RXIE BIT(6)
248
249 #define MAX_I2C_HW_FIFO_SIZE 32
250
251 /* I2C_VER reg fields */
252 #define I2C_VER_VERSION GENMASK(6, 0)
253 #define I2C_VER_FIFO_EN BIT(7)
254
255 /* stall/stuck timeout in us */
256 #define DEFAULT_STALL_COUNT 25
257
258 /* SCLFRQ field position */
259 #define SCLFRQ_0_TO_6 GENMASK(6, 0)
260 #define SCLFRQ_7_TO_8 GENMASK(8, 7)
261
262 /* supported clk settings. values in Hz. */
263 #define I2C_FREQ_MIN_HZ 10000
264 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ
265
266 struct npcm_i2c_data {
267 u8 fifo_size;
268 u32 segctl_init_val;
269 u8 txf_sts_tx_bytes;
270 u8 rxf_sts_rx_bytes;
271 u8 rxf_ctl_last_pec;
272 };
273
274 static const struct npcm_i2c_data npxm7xx_i2c_data = {
275 .fifo_size = 16,
276 .segctl_init_val = 0x0333F000,
277 .txf_sts_tx_bytes = GENMASK(4, 0),
278 .rxf_sts_rx_bytes = GENMASK(4, 0),
279 .rxf_ctl_last_pec = BIT(5),
280 };
281
282 static const struct npcm_i2c_data npxm8xx_i2c_data = {
283 .fifo_size = 32,
284 .segctl_init_val = 0x9333F000,
285 .txf_sts_tx_bytes = GENMASK(5, 0),
286 .rxf_sts_rx_bytes = GENMASK(5, 0),
287 .rxf_ctl_last_pec = BIT(7),
288 };
289
290 /* Status of one I2C module */
291 struct npcm_i2c {
292 struct i2c_adapter adap;
293 struct device *dev;
294 unsigned char __iomem *reg;
295 const struct npcm_i2c_data *data;
296 spinlock_t lock; /* IRQ synchronization */
297 struct completion cmd_complete;
298 int cmd_err;
299 struct i2c_msg *msgs;
300 int msgs_num;
301 int num;
302 u32 apb_clk;
303 struct i2c_bus_recovery_info rinfo;
304 enum i2c_state state;
305 enum i2c_oper operation;
306 enum i2c_mode master_or_slave;
307 enum i2c_state_ind stop_ind;
308 u8 dest_addr;
309 u8 *rd_buf;
310 u16 rd_size;
311 u16 rd_ind;
312 u8 *wr_buf;
313 u16 wr_size;
314 u16 wr_ind;
315 bool fifo_use;
316 u16 PEC_mask; /* PEC bit mask per slave address */
317 bool PEC_use;
318 bool read_block_use;
319 unsigned long int_time_stamp;
320 unsigned long bus_freq; /* in Hz */
321 #if IS_ENABLED(CONFIG_I2C_SLAVE)
322 u8 own_slave_addr;
323 struct i2c_client *slave;
324 int slv_rd_size;
325 int slv_rd_ind;
326 int slv_wr_size;
327 int slv_wr_ind;
328 u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];
329 u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];
330 #endif
331 u64 ber_cnt;
332 u64 rec_succ_cnt;
333 u64 rec_fail_cnt;
334 u64 nack_cnt;
335 u64 timeout_cnt;
336 u64 tx_complete_cnt;
337 bool ber_state; /* Indicate the bus error state */
338 };
339
npcm_i2c_select_bank(struct npcm_i2c * bus,enum i2c_bank bank)340 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
341 enum i2c_bank bank)
342 {
343 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
344
345 if (bank == I2C_BANK_0)
346 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
347 else
348 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
349 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
350 }
351
npcm_i2c_init_params(struct npcm_i2c * bus)352 static void npcm_i2c_init_params(struct npcm_i2c *bus)
353 {
354 bus->stop_ind = I2C_NO_STATUS_IND;
355 bus->rd_size = 0;
356 bus->wr_size = 0;
357 bus->rd_ind = 0;
358 bus->wr_ind = 0;
359 bus->read_block_use = false;
360 bus->int_time_stamp = 0;
361 bus->PEC_use = false;
362 bus->PEC_mask = 0;
363 #if IS_ENABLED(CONFIG_I2C_SLAVE)
364 if (bus->slave)
365 bus->master_or_slave = I2C_SLAVE;
366 #endif
367 }
368
npcm_i2c_wr_byte(struct npcm_i2c * bus,u8 data)369 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
370 {
371 iowrite8(data, bus->reg + NPCM_I2CSDA);
372 }
373
npcm_i2c_rd_byte(struct npcm_i2c * bus)374 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
375 {
376 return ioread8(bus->reg + NPCM_I2CSDA);
377 }
378
npcm_i2c_get_SCL(struct i2c_adapter * _adap)379 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
380 {
381 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
382
383 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
384 }
385
npcm_i2c_get_SDA(struct i2c_adapter * _adap)386 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
387 {
388 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
389
390 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
391 }
392
npcm_i2c_get_index(struct npcm_i2c * bus)393 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
394 {
395 if (bus->operation == I2C_READ_OPER)
396 return bus->rd_ind;
397 if (bus->operation == I2C_WRITE_OPER)
398 return bus->wr_ind;
399 return 0;
400 }
401
402 /* quick protocol (just address) */
npcm_i2c_is_quick(struct npcm_i2c * bus)403 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
404 {
405 return bus->wr_size == 0 && bus->rd_size == 0;
406 }
407
npcm_i2c_disable(struct npcm_i2c * bus)408 static void npcm_i2c_disable(struct npcm_i2c *bus)
409 {
410 u8 i2cctl2;
411
412 #if IS_ENABLED(CONFIG_I2C_SLAVE)
413 int i;
414
415 /* Slave addresses removal */
416 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
417 iowrite8(0, bus->reg + npcm_i2caddr[i]);
418
419 #endif
420 /* Disable module */
421 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
422 i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
423 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
424
425 bus->state = I2C_DISABLE;
426 }
427
npcm_i2c_enable(struct npcm_i2c * bus)428 static void npcm_i2c_enable(struct npcm_i2c *bus)
429 {
430 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
431
432 i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
433 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
434 bus->state = I2C_IDLE;
435 }
436
437 /* enable\disable end of busy (EOB) interrupts */
npcm_i2c_eob_int(struct npcm_i2c * bus,bool enable)438 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
439 {
440 u8 val;
441
442 /* Clear EO_BUSY pending bit: */
443 val = ioread8(bus->reg + NPCM_I2CCST3);
444 val = val | NPCM_I2CCST3_EO_BUSY;
445 iowrite8(val, bus->reg + NPCM_I2CCST3);
446
447 val = ioread8(bus->reg + NPCM_I2CCTL1);
448 val &= ~NPCM_I2CCTL1_RWS;
449 if (enable)
450 val |= NPCM_I2CCTL1_EOBINTE;
451 else
452 val &= ~NPCM_I2CCTL1_EOBINTE;
453 iowrite8(val, bus->reg + NPCM_I2CCTL1);
454 }
455
npcm_i2c_tx_fifo_empty(struct npcm_i2c * bus)456 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
457 {
458 u8 tx_fifo_sts;
459
460 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
461 /* check if TX FIFO is not empty */
462 if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
463 return false;
464
465 /* check if TX FIFO status bit is set: */
466 return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
467 }
468
npcm_i2c_rx_fifo_full(struct npcm_i2c * bus)469 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
470 {
471 u8 rx_fifo_sts;
472
473 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
474 /* check if RX FIFO is not empty: */
475 if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
476 return false;
477
478 /* check if rx fifo full status is set: */
479 return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
480 }
481
npcm_i2c_clear_fifo_int(struct npcm_i2c * bus)482 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
483 {
484 u8 val;
485
486 val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
487 val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
488 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
489 }
490
npcm_i2c_clear_tx_fifo(struct npcm_i2c * bus)491 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
492 {
493 u8 val;
494
495 val = ioread8(bus->reg + NPCM_I2CTXF_STS);
496 val = val | NPCM_I2CTXF_STS_TX_THST;
497 iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
498 }
499
npcm_i2c_clear_rx_fifo(struct npcm_i2c * bus)500 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
501 {
502 u8 val;
503
504 val = ioread8(bus->reg + NPCM_I2CRXF_STS);
505 val = val | NPCM_I2CRXF_STS_RX_THST;
506 iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
507 }
508
npcm_i2c_int_enable(struct npcm_i2c * bus,bool enable)509 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
510 {
511 u8 val;
512
513 val = ioread8(bus->reg + NPCM_I2CCTL1);
514 val &= ~NPCM_I2CCTL1_RWS;
515 if (enable)
516 val |= NPCM_I2CCTL1_INTEN;
517 else
518 val &= ~NPCM_I2CCTL1_INTEN;
519 iowrite8(val, bus->reg + NPCM_I2CCTL1);
520 }
521
npcm_i2c_master_start(struct npcm_i2c * bus)522 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
523 {
524 u8 val;
525
526 val = ioread8(bus->reg + NPCM_I2CCTL1);
527 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
528 val |= NPCM_I2CCTL1_START;
529 iowrite8(val, bus->reg + NPCM_I2CCTL1);
530 }
531
npcm_i2c_master_stop(struct npcm_i2c * bus)532 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
533 {
534 u8 val;
535
536 /*
537 * override HW issue: I2C may fail to supply stop condition in Master
538 * Write operation.
539 * Need to delay at least 5 us from the last int, before issueing a stop
540 */
541 udelay(10); /* function called from interrupt, can't sleep */
542 val = ioread8(bus->reg + NPCM_I2CCTL1);
543 val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
544 val |= NPCM_I2CCTL1_STOP;
545 iowrite8(val, bus->reg + NPCM_I2CCTL1);
546
547 if (!bus->fifo_use)
548 return;
549
550 npcm_i2c_select_bank(bus, I2C_BANK_1);
551
552 if (bus->operation == I2C_READ_OPER)
553 npcm_i2c_clear_rx_fifo(bus);
554 else
555 npcm_i2c_clear_tx_fifo(bus);
556 npcm_i2c_clear_fifo_int(bus);
557 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
558 }
559
npcm_i2c_stall_after_start(struct npcm_i2c * bus,bool stall)560 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
561 {
562 u8 val;
563
564 val = ioread8(bus->reg + NPCM_I2CCTL1);
565 val &= ~NPCM_I2CCTL1_RWS;
566 if (stall)
567 val |= NPCM_I2CCTL1_STASTRE;
568 else
569 val &= ~NPCM_I2CCTL1_STASTRE;
570 iowrite8(val, bus->reg + NPCM_I2CCTL1);
571 }
572
npcm_i2c_nack(struct npcm_i2c * bus)573 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
574 {
575 u8 val;
576
577 val = ioread8(bus->reg + NPCM_I2CCTL1);
578 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
579 val |= NPCM_I2CCTL1_ACK;
580 iowrite8(val, bus->reg + NPCM_I2CCTL1);
581 }
582
npcm_i2c_clear_master_status(struct npcm_i2c * bus)583 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
584 {
585 u8 val;
586
587 /* Clear NEGACK, STASTR and BER bits */
588 val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
589 iowrite8(val, bus->reg + NPCM_I2CST);
590 }
591
592 #if IS_ENABLED(CONFIG_I2C_SLAVE)
npcm_i2c_slave_int_enable(struct npcm_i2c * bus,bool enable)593 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
594 {
595 u8 i2cctl1;
596
597 /* enable interrupt on slave match: */
598 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
599 i2cctl1 &= ~NPCM_I2CCTL1_RWS;
600 if (enable)
601 i2cctl1 |= NPCM_I2CCTL1_NMINTE;
602 else
603 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
604 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
605 }
606
npcm_i2c_slave_enable(struct npcm_i2c * bus,enum i2c_addr addr_type,u8 addr,bool enable)607 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
608 u8 addr, bool enable)
609 {
610 u8 i2cctl1;
611 u8 i2cctl3;
612 u8 sa_reg;
613
614 sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
615 if (addr_type == I2C_GC_ADDR) {
616 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
617 if (enable)
618 i2cctl1 |= NPCM_I2CCTL1_GCMEN;
619 else
620 i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
621 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
622 return 0;
623 } else if (addr_type == I2C_ARP_ADDR) {
624 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
625 if (enable)
626 i2cctl3 |= I2CCTL3_ARPMEN;
627 else
628 i2cctl3 &= ~I2CCTL3_ARPMEN;
629 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
630 return 0;
631 }
632 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
633 dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
634
635 if (addr_type >= I2C_ARP_ADDR)
636 return -EFAULT;
637
638 /* Set and enable the address */
639 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
640 npcm_i2c_slave_int_enable(bus, enable);
641
642 return 0;
643 }
644 #endif
645
npcm_i2c_reset(struct npcm_i2c * bus)646 static void npcm_i2c_reset(struct npcm_i2c *bus)
647 {
648 /*
649 * Save I2CCTL1 relevant bits. It is being cleared when the module
650 * is disabled.
651 */
652 u8 i2cctl1;
653 #if IS_ENABLED(CONFIG_I2C_SLAVE)
654 u8 addr;
655 #endif
656
657 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
658
659 npcm_i2c_disable(bus);
660 npcm_i2c_enable(bus);
661
662 /* Restore NPCM_I2CCTL1 Status */
663 i2cctl1 &= ~NPCM_I2CCTL1_RWS;
664 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
665
666 /* Clear BB (BUS BUSY) bit */
667 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
668 iowrite8(0xFF, bus->reg + NPCM_I2CST);
669
670 /* Clear and disable EOB */
671 npcm_i2c_eob_int(bus, false);
672
673 /* Clear all fifo bits: */
674 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
675
676 #if IS_ENABLED(CONFIG_I2C_SLAVE)
677 if (bus->slave) {
678 addr = bus->slave->addr;
679 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
680 }
681 #endif
682
683 /* Clear status bits for spurious interrupts */
684 npcm_i2c_clear_master_status(bus);
685
686 bus->state = I2C_IDLE;
687 }
688
npcm_i2c_is_master(struct npcm_i2c * bus)689 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
690 {
691 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
692 }
693
npcm_i2c_callback(struct npcm_i2c * bus,enum i2c_state_ind op_status,u16 info)694 static void npcm_i2c_callback(struct npcm_i2c *bus,
695 enum i2c_state_ind op_status, u16 info)
696 {
697 struct i2c_msg *msgs;
698 int msgs_num;
699 bool do_complete = false;
700
701 msgs = bus->msgs;
702 msgs_num = bus->msgs_num;
703 /*
704 * check that transaction was not timed-out, and msgs still
705 * holds a valid value.
706 */
707 if (!msgs)
708 return;
709
710 if (completion_done(&bus->cmd_complete))
711 return;
712
713 switch (op_status) {
714 case I2C_MASTER_DONE_IND:
715 bus->cmd_err = bus->msgs_num;
716 if (bus->tx_complete_cnt < ULLONG_MAX)
717 bus->tx_complete_cnt++;
718 fallthrough;
719 case I2C_BLOCK_BYTES_ERR_IND:
720 /* Master tx finished and all transmit bytes were sent */
721 if (bus->msgs) {
722 if (msgs[0].flags & I2C_M_RD)
723 msgs[0].len = info;
724 else if (msgs_num == 2 &&
725 msgs[1].flags & I2C_M_RD)
726 msgs[1].len = info;
727 }
728 do_complete = true;
729 break;
730 case I2C_NACK_IND:
731 /* MASTER transmit got a NACK before tx all bytes */
732 bus->cmd_err = -ENXIO;
733 do_complete = true;
734 break;
735 case I2C_BUS_ERR_IND:
736 /* Bus error */
737 bus->cmd_err = -EAGAIN;
738 do_complete = true;
739 break;
740 case I2C_WAKE_UP_IND:
741 /* I2C wake up */
742 break;
743 default:
744 break;
745 }
746
747 bus->operation = I2C_NO_OPER;
748 #if IS_ENABLED(CONFIG_I2C_SLAVE)
749 if (bus->slave)
750 bus->master_or_slave = I2C_SLAVE;
751 #endif
752 if (do_complete)
753 complete(&bus->cmd_complete);
754 }
755
npcm_i2c_fifo_usage(struct npcm_i2c * bus)756 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
757 {
758 if (bus->operation == I2C_WRITE_OPER)
759 return (bus->data->txf_sts_tx_bytes &
760 ioread8(bus->reg + NPCM_I2CTXF_STS));
761 if (bus->operation == I2C_READ_OPER)
762 return (bus->data->rxf_sts_rx_bytes &
763 ioread8(bus->reg + NPCM_I2CRXF_STS));
764 return 0;
765 }
766
npcm_i2c_write_to_fifo_master(struct npcm_i2c * bus,u16 max_bytes)767 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
768 {
769 u8 size_free_fifo;
770
771 /*
772 * Fill the FIFO, while the FIFO is not full and there are more bytes
773 * to write
774 */
775 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
776 while (max_bytes-- && size_free_fifo) {
777 if (bus->wr_ind < bus->wr_size)
778 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
779 else
780 npcm_i2c_wr_byte(bus, 0xFF);
781 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
782 }
783 }
784
785 /*
786 * npcm_i2c_set_fifo:
787 * configure the FIFO before using it. If nread is -1 RX FIFO will not be
788 * configured. same for nwrite
789 */
npcm_i2c_set_fifo(struct npcm_i2c * bus,int nread,int nwrite)790 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
791 {
792 u8 rxf_ctl = 0;
793
794 if (!bus->fifo_use)
795 return;
796 npcm_i2c_select_bank(bus, I2C_BANK_1);
797 npcm_i2c_clear_tx_fifo(bus);
798 npcm_i2c_clear_rx_fifo(bus);
799
800 /* configure RX FIFO */
801 if (nread > 0) {
802 rxf_ctl = min_t(int, nread, bus->data->fifo_size);
803
804 /* set LAST bit. if LAST is set next FIFO packet is nacked */
805 if (nread <= bus->data->fifo_size)
806 rxf_ctl |= bus->data->rxf_ctl_last_pec;
807
808 /*
809 * if we are about to read the first byte in blk rd mode,
810 * don't NACK it. If slave returns zero size HW can't NACK
811 * it immediately, it will read extra byte and then NACK.
812 */
813 if (bus->rd_ind == 0 && bus->read_block_use) {
814 /* set fifo to read one byte, no last: */
815 rxf_ctl = 1;
816 }
817
818 /* set fifo size: */
819 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
820 }
821
822 /* configure TX FIFO */
823 if (nwrite > 0) {
824 if (nwrite > bus->data->fifo_size)
825 /* data to send is more then FIFO size. */
826 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
827 else
828 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
829
830 npcm_i2c_clear_tx_fifo(bus);
831 }
832 }
833
npcm_i2c_read_fifo(struct npcm_i2c * bus,u8 bytes_in_fifo)834 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
835 {
836 u8 data;
837
838 while (bytes_in_fifo--) {
839 data = npcm_i2c_rd_byte(bus);
840 if (bus->rd_ind < bus->rd_size)
841 bus->rd_buf[bus->rd_ind++] = data;
842 }
843 }
844
npcm_i2c_master_abort(struct npcm_i2c * bus)845 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
846 {
847 /* Only current master is allowed to issue a stop condition */
848 if (!npcm_i2c_is_master(bus))
849 return;
850
851 npcm_i2c_eob_int(bus, true);
852 npcm_i2c_master_stop(bus);
853 npcm_i2c_clear_master_status(bus);
854 }
855
856 #if IS_ENABLED(CONFIG_I2C_SLAVE)
npcm_i2c_get_slave_addr(struct npcm_i2c * bus,enum i2c_addr addr_type)857 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
858 {
859 u8 slave_add;
860
861 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
862 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
863
864 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
865
866 return slave_add;
867 }
868
npcm_i2c_remove_slave_addr(struct npcm_i2c * bus,u8 slave_add)869 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
870 {
871 int i;
872
873 /* Set the enable bit */
874 slave_add |= 0x80;
875
876 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
877 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
878 iowrite8(0, bus->reg + npcm_i2caddr[i]);
879 }
880
881 return 0;
882 }
883
npcm_i2c_write_fifo_slave(struct npcm_i2c * bus,u16 max_bytes)884 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
885 {
886 /*
887 * Fill the FIFO, while the FIFO is not full and there are more bytes
888 * to write
889 */
890 npcm_i2c_clear_fifo_int(bus);
891 npcm_i2c_clear_tx_fifo(bus);
892 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
893 while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
894 if (bus->slv_wr_size <= 0)
895 break;
896 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
897 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
898 bus->slv_wr_ind++;
899 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
900 bus->slv_wr_size--;
901 }
902 }
903
npcm_i2c_read_fifo_slave(struct npcm_i2c * bus,u8 bytes_in_fifo)904 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
905 {
906 u8 data;
907
908 if (!bus->slave)
909 return;
910
911 while (bytes_in_fifo--) {
912 data = npcm_i2c_rd_byte(bus);
913
914 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
915 bus->slv_rd_buf[bus->slv_rd_ind] = data;
916 bus->slv_rd_ind++;
917
918 /* 1st byte is length in block protocol: */
919 if (bus->slv_rd_ind == 1 && bus->read_block_use)
920 bus->slv_rd_size = data + bus->PEC_use + 1;
921 }
922 }
923
npcm_i2c_slave_get_wr_buf(struct npcm_i2c * bus)924 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
925 {
926 int i;
927 u8 value;
928 int ind;
929 int ret = bus->slv_wr_ind;
930
931 /* fill a cyclic buffer */
932 for (i = 0; i < bus->data->fifo_size; i++) {
933 if (bus->slv_wr_size >= bus->data->fifo_size)
934 break;
935 if (bus->state == I2C_SLAVE_MATCH) {
936 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
937 bus->state = I2C_OPER_STARTED;
938 } else {
939 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
940 }
941 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
942 bus->slv_wr_buf[ind] = value;
943 bus->slv_wr_size++;
944 }
945 return bus->data->fifo_size - ret;
946 }
947
npcm_i2c_slave_send_rd_buf(struct npcm_i2c * bus)948 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
949 {
950 int i;
951
952 for (i = 0; i < bus->slv_rd_ind; i++)
953 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
954 &bus->slv_rd_buf[i]);
955 /*
956 * once we send bytes up, need to reset the counter of the wr buf
957 * got data from master (new offset in device), ignore wr fifo:
958 */
959 if (bus->slv_rd_ind) {
960 bus->slv_wr_size = 0;
961 bus->slv_wr_ind = 0;
962 }
963
964 bus->slv_rd_ind = 0;
965 bus->slv_rd_size = bus->adap.quirks->max_read_len;
966
967 npcm_i2c_clear_fifo_int(bus);
968 npcm_i2c_clear_rx_fifo(bus);
969 }
970
npcm_i2c_slave_receive(struct npcm_i2c * bus,u16 nread,u8 * read_data)971 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
972 u8 *read_data)
973 {
974 bus->state = I2C_OPER_STARTED;
975 bus->operation = I2C_READ_OPER;
976 bus->slv_rd_size = nread;
977 bus->slv_rd_ind = 0;
978
979 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
980 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
981 npcm_i2c_clear_tx_fifo(bus);
982 npcm_i2c_clear_rx_fifo(bus);
983 }
984
npcm_i2c_slave_xmit(struct npcm_i2c * bus,u16 nwrite,u8 * write_data)985 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
986 u8 *write_data)
987 {
988 if (nwrite == 0)
989 return;
990
991 bus->operation = I2C_WRITE_OPER;
992
993 /* get the next buffer */
994 npcm_i2c_slave_get_wr_buf(bus);
995 npcm_i2c_write_fifo_slave(bus, nwrite);
996 }
997
998 /*
999 * npcm_i2c_slave_wr_buf_sync:
1000 * currently slave IF only supports single byte operations.
1001 * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
1002 * at a time, pack them in buffer, and then transmit them all together
1003 * to the FIFO and onward to the bus.
1004 * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1005 * sending a NACK wherever the backend requests for it is not supported.
1006 * the next two functions allow reading to local buffer before writing it all
1007 * to the HW FIFO.
1008 */
npcm_i2c_slave_wr_buf_sync(struct npcm_i2c * bus)1009 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1010 {
1011 int left_in_fifo;
1012
1013 left_in_fifo = bus->data->txf_sts_tx_bytes &
1014 ioread8(bus->reg + NPCM_I2CTXF_STS);
1015
1016 /* fifo already full: */
1017 if (left_in_fifo >= bus->data->fifo_size ||
1018 bus->slv_wr_size >= bus->data->fifo_size)
1019 return;
1020
1021 /* update the wr fifo index back to the untransmitted bytes: */
1022 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1023 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1024
1025 if (bus->slv_wr_ind < 0)
1026 bus->slv_wr_ind += bus->data->fifo_size;
1027 }
1028
npcm_i2c_slave_rd_wr(struct npcm_i2c * bus)1029 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1030 {
1031 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1032 /*
1033 * Slave got an address match with direction bit 1 so it should
1034 * transmit data. Write till the master will NACK
1035 */
1036 bus->operation = I2C_WRITE_OPER;
1037 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1038 bus->slv_wr_buf);
1039 } else {
1040 /*
1041 * Slave got an address match with direction bit 0 so it should
1042 * receive data.
1043 * this module does not support saying no to bytes.
1044 * it will always ACK.
1045 */
1046 bus->operation = I2C_READ_OPER;
1047 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1048 bus->stop_ind = I2C_SLAVE_RCV_IND;
1049 npcm_i2c_slave_send_rd_buf(bus);
1050 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1051 bus->slv_rd_buf);
1052 }
1053 }
1054
npcm_i2c_int_slave_handler(struct npcm_i2c * bus)1055 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1056 {
1057 u8 val;
1058 irqreturn_t ret = IRQ_NONE;
1059 u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1060
1061 /* Slave: A NACK has occurred */
1062 if (NPCM_I2CST_NEGACK & i2cst) {
1063 bus->stop_ind = I2C_NACK_IND;
1064 npcm_i2c_slave_wr_buf_sync(bus);
1065 if (bus->fifo_use)
1066 /* clear the FIFO */
1067 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1068 bus->reg + NPCM_I2CFIF_CTS);
1069
1070 /* In slave write, NACK is OK, otherwise it is a problem */
1071 bus->stop_ind = I2C_NO_STATUS_IND;
1072 bus->operation = I2C_NO_OPER;
1073 bus->own_slave_addr = 0xFF;
1074
1075 /*
1076 * Slave has to wait for STOP to decide this is the end
1077 * of the transaction. tx is not yet considered as done
1078 */
1079 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1080
1081 ret = IRQ_HANDLED;
1082 }
1083
1084 /* Slave mode: a Bus Error (BER) has been identified */
1085 if (NPCM_I2CST_BER & i2cst) {
1086 /*
1087 * Check whether bus arbitration or Start or Stop during data
1088 * xfer bus arbitration problem should not result in recovery
1089 */
1090 bus->stop_ind = I2C_BUS_ERR_IND;
1091
1092 /* wait for bus busy before clear fifo */
1093 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1094
1095 bus->state = I2C_IDLE;
1096
1097 /*
1098 * in BER case we might get 2 interrupts: one for slave one for
1099 * master ( for a channel which is master\slave switching)
1100 */
1101 if (completion_done(&bus->cmd_complete) == false) {
1102 bus->cmd_err = -EIO;
1103 complete(&bus->cmd_complete);
1104 }
1105 bus->own_slave_addr = 0xFF;
1106 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1107 ret = IRQ_HANDLED;
1108 }
1109
1110 /* A Slave Stop Condition has been identified */
1111 if (NPCM_I2CST_SLVSTP & i2cst) {
1112 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1113
1114 bus->stop_ind = I2C_SLAVE_DONE_IND;
1115
1116 if (bus->operation == I2C_READ_OPER)
1117 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1118
1119 /* if the buffer is empty nothing will be sent */
1120 npcm_i2c_slave_send_rd_buf(bus);
1121
1122 /* Slave done transmitting or receiving */
1123 bus->stop_ind = I2C_NO_STATUS_IND;
1124
1125 /*
1126 * Note, just because we got here, it doesn't mean we through
1127 * away the wr buffer.
1128 * we keep it until the next received offset.
1129 */
1130 bus->operation = I2C_NO_OPER;
1131 bus->own_slave_addr = 0xFF;
1132 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1133 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1134 if (bus->fifo_use) {
1135 npcm_i2c_clear_fifo_int(bus);
1136 npcm_i2c_clear_rx_fifo(bus);
1137 npcm_i2c_clear_tx_fifo(bus);
1138
1139 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1140 bus->reg + NPCM_I2CFIF_CTS);
1141 }
1142 bus->state = I2C_IDLE;
1143 ret = IRQ_HANDLED;
1144 }
1145
1146 /* restart condition occurred and Rx-FIFO was not empty */
1147 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1148 ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1149 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1150 bus->master_or_slave = I2C_SLAVE;
1151 if (bus->operation == I2C_READ_OPER)
1152 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1153 bus->operation = I2C_WRITE_OPER;
1154 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1155 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1156 NPCM_I2CFIF_CTS_RXF_TXE;
1157 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1158 npcm_i2c_slave_rd_wr(bus);
1159 ret = IRQ_HANDLED;
1160 }
1161
1162 /* A Slave Address Match has been identified */
1163 if (NPCM_I2CST_NMATCH & i2cst) {
1164 u8 info = 0;
1165
1166 /* Address match automatically implies slave mode */
1167 bus->master_or_slave = I2C_SLAVE;
1168 npcm_i2c_clear_fifo_int(bus);
1169 npcm_i2c_clear_rx_fifo(bus);
1170 npcm_i2c_clear_tx_fifo(bus);
1171 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1172 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1173 if (NPCM_I2CST_XMIT & i2cst) {
1174 bus->operation = I2C_WRITE_OPER;
1175 } else {
1176 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1177 &info);
1178 bus->operation = I2C_READ_OPER;
1179 }
1180 if (bus->own_slave_addr == 0xFF) {
1181 /* Check which type of address match */
1182 val = ioread8(bus->reg + NPCM_I2CCST);
1183 if (NPCM_I2CCST_MATCH & val) {
1184 u16 addr;
1185 enum i2c_addr eaddr;
1186 u8 i2ccst2;
1187 u8 i2ccst3;
1188
1189 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1190 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1191
1192 /*
1193 * the i2c module can response to 10 own SA.
1194 * check which one was addressed by the master.
1195 * respond to the first one.
1196 */
1197 addr = ((i2ccst3 & 0x07) << 7) |
1198 (i2ccst2 & 0x7F);
1199 info = ffs(addr);
1200 eaddr = (enum i2c_addr)info;
1201 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1202 addr &= 0x7F;
1203 bus->own_slave_addr = addr;
1204 if (bus->PEC_mask & BIT(info))
1205 bus->PEC_use = true;
1206 else
1207 bus->PEC_use = false;
1208 } else {
1209 if (NPCM_I2CCST_GCMATCH & val)
1210 bus->own_slave_addr = 0;
1211 if (NPCM_I2CCST_ARPMATCH & val)
1212 bus->own_slave_addr = 0x61;
1213 }
1214 } else {
1215 /*
1216 * Slave match can happen in two options:
1217 * 1. Start, SA, read (slave read without further ado)
1218 * 2. Start, SA, read, data, restart, SA, read, ...
1219 * (slave read in fragmented mode)
1220 * 3. Start, SA, write, data, restart, SA, read, ..
1221 * (regular write-read mode)
1222 */
1223 if ((bus->state == I2C_OPER_STARTED &&
1224 bus->operation == I2C_READ_OPER &&
1225 bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1226 bus->stop_ind == I2C_SLAVE_RCV_IND) {
1227 /* slave tx after slave rx w/o STOP */
1228 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1229 }
1230 }
1231
1232 if (NPCM_I2CST_XMIT & i2cst)
1233 bus->stop_ind = I2C_SLAVE_XMIT_IND;
1234 else
1235 bus->stop_ind = I2C_SLAVE_RCV_IND;
1236 bus->state = I2C_SLAVE_MATCH;
1237 npcm_i2c_slave_rd_wr(bus);
1238 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1239 ret = IRQ_HANDLED;
1240 }
1241
1242 /* Slave SDA status is set - tx or rx */
1243 if ((NPCM_I2CST_SDAST & i2cst) ||
1244 (bus->fifo_use &&
1245 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1246 npcm_i2c_slave_rd_wr(bus);
1247 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1248 ret = IRQ_HANDLED;
1249 } /* SDAST */
1250
1251 /*
1252 * If irq is not one of the above, make sure EOB is disabled and all
1253 * status bits are cleared.
1254 */
1255 if (ret == IRQ_NONE) {
1256 npcm_i2c_eob_int(bus, false);
1257 npcm_i2c_clear_master_status(bus);
1258 }
1259
1260 return IRQ_HANDLED;
1261 }
1262
npcm_i2c_reg_slave(struct i2c_client * client)1263 static int npcm_i2c_reg_slave(struct i2c_client *client)
1264 {
1265 unsigned long lock_flags;
1266 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1267
1268 bus->slave = client;
1269
1270 if (client->flags & I2C_CLIENT_TEN)
1271 return -EAFNOSUPPORT;
1272
1273 spin_lock_irqsave(&bus->lock, lock_flags);
1274
1275 npcm_i2c_init_params(bus);
1276 bus->slv_rd_size = 0;
1277 bus->slv_wr_size = 0;
1278 bus->slv_rd_ind = 0;
1279 bus->slv_wr_ind = 0;
1280 if (client->flags & I2C_CLIENT_PEC)
1281 bus->PEC_use = true;
1282
1283 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1284 client->addr, bus->PEC_use);
1285
1286 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1287 npcm_i2c_clear_fifo_int(bus);
1288 npcm_i2c_clear_rx_fifo(bus);
1289 npcm_i2c_clear_tx_fifo(bus);
1290 npcm_i2c_slave_int_enable(bus, true);
1291
1292 spin_unlock_irqrestore(&bus->lock, lock_flags);
1293 return 0;
1294 }
1295
npcm_i2c_unreg_slave(struct i2c_client * client)1296 static int npcm_i2c_unreg_slave(struct i2c_client *client)
1297 {
1298 struct npcm_i2c *bus = client->adapter->algo_data;
1299 unsigned long lock_flags;
1300
1301 spin_lock_irqsave(&bus->lock, lock_flags);
1302 if (!bus->slave) {
1303 spin_unlock_irqrestore(&bus->lock, lock_flags);
1304 return -EINVAL;
1305 }
1306 npcm_i2c_slave_int_enable(bus, false);
1307 npcm_i2c_remove_slave_addr(bus, client->addr);
1308 bus->slave = NULL;
1309 spin_unlock_irqrestore(&bus->lock, lock_flags);
1310 return 0;
1311 }
1312 #endif /* CONFIG_I2C_SLAVE */
1313
npcm_i2c_master_fifo_read(struct npcm_i2c * bus)1314 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1315 {
1316 int rcount;
1317 int fifo_bytes;
1318 enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1319
1320 fifo_bytes = npcm_i2c_fifo_usage(bus);
1321 rcount = bus->rd_size - bus->rd_ind;
1322
1323 /*
1324 * In order not to change the RX_TRH during transaction (we found that
1325 * this might be problematic if it takes too much time to read the FIFO)
1326 * we read the data in the following way. If the number of bytes to
1327 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1328 * and in the next int we read rest of the data.
1329 */
1330 if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1331 fifo_bytes = rcount - bus->data->fifo_size;
1332
1333 if (rcount <= fifo_bytes) {
1334 /* last bytes are about to be read - end of tx */
1335 bus->state = I2C_STOP_PENDING;
1336 bus->stop_ind = ind;
1337 npcm_i2c_eob_int(bus, true);
1338 /* Stop should be set before reading last byte. */
1339 npcm_i2c_master_stop(bus);
1340 npcm_i2c_read_fifo(bus, fifo_bytes);
1341 } else {
1342 npcm_i2c_read_fifo(bus, fifo_bytes);
1343 rcount = bus->rd_size - bus->rd_ind;
1344 npcm_i2c_set_fifo(bus, rcount, -1);
1345 }
1346 }
1347
npcm_i2c_irq_master_handler_write(struct npcm_i2c * bus)1348 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1349 {
1350 u16 wcount;
1351
1352 if (bus->fifo_use)
1353 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1354
1355 /* Master write operation - last byte handling */
1356 if (bus->wr_ind == bus->wr_size) {
1357 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1358 /*
1359 * No more bytes to send (to add to the FIFO),
1360 * however the FIFO is not empty yet. It is
1361 * still in the middle of tx. Currently there's nothing
1362 * to do except for waiting to the end of the tx
1363 * We will get an int when the FIFO will get empty.
1364 */
1365 return;
1366
1367 if (bus->rd_size == 0) {
1368 /* all bytes have been written, in wr only operation */
1369 npcm_i2c_eob_int(bus, true);
1370 bus->state = I2C_STOP_PENDING;
1371 bus->stop_ind = I2C_MASTER_DONE_IND;
1372 npcm_i2c_master_stop(bus);
1373 /* Clear SDA Status bit (by writing dummy byte) */
1374 npcm_i2c_wr_byte(bus, 0xFF);
1375
1376 } else {
1377 /* last write-byte written on previous int - restart */
1378 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1379 /* Generate repeated start upon next write to SDA */
1380 npcm_i2c_master_start(bus);
1381
1382 /*
1383 * Receiving one byte only - stall after successful
1384 * completion of send address byte. If we NACK here, and
1385 * slave doesn't ACK the address, we might
1386 * unintentionally NACK the next multi-byte read.
1387 */
1388 if (bus->rd_size == 1)
1389 npcm_i2c_stall_after_start(bus, true);
1390
1391 /* Next int will occur on read */
1392 bus->operation = I2C_READ_OPER;
1393 /* send the slave address in read direction */
1394 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1395 }
1396 } else {
1397 /* write next byte not last byte and not slave address */
1398 if (!bus->fifo_use || bus->wr_size == 1) {
1399 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1400 } else {
1401 wcount = bus->wr_size - bus->wr_ind;
1402 npcm_i2c_set_fifo(bus, -1, wcount);
1403 if (wcount)
1404 npcm_i2c_write_to_fifo_master(bus, wcount);
1405 }
1406 }
1407 }
1408
npcm_i2c_irq_master_handler_read(struct npcm_i2c * bus)1409 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1410 {
1411 u16 block_extra_bytes_size;
1412 u8 data;
1413
1414 /* added bytes to the packet: */
1415 block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1416
1417 /*
1418 * Perform master read, distinguishing between last byte and the rest of
1419 * the bytes. The last byte should be read when the clock is stopped
1420 */
1421 if (bus->rd_ind == 0) { /* first byte handling: */
1422 if (bus->read_block_use) {
1423 /* first byte in block protocol is the size: */
1424 data = npcm_i2c_rd_byte(bus);
1425 data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1426 bus->rd_size = data + block_extra_bytes_size;
1427 bus->rd_buf[bus->rd_ind++] = data;
1428
1429 /* clear RX FIFO interrupt status: */
1430 if (bus->fifo_use) {
1431 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1432 data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1433 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1434 }
1435
1436 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1437 npcm_i2c_stall_after_start(bus, false);
1438 } else {
1439 npcm_i2c_clear_tx_fifo(bus);
1440 npcm_i2c_master_fifo_read(bus);
1441 }
1442 } else {
1443 if (bus->rd_size == block_extra_bytes_size &&
1444 bus->read_block_use) {
1445 bus->state = I2C_STOP_PENDING;
1446 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1447 bus->cmd_err = -EIO;
1448 npcm_i2c_eob_int(bus, true);
1449 npcm_i2c_master_stop(bus);
1450 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1451 } else {
1452 npcm_i2c_master_fifo_read(bus);
1453 }
1454 }
1455 }
1456
npcm_i2c_irq_handle_nmatch(struct npcm_i2c * bus)1457 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1458 {
1459 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1460 npcm_i2c_nack(bus);
1461 bus->stop_ind = I2C_BUS_ERR_IND;
1462 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1463 }
1464
1465 /* A NACK has occurred */
npcm_i2c_irq_handle_nack(struct npcm_i2c * bus)1466 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1467 {
1468 u8 val;
1469
1470 if (bus->nack_cnt < ULLONG_MAX)
1471 bus->nack_cnt++;
1472
1473 if (bus->fifo_use) {
1474 /*
1475 * if there are still untransmitted bytes in TX FIFO
1476 * reduce them from wr_ind
1477 */
1478 if (bus->operation == I2C_WRITE_OPER)
1479 bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1480
1481 /* clear the FIFO */
1482 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1483 }
1484
1485 /* In master write operation, got unexpected NACK */
1486 bus->stop_ind = I2C_NACK_IND;
1487 /* Only current master is allowed to issue Stop Condition */
1488 if (npcm_i2c_is_master(bus)) {
1489 /* stopping in the middle */
1490 npcm_i2c_eob_int(bus, false);
1491 npcm_i2c_master_stop(bus);
1492
1493 /* Clear SDA Status bit (by reading dummy byte) */
1494 npcm_i2c_rd_byte(bus);
1495
1496 /*
1497 * The bus is released from stall only after the SW clears
1498 * NEGACK bit. Then a Stop condition is sent.
1499 */
1500 npcm_i2c_clear_master_status(bus);
1501 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1502 !(val & NPCM_I2CCST_BUSY), 10, 200);
1503 /* Verify no status bits are still set after bus is released */
1504 npcm_i2c_clear_master_status(bus);
1505 }
1506 bus->state = I2C_IDLE;
1507
1508 /*
1509 * In Master mode, NACK should be cleared only after STOP.
1510 * In such case, the bus is released from stall only after the
1511 * software clears NACK bit. Then a Stop condition is sent.
1512 */
1513 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1514 }
1515
1516 /* Master mode: a Bus Error has been identified */
npcm_i2c_irq_handle_ber(struct npcm_i2c * bus)1517 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1518 {
1519 if (bus->ber_cnt < ULLONG_MAX)
1520 bus->ber_cnt++;
1521 bus->stop_ind = I2C_BUS_ERR_IND;
1522 if (npcm_i2c_is_master(bus)) {
1523 npcm_i2c_master_abort(bus);
1524 } else {
1525 bus->ber_state = true;
1526 npcm_i2c_clear_master_status(bus);
1527
1528 /* Clear BB (BUS BUSY) bit */
1529 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1530
1531 bus->cmd_err = -EAGAIN;
1532 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1533 }
1534 bus->state = I2C_IDLE;
1535 }
1536
1537 /* EOB: a master End Of Busy (meaning STOP completed) */
npcm_i2c_irq_handle_eob(struct npcm_i2c * bus)1538 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1539 {
1540 npcm_i2c_eob_int(bus, false);
1541 bus->state = I2C_IDLE;
1542 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1543 }
1544
1545 /* Address sent and requested stall occurred (Master mode) */
npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c * bus)1546 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1547 {
1548 if (npcm_i2c_is_quick(bus)) {
1549 bus->state = I2C_STOP_PENDING;
1550 bus->stop_ind = I2C_MASTER_DONE_IND;
1551 npcm_i2c_eob_int(bus, true);
1552 npcm_i2c_master_stop(bus);
1553 } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1554 /*
1555 * Receiving one byte only - set NACK after ensuring
1556 * slave ACKed the address byte.
1557 */
1558 npcm_i2c_nack(bus);
1559 }
1560
1561 /* Reset stall-after-address-byte */
1562 npcm_i2c_stall_after_start(bus, false);
1563
1564 /* Clear stall only after setting STOP */
1565 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1566 }
1567
1568 /* SDA status is set - TX or RX, master */
npcm_i2c_irq_handle_sda(struct npcm_i2c * bus,u8 i2cst)1569 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1570 {
1571 u8 fif_cts;
1572
1573 if (!npcm_i2c_is_master(bus))
1574 return;
1575
1576 if (bus->state == I2C_IDLE) {
1577 bus->stop_ind = I2C_WAKE_UP_IND;
1578
1579 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1580 /*
1581 * Need to stall after successful
1582 * completion of sending address byte
1583 */
1584 npcm_i2c_stall_after_start(bus, true);
1585 else
1586 npcm_i2c_stall_after_start(bus, false);
1587
1588 /*
1589 * Receiving one byte only - stall after successful completion
1590 * of sending address byte If we NACK here, and slave doesn't
1591 * ACK the address, we might unintentionally NACK the next
1592 * multi-byte read
1593 */
1594 if (bus->wr_size == 0 && bus->rd_size == 1)
1595 npcm_i2c_stall_after_start(bus, true);
1596
1597 /* Initiate I2C master tx */
1598
1599 /* select bank 1 for FIFO regs */
1600 npcm_i2c_select_bank(bus, I2C_BANK_1);
1601
1602 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1603 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1604
1605 /* clear FIFO and relevant status bits. */
1606 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1607 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1608
1609 /* re-enable */
1610 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1611 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1612
1613 /*
1614 * Configure the FIFO threshold:
1615 * according to the needed # of bytes to read.
1616 * Note: due to HW limitation can't config the rx fifo before it
1617 * got and ACK on the restart. LAST bit will not be reset unless
1618 * RX completed. It will stay set on the next tx.
1619 */
1620 if (bus->wr_size)
1621 npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1622 else
1623 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1624
1625 bus->state = I2C_OPER_STARTED;
1626
1627 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1628 npcm_i2c_wr_byte(bus, bus->dest_addr);
1629 else
1630 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1631 /* SDA interrupt, after start\restart */
1632 } else {
1633 if (bus->operation == I2C_WRITE_OPER)
1634 npcm_i2c_irq_master_handler_write(bus);
1635 else if (bus->operation == I2C_READ_OPER)
1636 npcm_i2c_irq_master_handler_read(bus);
1637 }
1638 }
1639
npcm_i2c_int_master_handler(struct npcm_i2c * bus)1640 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1641 {
1642 u8 i2cst;
1643 int ret = -EIO;
1644
1645 i2cst = ioread8(bus->reg + NPCM_I2CST);
1646
1647 if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1648 npcm_i2c_irq_handle_nmatch(bus);
1649 return 0;
1650 }
1651 /* A NACK has occurred */
1652 if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1653 npcm_i2c_irq_handle_nack(bus);
1654 return 0;
1655 }
1656
1657 /* Master mode: a Bus Error has been identified */
1658 if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1659 npcm_i2c_irq_handle_ber(bus);
1660 return 0;
1661 }
1662
1663 /* EOB: a master End Of Busy (meaning STOP completed) */
1664 if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1665 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1666 (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1667 ioread8(bus->reg + NPCM_I2CCST3)))) {
1668 npcm_i2c_irq_handle_eob(bus);
1669 return 0;
1670 }
1671
1672 /* Address sent and requested stall occurred (Master mode) */
1673 if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1674 npcm_i2c_irq_handle_stall_after_start(bus);
1675 ret = 0;
1676 }
1677
1678 /* SDA status is set - TX or RX, master */
1679 if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1680 (bus->fifo_use &&
1681 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1682 npcm_i2c_irq_handle_sda(bus, i2cst);
1683 ret = 0;
1684 }
1685
1686 return ret;
1687 }
1688
1689 /* recovery using TGCLK functionality of the module */
npcm_i2c_recovery_tgclk(struct i2c_adapter * _adap)1690 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1691 {
1692 u8 val;
1693 u8 fif_cts;
1694 bool done = false;
1695 int status = -ENOTRECOVERABLE;
1696 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1697 /* Allow 3 bytes (27 toggles) to be read from the slave: */
1698 int iter = 27;
1699
1700 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1701 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1702 bus->num, bus->dest_addr);
1703 npcm_i2c_reset(bus);
1704 bus->ber_state = false;
1705 return 0;
1706 }
1707
1708 npcm_i2c_int_enable(bus, false);
1709 npcm_i2c_disable(bus);
1710 npcm_i2c_enable(bus);
1711 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1712 npcm_i2c_clear_tx_fifo(bus);
1713 npcm_i2c_clear_rx_fifo(bus);
1714 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1715 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1716 npcm_i2c_stall_after_start(bus, false);
1717
1718 /* select bank 1 for FIFO regs */
1719 npcm_i2c_select_bank(bus, I2C_BANK_1);
1720
1721 /* clear FIFO and relevant status bits. */
1722 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1723 fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1724 fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1725 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1726 npcm_i2c_set_fifo(bus, -1, 0);
1727
1728 /* Repeat the following sequence until SDA is released */
1729 do {
1730 /* Issue a single SCL toggle */
1731 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1732 usleep_range(20, 30);
1733 /* If SDA line is inactive (high), stop */
1734 if (npcm_i2c_get_SDA(_adap)) {
1735 done = true;
1736 status = 0;
1737 }
1738 } while (!done && iter--);
1739
1740 /* If SDA line is released: send start-addr-stop, to re-sync. */
1741 if (npcm_i2c_get_SDA(_adap)) {
1742 /* Send an address byte in write direction: */
1743 npcm_i2c_wr_byte(bus, bus->dest_addr);
1744 npcm_i2c_master_start(bus);
1745 /* Wait until START condition is sent */
1746 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1747 20, 200);
1748 /* If START condition was sent */
1749 if (npcm_i2c_is_master(bus) > 0) {
1750 usleep_range(20, 30);
1751 npcm_i2c_master_stop(bus);
1752 usleep_range(200, 500);
1753 }
1754 }
1755 npcm_i2c_reset(bus);
1756 npcm_i2c_int_enable(bus, true);
1757
1758 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1759 status = 0;
1760 else
1761 status = -ENOTRECOVERABLE;
1762 if (status) {
1763 if (bus->rec_fail_cnt < ULLONG_MAX)
1764 bus->rec_fail_cnt++;
1765 } else {
1766 if (bus->rec_succ_cnt < ULLONG_MAX)
1767 bus->rec_succ_cnt++;
1768 }
1769 bus->ber_state = false;
1770 return status;
1771 }
1772
1773 /* recovery using bit banging functionality of the module */
npcm_i2c_recovery_init(struct i2c_adapter * _adap)1774 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1775 {
1776 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1777 struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1778
1779 rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1780
1781 /*
1782 * npcm i2c HW allows direct reading of SCL and SDA.
1783 * However, it does not support setting SCL and SDA directly.
1784 * The recovery function can toggle SCL when SDA is low (but not set)
1785 * Getter functions used internally, and can be used externally.
1786 */
1787 rinfo->get_scl = npcm_i2c_get_SCL;
1788 rinfo->get_sda = npcm_i2c_get_SDA;
1789 _adap->bus_recovery_info = rinfo;
1790 }
1791
1792 /* SCLFRQ min/max field values */
1793 #define SCLFRQ_MIN 10
1794 #define SCLFRQ_MAX 511
1795 #define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000)
1796
1797 /*
1798 * npcm_i2c_init_clk: init HW timing parameters.
1799 * NPCM7XX i2c module timing parameters are dependent on module core clk (APB)
1800 * and bus frequency.
1801 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
1802 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
1803 * by the HW designer, given core clock range (equations in comments below).
1804 *
1805 */
npcm_i2c_init_clk(struct npcm_i2c * bus,u32 bus_freq_hz)1806 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1807 {
1808 u32 k1 = 0;
1809 u32 k2 = 0;
1810 u8 dbnct = 0;
1811 u32 sclfrq = 0;
1812 u8 hldt = 7;
1813 u8 fast_mode = 0;
1814 u32 src_clk_khz;
1815 u32 bus_freq_khz;
1816
1817 src_clk_khz = bus->apb_clk / 1000;
1818 bus_freq_khz = bus_freq_hz / 1000;
1819 bus->bus_freq = bus_freq_hz;
1820
1821 /* 100KHz and below: */
1822 if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1823 sclfrq = src_clk_khz / (bus_freq_khz * 4);
1824
1825 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1826 return -EDOM;
1827
1828 if (src_clk_khz >= 40000)
1829 hldt = 17;
1830 else if (src_clk_khz >= 12500)
1831 hldt = 15;
1832 else
1833 hldt = 7;
1834 }
1835
1836 /* 400KHz: */
1837 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1838 sclfrq = 0;
1839 fast_mode = I2CCTL3_400K_MODE;
1840
1841 if (src_clk_khz < 7500)
1842 /* 400KHZ cannot be supported for core clock < 7.5MHz */
1843 return -EDOM;
1844
1845 else if (src_clk_khz >= 50000) {
1846 k1 = 80;
1847 k2 = 48;
1848 hldt = 12;
1849 dbnct = 7;
1850 }
1851
1852 /* Master or Slave with frequency > 25MHz */
1853 else if (src_clk_khz > 25000) {
1854 hldt = clk_coef(src_clk_khz, 300) + 7;
1855 k1 = clk_coef(src_clk_khz, 1600);
1856 k2 = clk_coef(src_clk_khz, 900);
1857 }
1858 }
1859
1860 /* 1MHz: */
1861 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1862 sclfrq = 0;
1863 fast_mode = I2CCTL3_400K_MODE;
1864
1865 /* 1MHZ cannot be supported for core clock < 24 MHz */
1866 if (src_clk_khz < 24000)
1867 return -EDOM;
1868
1869 k1 = clk_coef(src_clk_khz, 620);
1870 k2 = clk_coef(src_clk_khz, 380);
1871
1872 /* Core clk > 40 MHz */
1873 if (src_clk_khz > 40000) {
1874 /*
1875 * Set HLDT:
1876 * SDA hold time: (HLDT-7) * T(CLK) >= 120
1877 * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1878 */
1879 hldt = clk_coef(src_clk_khz, 120) + 7;
1880 } else {
1881 hldt = 7;
1882 dbnct = 2;
1883 }
1884 }
1885
1886 /* Frequency larger than 1 MHz is not supported */
1887 else
1888 return -EINVAL;
1889
1890 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1891 k1 = round_up(k1, 2);
1892 k2 = round_up(k2 + 1, 2);
1893 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1894 k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1895 return -EDOM;
1896 }
1897
1898 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1899 iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1900 bus->reg + NPCM_I2CCTL2);
1901
1902 /* bits [8:7] are in I2CCTL3 reg */
1903 iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1904 bus->reg + NPCM_I2CCTL3);
1905
1906 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1907 npcm_i2c_select_bank(bus, I2C_BANK_0);
1908
1909 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1910 /*
1911 * Set SCL Low/High Time:
1912 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2
1913 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1914 */
1915 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1916 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1917
1918 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1919 }
1920
1921 iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1922
1923 /* Return to Bank 1, and stay there by default: */
1924 npcm_i2c_select_bank(bus, I2C_BANK_1);
1925
1926 return 0;
1927 }
1928
npcm_i2c_init_module(struct npcm_i2c * bus,enum i2c_mode mode,u32 bus_freq_hz)1929 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1930 u32 bus_freq_hz)
1931 {
1932 u8 val;
1933 int ret;
1934
1935 /* Check whether module already enabled or frequency is out of bounds */
1936 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1937 bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1938 return -EINVAL;
1939
1940 npcm_i2c_int_enable(bus, false);
1941 npcm_i2c_disable(bus);
1942
1943 /* Configure FIFO mode : */
1944 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1945 bus->fifo_use = true;
1946 npcm_i2c_select_bank(bus, I2C_BANK_0);
1947 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1948 val |= NPCM_I2CFIF_CTL_FIFO_EN;
1949 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1950 npcm_i2c_select_bank(bus, I2C_BANK_1);
1951 } else {
1952 bus->fifo_use = false;
1953 }
1954
1955 /* Configure I2C module clock frequency */
1956 ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1957 if (ret) {
1958 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1959 return ret;
1960 }
1961
1962 /* Enable module (before configuring CTL1) */
1963 npcm_i2c_enable(bus);
1964 bus->state = I2C_IDLE;
1965 val = ioread8(bus->reg + NPCM_I2CCTL1);
1966 val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1967 iowrite8(val, bus->reg + NPCM_I2CCTL1);
1968
1969 npcm_i2c_reset(bus);
1970
1971 /* Check HW is OK: SDA and SCL should be high at this point. */
1972 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1973 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1974 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1975 npcm_i2c_get_SCL(&bus->adap));
1976 return -ENXIO;
1977 }
1978
1979 npcm_i2c_int_enable(bus, true);
1980 return 0;
1981 }
1982
__npcm_i2c_init(struct npcm_i2c * bus,struct platform_device * pdev)1983 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1984 {
1985 u32 clk_freq_hz;
1986 int ret;
1987
1988 /* Initialize the internal data structures */
1989 bus->state = I2C_DISABLE;
1990 bus->master_or_slave = I2C_SLAVE;
1991 bus->int_time_stamp = 0;
1992 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1993 bus->slave = NULL;
1994 #endif
1995
1996 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1997 &clk_freq_hz);
1998 if (ret) {
1999 dev_info(&pdev->dev, "Could not read clock-frequency property");
2000 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
2001 }
2002
2003 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2004 if (ret) {
2005 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
2006 return ret;
2007 }
2008
2009 return 0;
2010 }
2011
npcm_i2c_bus_irq(int irq,void * dev_id)2012 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
2013 {
2014 struct npcm_i2c *bus = dev_id;
2015
2016 if (npcm_i2c_is_master(bus))
2017 bus->master_or_slave = I2C_MASTER;
2018
2019 if (bus->master_or_slave == I2C_MASTER) {
2020 bus->int_time_stamp = jiffies;
2021 if (!npcm_i2c_int_master_handler(bus))
2022 return IRQ_HANDLED;
2023 }
2024 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2025 if (bus->slave) {
2026 bus->master_or_slave = I2C_SLAVE;
2027 if (npcm_i2c_int_slave_handler(bus))
2028 return IRQ_HANDLED;
2029 }
2030 #endif
2031 /* Clear status bits for spurious interrupts */
2032 npcm_i2c_clear_master_status(bus);
2033
2034 return IRQ_HANDLED;
2035 }
2036
npcm_i2c_master_start_xmit(struct npcm_i2c * bus,u8 slave_addr,u16 nwrite,u16 nread,u8 * write_data,u8 * read_data,bool use_PEC,bool use_read_block)2037 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2038 u8 slave_addr, u16 nwrite, u16 nread,
2039 u8 *write_data, u8 *read_data,
2040 bool use_PEC, bool use_read_block)
2041 {
2042 if (bus->state != I2C_IDLE) {
2043 bus->cmd_err = -EBUSY;
2044 return false;
2045 }
2046 bus->dest_addr = slave_addr << 1;
2047 bus->wr_buf = write_data;
2048 bus->wr_size = nwrite;
2049 bus->wr_ind = 0;
2050 bus->rd_buf = read_data;
2051 bus->rd_size = nread;
2052 bus->rd_ind = 0;
2053 bus->PEC_use = 0;
2054
2055 /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2056 if (nread)
2057 bus->PEC_use = use_PEC;
2058
2059 bus->read_block_use = use_read_block;
2060 if (nread && !nwrite)
2061 bus->operation = I2C_READ_OPER;
2062 else
2063 bus->operation = I2C_WRITE_OPER;
2064 if (bus->fifo_use) {
2065 u8 i2cfif_cts;
2066
2067 npcm_i2c_select_bank(bus, I2C_BANK_1);
2068 /* clear FIFO and relevant status bits. */
2069 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2070 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2071 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2072 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2073 }
2074
2075 bus->state = I2C_IDLE;
2076 npcm_i2c_stall_after_start(bus, true);
2077 npcm_i2c_master_start(bus);
2078 return true;
2079 }
2080
npcm_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)2081 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2082 int num)
2083 {
2084 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2085 struct i2c_msg *msg0, *msg1;
2086 unsigned long time_left, flags;
2087 u16 nwrite, nread;
2088 u8 *write_data, *read_data;
2089 u8 slave_addr;
2090 unsigned long timeout;
2091 bool read_block = false;
2092 bool read_PEC = false;
2093 u8 bus_busy;
2094 unsigned long timeout_usec;
2095
2096 if (bus->state == I2C_DISABLE) {
2097 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2098 return -EINVAL;
2099 }
2100
2101 msg0 = &msgs[0];
2102 slave_addr = msg0->addr;
2103 if (msg0->flags & I2C_M_RD) { /* read */
2104 nwrite = 0;
2105 write_data = NULL;
2106 read_data = msg0->buf;
2107 if (msg0->flags & I2C_M_RECV_LEN) {
2108 nread = 1;
2109 read_block = true;
2110 if (msg0->flags & I2C_CLIENT_PEC)
2111 read_PEC = true;
2112 } else {
2113 nread = msg0->len;
2114 }
2115 } else { /* write */
2116 nwrite = msg0->len;
2117 write_data = msg0->buf;
2118 nread = 0;
2119 read_data = NULL;
2120 if (num == 2) {
2121 msg1 = &msgs[1];
2122 read_data = msg1->buf;
2123 if (msg1->flags & I2C_M_RECV_LEN) {
2124 nread = 1;
2125 read_block = true;
2126 if (msg1->flags & I2C_CLIENT_PEC)
2127 read_PEC = true;
2128 } else {
2129 nread = msg1->len;
2130 read_block = false;
2131 }
2132 }
2133 }
2134
2135 /*
2136 * Adaptive TimeOut: estimated time in usec + 100% margin:
2137 * 2: double the timeout for clock stretching case
2138 * 9: bits per transaction (including the ack/nack)
2139 */
2140 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2141 timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2142 if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2143 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2144 return -EINVAL;
2145 }
2146
2147 time_left = jiffies + timeout + 1;
2148 do {
2149 /*
2150 * we must clear slave address immediately when the bus is not
2151 * busy, so we spinlock it, but we don't keep the lock for the
2152 * entire while since it is too long.
2153 */
2154 spin_lock_irqsave(&bus->lock, flags);
2155 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2156 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2157 if (!bus_busy && bus->slave)
2158 iowrite8((bus->slave->addr & 0x7F),
2159 bus->reg + NPCM_I2CADDR1);
2160 #endif
2161 spin_unlock_irqrestore(&bus->lock, flags);
2162
2163 } while (time_is_after_jiffies(time_left) && bus_busy);
2164
2165 /*
2166 * Check the BER (bus error) state, when ber_state is true, it means that the module
2167 * detects the bus error which is caused by some factor like that the electricity
2168 * noise occurs on the bus. Under this condition, the module is reset and the bus
2169 * gets recovered.
2170 *
2171 * While ber_state is false, the module reset and bus recovery also get done as the
2172 * bus is busy.
2173 */
2174 if (bus_busy || bus->ber_state) {
2175 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2176 npcm_i2c_reset(bus);
2177 i2c_recover_bus(adap);
2178 return -EAGAIN;
2179 }
2180
2181 npcm_i2c_init_params(bus);
2182 bus->dest_addr = slave_addr;
2183 bus->msgs = msgs;
2184 bus->msgs_num = num;
2185 bus->cmd_err = 0;
2186 bus->read_block_use = read_block;
2187
2188 reinit_completion(&bus->cmd_complete);
2189
2190 npcm_i2c_int_enable(bus, true);
2191
2192 if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2193 write_data, read_data, read_PEC,
2194 read_block)) {
2195 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2196 timeout);
2197
2198 if (time_left == 0) {
2199 if (bus->timeout_cnt < ULLONG_MAX)
2200 bus->timeout_cnt++;
2201 if (bus->master_or_slave == I2C_MASTER) {
2202 i2c_recover_bus(adap);
2203 bus->cmd_err = -EIO;
2204 bus->state = I2C_IDLE;
2205 }
2206 }
2207 }
2208
2209 /* if there was BER, check if need to recover the bus: */
2210 if (bus->cmd_err == -EAGAIN)
2211 bus->cmd_err = i2c_recover_bus(adap);
2212
2213 /*
2214 * After any type of error, check if LAST bit is still set,
2215 * due to a HW issue.
2216 * It cannot be cleared without resetting the module.
2217 */
2218 else if (bus->cmd_err &&
2219 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2220 npcm_i2c_reset(bus);
2221
2222 /* After any xfer, successful or not, stall and EOB must be disabled */
2223 npcm_i2c_stall_after_start(bus, false);
2224 npcm_i2c_eob_int(bus, false);
2225
2226 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2227 /* reenable slave if it was enabled */
2228 if (bus->slave)
2229 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2230 bus->reg + NPCM_I2CADDR1);
2231 #else
2232 npcm_i2c_int_enable(bus, false);
2233 #endif
2234 return bus->cmd_err;
2235 }
2236
npcm_i2c_functionality(struct i2c_adapter * adap)2237 static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2238 {
2239 return I2C_FUNC_I2C |
2240 I2C_FUNC_SMBUS_EMUL |
2241 I2C_FUNC_SMBUS_BLOCK_DATA |
2242 I2C_FUNC_SMBUS_PEC |
2243 I2C_FUNC_SLAVE;
2244 }
2245
2246 static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2247 .max_read_len = 32768,
2248 .max_write_len = 32768,
2249 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
2250 };
2251
2252 static const struct i2c_algorithm npcm_i2c_algo = {
2253 .master_xfer = npcm_i2c_master_xfer,
2254 .functionality = npcm_i2c_functionality,
2255 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2256 .reg_slave = npcm_i2c_reg_slave,
2257 .unreg_slave = npcm_i2c_unreg_slave,
2258 #endif
2259 };
2260
npcm_i2c_init_debugfs(struct platform_device * pdev,struct npcm_i2c * bus)2261 static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2262 struct npcm_i2c *bus)
2263 {
2264 debugfs_create_u64("ber_cnt", 0444, bus->adap.debugfs, &bus->ber_cnt);
2265 debugfs_create_u64("nack_cnt", 0444, bus->adap.debugfs, &bus->nack_cnt);
2266 debugfs_create_u64("rec_succ_cnt", 0444, bus->adap.debugfs, &bus->rec_succ_cnt);
2267 debugfs_create_u64("rec_fail_cnt", 0444, bus->adap.debugfs, &bus->rec_fail_cnt);
2268 debugfs_create_u64("timeout_cnt", 0444, bus->adap.debugfs, &bus->timeout_cnt);
2269 debugfs_create_u64("tx_complete_cnt", 0444, bus->adap.debugfs, &bus->tx_complete_cnt);
2270 }
2271
npcm_i2c_probe_bus(struct platform_device * pdev)2272 static int npcm_i2c_probe_bus(struct platform_device *pdev)
2273 {
2274 struct device_node *np = pdev->dev.of_node;
2275 static struct regmap *gcr_regmap;
2276 struct device *dev = &pdev->dev;
2277 struct i2c_adapter *adap;
2278 struct npcm_i2c *bus;
2279 struct clk *i2c_clk;
2280 int irq;
2281 int ret;
2282
2283 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2284 if (!bus)
2285 return -ENOMEM;
2286
2287 bus->dev = &pdev->dev;
2288
2289 bus->data = of_device_get_match_data(dev);
2290 if (!bus->data) {
2291 dev_err(dev, "OF data missing\n");
2292 return -EINVAL;
2293 }
2294
2295 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2296 /* core clk must be acquired to calculate module timing settings */
2297 i2c_clk = devm_clk_get(&pdev->dev, NULL);
2298 if (IS_ERR(i2c_clk))
2299 return PTR_ERR(i2c_clk);
2300 bus->apb_clk = clk_get_rate(i2c_clk);
2301
2302 gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr");
2303 if (IS_ERR(gcr_regmap))
2304 gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2305
2306 if (IS_ERR(gcr_regmap))
2307 return PTR_ERR(gcr_regmap);
2308 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2309
2310 bus->reg = devm_platform_ioremap_resource(pdev, 0);
2311 if (IS_ERR(bus->reg))
2312 return PTR_ERR(bus->reg);
2313
2314 spin_lock_init(&bus->lock);
2315 init_completion(&bus->cmd_complete);
2316
2317 adap = &bus->adap;
2318 adap->owner = THIS_MODULE;
2319 adap->retries = 3;
2320 adap->timeout = msecs_to_jiffies(35);
2321 adap->algo = &npcm_i2c_algo;
2322 adap->quirks = &npcm_i2c_quirks;
2323 adap->algo_data = bus;
2324 adap->dev.parent = &pdev->dev;
2325 adap->dev.of_node = pdev->dev.of_node;
2326 adap->nr = pdev->id;
2327
2328 irq = platform_get_irq(pdev, 0);
2329 if (irq < 0)
2330 return irq;
2331
2332 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2333 dev_name(bus->dev), bus);
2334 if (ret)
2335 return ret;
2336
2337 ret = __npcm_i2c_init(bus, pdev);
2338 if (ret)
2339 return ret;
2340
2341 npcm_i2c_recovery_init(adap);
2342
2343 i2c_set_adapdata(adap, bus);
2344
2345 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2346 bus->num);
2347 ret = i2c_add_numbered_adapter(&bus->adap);
2348 if (ret)
2349 return ret;
2350
2351 platform_set_drvdata(pdev, bus);
2352 npcm_i2c_init_debugfs(pdev, bus);
2353 return 0;
2354 }
2355
npcm_i2c_remove_bus(struct platform_device * pdev)2356 static void npcm_i2c_remove_bus(struct platform_device *pdev)
2357 {
2358 unsigned long lock_flags;
2359 struct npcm_i2c *bus = platform_get_drvdata(pdev);
2360
2361 spin_lock_irqsave(&bus->lock, lock_flags);
2362 npcm_i2c_disable(bus);
2363 spin_unlock_irqrestore(&bus->lock, lock_flags);
2364 i2c_del_adapter(&bus->adap);
2365 }
2366
2367 static const struct of_device_id npcm_i2c_bus_of_table[] = {
2368 { .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data },
2369 { .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data },
2370 {}
2371 };
2372 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2373
2374 static struct platform_driver npcm_i2c_bus_driver = {
2375 .probe = npcm_i2c_probe_bus,
2376 .remove = npcm_i2c_remove_bus,
2377 .driver = {
2378 .name = "nuvoton-i2c",
2379 .of_match_table = npcm_i2c_bus_of_table,
2380 }
2381 };
2382
2383 module_platform_driver(npcm_i2c_bus_driver);
2384
2385 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2386 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2387 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2388 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2389 MODULE_LICENSE("GPL v2");
2390