1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ 14 #define ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_DEC0_CMD 19 * (Prototype: VSI_CMD) 20 ***************************************** 21 */ 22 23 /* DCORE0_DEC0_CMD_SWREG0 */ 24 #define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0 25 #define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF 26 #define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16 27 #define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000 28 29 /* DCORE0_DEC0_CMD_SWREG1 */ 30 #define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0 31 #define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF 32 33 /* DCORE0_DEC0_CMD_SWREG2 */ 34 #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0 35 #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF 36 #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16 37 #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000 38 39 /* DCORE0_DEC0_CMD_SWREG3 */ 40 #define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0 41 #define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF 42 43 /* DCORE0_DEC0_CMD_SWREG4 */ 44 #define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0 45 #define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF 46 47 /* DCORE0_DEC0_CMD_SWREG5 */ 48 #define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0 49 #define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF 50 51 /* DCORE0_DEC0_CMD_SWREG6 */ 52 #define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0 53 #define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF 54 55 /* DCORE0_DEC0_CMD_SWREG7 */ 56 #define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0 57 #define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF 58 59 /* DCORE0_DEC0_CMD_SWREG8 */ 60 #define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0 61 #define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF 62 63 /* DCORE0_DEC0_CMD_SWREG9 */ 64 #define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0 65 #define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF 66 67 /* DCORE0_DEC0_CMD_SWREG10 */ 68 #define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0 69 #define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF 70 71 /* DCORE0_DEC0_CMD_SWREG11 */ 72 #define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0 73 #define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF 74 75 /* DCORE0_DEC0_CMD_SWREG12 */ 76 #define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0 77 #define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF 78 79 /* DCORE0_DEC0_CMD_SWREG13 */ 80 #define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0 81 #define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF 82 83 /* DCORE0_DEC0_CMD_SWREG14 */ 84 #define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0 85 #define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF 86 87 /* DCORE0_DEC0_CMD_SWREG15 */ 88 #define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0 89 #define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7 90 #define DCORE0_DEC0_CMD_SWREG15_RSV_SHIFT 3 91 #define DCORE0_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8 92 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22 93 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000 94 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23 95 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000 96 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24 97 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000 98 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25 99 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000 100 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26 101 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000 102 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27 103 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000 104 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28 105 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000 106 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29 107 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000 108 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30 109 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000 110 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31 111 #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000 112 113 /* DCORE0_DEC0_CMD_SWREG16 */ 114 #define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0 115 #define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1 116 #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1 117 #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2 118 #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2 119 #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4 120 #define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3 121 #define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8 122 #define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4 123 #define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10 124 #define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5 125 #define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20 126 #define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6 127 #define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40 128 #define DCORE0_DEC0_CMD_SWREG16_RSV_SHIFT 7 129 #define DCORE0_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80 130 131 /* DCORE0_DEC0_CMD_SWREG17 */ 132 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0 133 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1 134 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1 135 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2 136 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2 137 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4 138 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3 139 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8 140 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4 141 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10 142 #define DCORE0_DEC0_CMD_SWREG17_RSV_1_SHIFT 5 143 #define DCORE0_DEC0_CMD_SWREG17_RSV_1_MASK 0x20 144 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6 145 #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40 146 #define DCORE0_DEC0_CMD_SWREG17_RSV_SHIFT 7 147 #define DCORE0_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80 148 149 /* DCORE0_DEC0_CMD_SWREG18 */ 150 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0 151 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1 152 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1 153 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2 154 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2 155 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4 156 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3 157 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8 158 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4 159 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10 160 #define DCORE0_DEC0_CMD_SWREG18_RSV_1_SHIFT 5 161 #define DCORE0_DEC0_CMD_SWREG18_RSV_1_MASK 0x20 162 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6 163 #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40 164 #define DCORE0_DEC0_CMD_SWREG18_RSV_SHIFT 7 165 #define DCORE0_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80 166 167 /* DCORE0_DEC0_CMD_SWREG19 */ 168 #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0 169 #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF 170 #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31 171 #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000 172 173 /* DCORE0_DEC0_CMD_SWREG20 */ 174 #define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0 175 #define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF 176 177 /* DCORE0_DEC0_CMD_SWREG21 */ 178 #define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0 179 #define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF 180 181 /* DCORE0_DEC0_CMD_SWREG22 */ 182 #define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0 183 #define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF 184 #define DCORE0_DEC0_CMD_SWREG22_RSV_SHIFT 16 185 #define DCORE0_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000 186 187 /* DCORE0_DEC0_CMD_SWREG23 */ 188 #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0 189 #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF 190 #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8 191 #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00 192 #define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16 193 #define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000 194 #define DCORE0_DEC0_CMD_SWREG23_RSV_SHIFT 24 195 #define DCORE0_DEC0_CMD_SWREG23_RSV_MASK 0xF000000 196 #define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28 197 #define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000 198 199 /* DCORE0_DEC0_CMD_SWREG24 */ 200 #define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0 201 #define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF 202 203 /* DCORE0_DEC0_CMD_SWREG25 */ 204 #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0 205 #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF 206 #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16 207 #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000 208 209 /* DCORE0_DEC0_CMD_SWREG26 */ 210 #define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0 211 #define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF 212 213 /* DCORE0_DEC0_CMD_SWREG64 */ 214 #define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0 215 #define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF 216 217 /* DCORE0_DEC0_CMD_SWREG65 */ 218 #define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0 219 #define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF 220 221 /* DCORE0_DEC0_CMD_SWREG66 */ 222 #define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0 223 #define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF 224 225 /* DCORE0_DEC0_CMD_SWREG67 */ 226 #define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0 227 #define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF 228 229 #endif /* ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ */ 230