| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 693 const double DCFCLK,
699 const double DCFCLK,
706 double DCFCLK,
807 double DCFCLK,
1003 double DCFCLK,
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| H A D | display_mode_vba_util_32.c | 3286 const double DCFCLK, in dml32_get_return_bw_mbps() argument
3291 …e IdealSDPPortBandwidth = soc->return_bus_width_bytes /*mode_lib->vba.ReturnBusWidth*/ * DCFCLK; in dml32_get_return_bw_mbps()
3311 dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK); in dml32_get_return_bw_mbps()
3328 const double DCFCLK, in dml32_get_return_bw_mbps_vm_only() argument
3333 soc->return_bus_width_bytes * DCFCLK * soc->pct_ideal_sdp_bw_after_urgent / 100.0, in dml32_get_return_bw_mbps_vm_only()
3342 dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK); in dml32_get_return_bw_mbps_vm_only()
3353 double DCFCLK, in dml32_CalculateExtraLatency() argument
3386 …ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyByte… in dml32_CalculateExtraLatency()
3390 dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK); in dml32_CalculateExtraLatency()
4262 double DCFCLK, in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() argument
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| H A D | display_mode_vba_32.c | 539 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
545 dml_print("DML::%s: mode_lib->vba.DCFCLK = %f\n", __func__, mode_lib->vba.DCFCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
582 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1194 v->DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1522 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1586 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3732 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 268 double DCFCLK,
445 double DCFCLK,
552 double DCFCLK,
1766 v->ReturnBusWidth * v->DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1923 DTRACE(" dcfclk_mhz = %f", v->DCFCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2236 v->DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2610 v->DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2842 v->DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4941 v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine]; in dml30_ModeSupportAndSystemConfigurationFull()
4953 double DCFCLK, in CalculateWatermarksAndDRAMSpeedChangeSupport() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_core_structs.h | 834 …dml_float_t DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max c… member
1336 dml_float_t DCFCLK; member
1532 dml_float_t DCFCLK; member
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| H A D | display_mode_core.c | 621 dml_float_t DCFCLK,
3969 dml_print("DML::%s: DCFCLK = %f\n", __func__, p->DCFCLK); in CalculateStutterEfficiency()
3972 …th - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (p->DCFCLK * 64) + *p->Stutte… in CalculateStutterEfficiency()
3976 …aReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (p->DCFCLK * 64)); in CalculateStutterEfficiency()
4465 dml_float_t DCFCLK, in CalculateExtraLatency() argument
4498 …ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyByte… in CalculateExtraLatency()
4502 dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK); in CalculateExtraLatency()
5771 dml_float_t DCFCLK, in dml_get_return_bw_mbps_vm_only() argument
5776 dml_min3(soc->return_bus_width_bytes * DCFCLK * soc->pct_ideal_sdp_bw_after_urgent / 100.0, in dml_get_return_bw_mbps_vm_only()
5783 dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK); in dml_get_return_bw_mbps_vm_only()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_vba.h | 438 double DCFCLK; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 5008 double DCFCLK, in CalculateExtraLatency() argument
5066 *ExtraLatency_sr = dchub_arb_to_ret_delay / DCFCLK; in CalculateExtraLatency()
5071 …*ExtraLatency_sr = dchub_arb_to_ret_delay / DCFCLK + RoundTripPingLatencyCycles / FabricClock + Re… in CalculateExtraLatency()
5085 DML_LOG_VERBOSE("DML::%s: DCFCLK=%f\n", __func__, DCFCLK); in CalculateExtraLatency()
7374 mode_lib->ms.DCFCLK, in dml_core_ms_prefetch_check()
7902 CalculateWatermarks_params->DCFCLK = mode_lib->ms.DCFCLK; in dml_core_ms_prefetch_check()
7971 …mode_lib->ms.DCFCLK = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].… in dml_core_mode_support()
7994 DML_LOG_VERBOSE("DML::%s: DCFCLK = %f\n", __func__, mode_lib->ms.DCFCLK); in dml_core_mode_support()
9276 DML_LOG_VERBOSE("DML::%s: mode_lib->ms.DCFCLK = %f\n", __func__, mode_lib->ms.DCFCLK); in dml_core_mode_support()
9307 / (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)); in dml_core_mode_support()
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