| /linux/arch/x86/crypto/ |
| H A D | blowfish-x86_64-asm_64.S | 21 #define CTX %r12 macro
64 movl s0(CTX,RT0,4), RT0d; \
65 addl s1(CTX,RT1,4), RT0d; \
69 xorl s2(CTX,RT1,4), RT0d; \
70 addl s3(CTX,RT2,4), RT0d; \
74 xorq p+4*(n)(CTX), RX0;
83 movq p+4*(n-1)(CTX), RT0; \
110 movq %rdi, CTX;
141 movq %rdi, CTX;
179 movl s0(CTX,RT0,4), RT0d; \
[all …]
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| H A D | twofish-avx-x86_64-asm_64.S | 35 #define CTX %rdi macro
90 movl t0(CTX, RID1, 4), dst ## d; \
91 movl t1(CTX, RID2, 4), RID2d; \
96 xorl t2(CTX, RID1, 4), dst ## d; \
97 xorl t3(CTX, RID2, 4), dst ## d;
173 vbroadcastss (k+4*(2*(n)))(CTX), RK1; \
174 vbroadcastss (k+4*(2*(n)+1))(CTX), RK2; \
181 vbroadcastss (k+4*(2*(n)))(CTX), RK1; \
182 vbroadcastss (k+4*(2*(n)+1))(CTX), RK2; \
239 vmovdqu w(CTX), RK1;
[all …]
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| H A D | cast6-avx-x86_64-asm_64.S | 35 #define CTX %r15 macro
150 vbroadcastss (km+(4*(nn)))(CTX), RKM; \
187 vpxor (kr+n*16)(CTX), RKR, RKR; \
263 movq %rdi, CTX;
311 movq %rdi, CTX;
355 movq %rdi, CTX;
378 movq %rdi, CTX;
402 movq %rdi, CTX;
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| /linux/lib/crypto/x86/ |
| H A D | blake2s-core.S | 53 #define CTX %rdi macro
69 movdqu (CTX),%xmm0 // Load h[0..3]
70 movdqu 16(CTX),%xmm1 // Load h[4..7]
73 movdqu 32(CTX),%xmm14 // Load t and f
194 movdqu %xmm0,(CTX) // Store new h[0..3]
195 movdqu %xmm1,16(CTX) // Store new h[4..7]
196 movq %xmm14,32(CTX) // Store new t (f is unchanged)
210 vmovdqu (CTX),%xmm0 // Load h[0..3]
211 vmovdqu 16(CTX),%xmm1 // Load h[4..7]
212 vmovdqu 32(CTX),%xmm4 // Load t and f
[all …]
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| H A D | sha256-avx2-asm.S | 94 CTX = %rdi # 1st arg define
100 SRND = CTX # SRND is same register as CTX
545 mov (CTX), a
546 mov 4*1(CTX), b
547 mov 4*2(CTX), c
548 mov 4*3(CTX), d
549 mov 4*4(CTX), e
550 mov 4*5(CTX), f
551 mov 4*6(CTX), g
552 mov 4*7(CTX), h
[all …]
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| H A D | sha256-avx-asm.S | 99 CTX = %rdi # 1st arg define
364 mov 4*0(CTX), a
365 mov 4*1(CTX), b
366 mov 4*2(CTX), c
367 mov 4*3(CTX), d
368 mov 4*4(CTX), e
369 mov 4*5(CTX), f
370 mov 4*6(CTX), g
371 mov 4*7(CTX), h
434 addm (4*0)(CTX),a
[all …]
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| H A D | sha256-ssse3-asm.S | 92 CTX = %rdi # 1st arg define
371 mov 4*0(CTX), a
372 mov 4*1(CTX), b
373 mov 4*2(CTX), c
374 mov 4*3(CTX), d
375 mov 4*4(CTX), e
376 mov 4*5(CTX), f
377 mov 4*6(CTX), g
378 mov 4*7(CTX), h
445 addm (4*0)(CTX),a
[all …]
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| H A D | sha256-ni-asm.S | 185 #define CTX %rdi macro
296 movdqu OFFSETOF_STATE+0*16(CTX), STATE0_A // DCBA
297 movdqu OFFSETOF_STATE+1*16(CTX), STATE1_A // HGFE
308 mov OFFSETOF_BYTECOUNT(CTX), %rbx
318 movdqu OFFSETOF_BUF+0*16(CTX), MSG0_A
319 movdqu OFFSETOF_BUF+1*16(CTX), MSG1_A
320 movdqu OFFSETOF_BUF+2*16(CTX), MSG2_A
321 movdqu OFFSETOF_BUF+3*16(CTX), MSG3_A
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 51 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
54 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
59 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
86 dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
112 dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
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| H A D | dmub_dcn301.c | 35 #define CTX dmub macro
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| H A D | dmub_dcn303.c | 36 #define CTX dmub macro
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| H A D | dmub_dcn21.c | 35 #define CTX dmub macro
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| H A D | dmub_dcn302.c | 35 #define CTX dmub macro
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| H A D | dmub_dcn316.c | 41 #define CTX dmub macro
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| H A D | dmub_dcn315.c | 41 #define CTX dmub macro
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| H A D | dmub_dcn314.c | 41 #define CTX dmub macro
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_vmid.c | 34 #define CTX \ macro
42 CTX->logger
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30m_clk_mgr_smu_msg.c | 44 CTX->logger
95 dm_helpers_smu_timeout(CTX, msg_id, param_in, 10 * 200000); in dcn30m_smu_send_msg_with_param()
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/ |
| H A D | dcn301_hubbub.c | 33 #define CTX \ macro
43 #define CTX \ macro
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/ |
| H A D | dcn201_hubbub.c | 36 #define CTX \ macro
46 #define CTX \ macro
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn301/ |
| H A D | dcn301_hwseq.c | 33 #define CTX \ macro
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| /linux/arch/sparc/kernel/ |
| H A D | sun4v_tlb_miss.S | 11 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \ argument
13 ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
16 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \ argument
18 ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
24 #define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \ argument
26 brz,pn CTX, ZERO_CTX_LABEL; \
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 48 CTX->logger
126 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); in dcn301_smu_send_msg_with_param()
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| /linux/lib/crypto/arm/ |
| H A D | blake2b-neon-core.S | 19 CTX .req r0
261 mov ip, CTX
293 mov ip, CTX
325 mov ip, CTX
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| /linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/ |
| H A D | dcn35_mmhubbub.c | 34 #define CTX mcif_wb30->base.ctx macro
|