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Searched refs:CTRL_ENABLE (Results 1 – 4 of 4) sorted by relevance

/linux/arch/arm/mach-spear/
H A Dtime.c43 #define CTRL_ENABLE 0x0020 macro
85 val |= CTRL_ENABLE ; in spear_clocksource_init()
98 val &= ~CTRL_ENABLE; in spear_timer_shutdown()
137 val |= CTRL_ENABLE | CTRL_INT_ENABLE; in spear_set_periodic()
159 if (val & CTRL_ENABLE) in clockevent_next_event()
160 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); in clockevent_next_event()
164 val |= CTRL_ENABLE | CTRL_INT_ENABLE; in clockevent_next_event()
/linux/drivers/clk/
H A Dclk-apple-nco.c24 #define CTRL_ENABLE BIT(31) macro
83 writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL); in applnco_enable_nolock()
92 writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL); in applnco_disable_nolock()
99 return (readl_relaxed(chan->base + REG_CTRL) & CTRL_ENABLE) != 0; in applnco_is_enabled()
/linux/drivers/pwm/
H A Dpwm-vt8500.c34 #define CTRL_ENABLE BIT(0) macro
139 val |= CTRL_ENABLE; in vt8500_pwm_enable()
152 val &= ~CTRL_ENABLE; in vt8500_pwm_disable()
/linux/drivers/iommu/
H A Dexynos-iommu.c130 #define CTRL_ENABLE 0x5 macro
429 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); in sysmmu_unblock()
658 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); in __sysmmu_enable()