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Searched refs:CTL (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_eeprom.c39 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) macro
284 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
285 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
286 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
288 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
289 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
290 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
294 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
[all …]
/linux/sound/pci/lola/
H A Dlola_pcm.c64 lola_dsd_write(chip, str->dsd, CTL, in lola_stream_start()
75 lola_dsd_write(chip, str->dsd, CTL, in lola_stream_stop()
88 val = lola_dsd_read(chip, str->dsd, CTL); in wait_for_srst_clear()
163 lola_dsd_write(chip, str->dsd, CTL, LOLA_DSD_CTL_SRUN | in lola_sync_pause()
175 lola_dsd_write(chip, str->dsd, CTL, in lola_stream_reset()
179 lola_dsd_write(chip, str->dsd, CTL, LOLA_DSD_CTL_SRST); in lola_stream_reset()
443 lola_dsd_write(chip, str->dsd, CTL, in lola_setup_controller()
H A Dlola_proc.c186 lola_dsd_read(chip, i, CTL)); in lola_proc_regs_read()
/linux/Documentation/devicetree/bindings/net/
H A Dmicrel-ksz90x1.txt49 - rxdv-skew-ps : Skew control of RX CTL pad
51 - txen-skew-ps : Skew control of TX CTL pad
142 - rxdv-skew-ps : Skew control of RX CTL pad
143 - txen-skew-ps : Skew control of TX CTL pad
176 - rxdv-skew-psec : Skew control of RX CTL pad
177 - txen-skew-psec : Skew control of TX CTL pad
/linux/drivers/clk/imx/
H A DKconfig119 tristate "IMX95 Clock Driver for BLK CTL"
123 Build the clock driver for i.MX95 BLK CTL
/linux/Documentation/gpu/amdgpu/display/
H A Dtrace-groups-table.csv19 TRANSMITTER CTL, 0x20000
/linux/drivers/char/xilinx_hwicap/
H A Dxilinx_hwicap.h130 u32 CTL; member
/linux/drivers/net/wan/
H A Dc101.c184 sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */ in c101_open()
206 sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port); in c101_close()
H A Dhd64570.h63 #define CTL 0x11 /* Control */ macro
H A Dhd64572.h64 #define CTL 0x130 /* Control reg */ macro
H A Dhd64572.c459 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card); in sca_open()
H A Dhd64570.c501 sca_out(CTL_IDLE, msci + CTL, card); in sca_open()
/linux/sound/soc/qcom/
H A Dlpass-lpaif-reg.h159 __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
160 __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-etb1066 is read directly from HW register CTL, 0x020.
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-gateworks-gw2348.dts100 /* First register set is CMD second is CTL (notice it uses CS2) */
H A Dintel-ixp43x-gateworks-gw2358.dts116 /* First register set is CMD second is CTL */
/linux/drivers/media/dvb-frontends/
H A Dbcm3510_priv.h29 u8 CTL :8; member
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dfwsignal.c981 brcmf_dbg(CTL, "rssi %d\n", rssi); in brcmf_fws_rssi_indicate()
1590 brcmf_dbg(CTL, "received: seq %d, timestamp %d\n", data[1], in brcmf_fws_dbg_seqnum_check()