1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2025 Intel Corporation
5 */
6 #include "iwl-trans.h"
7 #include "iwl-prph.h"
8 #include "iwl-context-info.h"
9 #include "iwl-context-info-gen3.h"
10 #include "internal.h"
11 #include "fw/dbg.h"
12
13 #define FW_RESET_TIMEOUT (HZ / 5)
14
15 /*
16 * Start up NIC's basic functionality after it has been reset
17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
18 * NOTE: This does not load uCode nor start the embedded processor
19 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
21 {
22 int ret = 0;
23
24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
25
26 /*
27 * Use "set_bit" below rather than "write", to preserve any hardware
28 * bits already set by default after reset.
29 */
30
31 /*
32 * Disable L0s without affecting L1;
33 * don't wait for ICH L0s (ICH bug W/A)
34 */
35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
37
38 /* Set FH wait threshold to maximum (HW error during stress W/A) */
39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
40
41 /*
42 * Enable HAP INTA (interrupt from management bus) to
43 * wake device's PCI Express link L1a -> L0s
44 */
45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
46 CSR_HW_IF_CONFIG_REG_HAP_WAKE);
47
48 iwl_pcie_apm_config(trans);
49
50 ret = iwl_finish_nic_init(trans);
51 if (ret)
52 return ret;
53
54 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
55
56 return 0;
57 }
58
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
60 {
61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
62
63 if (op_mode_leave) {
64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
65 iwl_pcie_gen2_apm_init(trans);
66
67 /* inform ME that we are leaving */
68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
69 CSR_RESET_LINK_PWR_MGMT_DISABLED);
70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
71 CSR_HW_IF_CONFIG_REG_WAKE_ME |
72 CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
73 mdelay(1);
74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
75 CSR_RESET_LINK_PWR_MGMT_DISABLED);
76 mdelay(5);
77 }
78
79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
80
81 /* Stop device's DMA activity */
82 iwl_pcie_apm_stop_master(trans);
83
84 iwl_trans_sw_reset(trans, false);
85
86 /*
87 * Clear "initialization complete" bit to move adapter from
88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
89 */
90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
91 iwl_clear_bit(trans, CSR_GP_CNTRL,
92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
93 else
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
96 }
97
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)98 void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
99 {
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 int ret;
102
103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
104
105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
108 else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
111 else
112 iwl_write32(trans, CSR_DOORBELL_VECTOR,
113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114
115 /* wait 200ms */
116 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
117 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
118 FW_RESET_TIMEOUT);
119 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
120 u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
121
122 IWL_ERR(trans,
123 "timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
124 inta_hw);
125
126 if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE)) {
127 struct iwl_fw_error_dump_mode mode = {
128 .type = IWL_ERR_TYPE_RESET_HS_TIMEOUT,
129 .context = IWL_ERR_CONTEXT_FROM_OPMODE,
130 };
131 iwl_op_mode_nic_error(trans->op_mode,
132 IWL_ERR_TYPE_RESET_HS_TIMEOUT);
133 iwl_op_mode_dump_error(trans->op_mode, &mode);
134 }
135 }
136
137 trans_pcie->fw_reset_state = FW_RESET_IDLE;
138 }
139
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)140 static void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
141 {
142 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
143
144 lockdep_assert_held(&trans_pcie->mutex);
145
146 if (trans_pcie->is_down)
147 return;
148
149 if (trans->state >= IWL_TRANS_FW_STARTED &&
150 trans_pcie->fw_reset_handshake)
151 iwl_trans_pcie_fw_reset_handshake(trans);
152
153 trans_pcie->is_down = true;
154
155 /* tell the device to stop sending interrupts */
156 iwl_disable_interrupts(trans);
157
158 /* device going down, Stop using ICT table */
159 iwl_pcie_disable_ict(trans);
160
161 /*
162 * If a HW restart happens during firmware loading,
163 * then the firmware loading might call this function
164 * and later it might be called again due to the
165 * restart. So don't process again if the device is
166 * already dead.
167 */
168 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
169 IWL_DEBUG_INFO(trans,
170 "DEVICE_ENABLED bit was set and is now cleared\n");
171 iwl_pcie_synchronize_irqs(trans);
172 iwl_pcie_rx_napi_sync(trans);
173 iwl_txq_gen2_tx_free(trans);
174 iwl_pcie_rx_stop(trans);
175 }
176
177 iwl_pcie_ctxt_info_free_paging(trans);
178 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
179 iwl_pcie_ctxt_info_gen3_free(trans, false);
180 else
181 iwl_pcie_ctxt_info_free(trans);
182
183 /* Stop the device, and put it in low power state */
184 iwl_pcie_gen2_apm_stop(trans, false);
185
186 /* re-take ownership to prevent other users from stealing the device */
187 iwl_trans_sw_reset(trans, true);
188
189 /*
190 * Upon stop, the IVAR table gets erased, so msi-x won't
191 * work. This causes a bug in RF-KILL flows, since the interrupt
192 * that enables radio won't fire on the correct irq, and the
193 * driver won't be able to handle the interrupt.
194 * Configure the IVAR table again after reset.
195 */
196 iwl_pcie_conf_msix_hw(trans_pcie);
197
198 /*
199 * Upon stop, the APM issues an interrupt if HW RF kill is set.
200 * This is a bug in certain verions of the hardware.
201 * Certain devices also keep sending HW RF kill interrupt all
202 * the time, unless the interrupt is ACKed even if the interrupt
203 * should be masked. Re-ACK all the interrupts here.
204 */
205 iwl_disable_interrupts(trans);
206
207 /* clear all status bits */
208 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
209 clear_bit(STATUS_INT_ENABLED, &trans->status);
210 clear_bit(STATUS_TPOWER_PMI, &trans->status);
211
212 /*
213 * Even if we stop the HW, we still want the RF kill
214 * interrupt
215 */
216 iwl_enable_rfkill_int(trans);
217 }
218
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)219 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
220 {
221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
222 bool was_in_rfkill;
223
224 iwl_op_mode_time_point(trans->op_mode,
225 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
226 NULL);
227
228 mutex_lock(&trans_pcie->mutex);
229 trans_pcie->opmode_down = true;
230 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
231 _iwl_trans_pcie_gen2_stop_device(trans);
232 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
233 mutex_unlock(&trans_pcie->mutex);
234 }
235
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)236 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
237 {
238 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
239 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
240 trans->cfg->min_txq_size);
241 int ret;
242
243 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
244 spin_lock_bh(&trans_pcie->irq_lock);
245 ret = iwl_pcie_gen2_apm_init(trans);
246 spin_unlock_bh(&trans_pcie->irq_lock);
247 if (ret)
248 return ret;
249
250 iwl_op_mode_nic_config(trans->op_mode);
251
252 /* Allocate the RX queue, or reset if it is already allocated */
253 if (iwl_pcie_gen2_rx_init(trans))
254 return -ENOMEM;
255
256 /* Allocate or reset and init all Tx and Command queues */
257 if (iwl_txq_gen2_init(trans, trans_pcie->txqs.cmd.q_id, queue_size))
258 return -ENOMEM;
259
260 /* enable shadow regs in HW */
261 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
262 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
263
264 return 0;
265 }
266
iwl_pcie_get_rf_name(struct iwl_trans * trans)267 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
268 {
269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
270 char *buf = trans_pcie->rf_name;
271 size_t buflen = sizeof(trans_pcie->rf_name);
272 size_t pos;
273 u32 version;
274
275 if (buf[0])
276 return;
277
278 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
279 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
280 pos = scnprintf(buf, buflen, "JF");
281 break;
282 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
283 pos = scnprintf(buf, buflen, "GF");
284 break;
285 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
286 pos = scnprintf(buf, buflen, "GF4");
287 break;
288 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
289 pos = scnprintf(buf, buflen, "HR");
290 break;
291 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
292 pos = scnprintf(buf, buflen, "HR1");
293 break;
294 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
295 pos = scnprintf(buf, buflen, "HRCDB");
296 break;
297 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_FM):
298 pos = scnprintf(buf, buflen, "FM");
299 break;
300 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_WP):
301 if (SILICON_Z_STEP ==
302 CSR_HW_RFID_STEP(trans->hw_rf_id))
303 pos = scnprintf(buf, buflen, "WHTC");
304 else
305 pos = scnprintf(buf, buflen, "WH");
306 break;
307 default:
308 return;
309 }
310
311 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
312 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
313 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
314 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
315 version = iwl_read_prph(trans, CNVI_MBOX_C);
316 switch (version) {
317 case 0x20000:
318 pos += scnprintf(buf + pos, buflen - pos, " B3");
319 break;
320 case 0x120000:
321 pos += scnprintf(buf + pos, buflen - pos, " B5");
322 break;
323 default:
324 pos += scnprintf(buf + pos, buflen - pos,
325 " (0x%x)", version);
326 break;
327 }
328 break;
329 default:
330 break;
331 }
332
333 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
334 trans->hw_rf_id);
335
336 IWL_INFO(trans, "Detected RF %s\n", buf);
337
338 /*
339 * also add a \n for debugfs - need to do it after printing
340 * since our IWL_INFO machinery wants to see a static \n at
341 * the end of the string
342 */
343 pos += scnprintf(buf + pos, buflen - pos, "\n");
344 }
345
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans)346 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)
347 {
348 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
349
350 iwl_pcie_reset_ict(trans);
351
352 /* make sure all queue are not stopped/used */
353 memset(trans_pcie->txqs.queue_stopped, 0,
354 sizeof(trans_pcie->txqs.queue_stopped));
355 memset(trans_pcie->txqs.queue_used, 0,
356 sizeof(trans_pcie->txqs.queue_used));
357
358 /* now that we got alive we can free the fw image & the context info.
359 * paging memory cannot be freed included since FW will still use it
360 */
361 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
362 iwl_pcie_ctxt_info_gen3_free(trans, true);
363 else
364 iwl_pcie_ctxt_info_free(trans);
365
366 /*
367 * Re-enable all the interrupts, including the RF-Kill one, now that
368 * the firmware is alive.
369 */
370 iwl_enable_interrupts(trans);
371 mutex_lock(&trans_pcie->mutex);
372 iwl_pcie_check_hw_rf_kill(trans);
373
374 iwl_pcie_get_rf_name(trans);
375 mutex_unlock(&trans_pcie->mutex);
376 }
377
iwl_pcie_set_ltr(struct iwl_trans * trans)378 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
379 {
380 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
381 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
382 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
383 u32_encode_bits(250,
384 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
385 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
386 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
387 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
388 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
389
390 /*
391 * To workaround hardware latency issues during the boot process,
392 * initialize the LTR to ~250 usec (see ltr_val above).
393 * The firmware initializes this again later (to a smaller value).
394 */
395 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
396 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
397 !trans->trans_cfg->integrated) {
398 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
399 return true;
400 }
401
402 if (trans->trans_cfg->integrated &&
403 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
404 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
405 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
406 return true;
407 }
408
409 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
410 /* First clear the interrupt, just in case */
411 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
412 MSIX_HW_INT_CAUSES_REG_IML);
413 /* In this case, unfortunately the same ROM bug exists in the
414 * device (not setting LTR correctly), but we don't have control
415 * over the settings from the host due to some hardware security
416 * features. The only workaround we've been able to come up with
417 * so far is to try to keep the CPU and device busy by polling
418 * it and the IML (image loader) completed interrupt.
419 */
420 return false;
421 }
422
423 /* nothing needs to be done on other devices */
424 return true;
425 }
426
iwl_pcie_spin_for_iml(struct iwl_trans * trans)427 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
428 {
429 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
430 #define IML_WAIT_TIMEOUT (HZ / 10)
431 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
432 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
433 u32 value, loops = 0;
434 bool irq = false;
435
436 if (WARN_ON(!trans_pcie->iml))
437 return;
438
439 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
440 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
441 value);
442
443 while (time_before(jiffies, end_time)) {
444 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
445 MSIX_HW_INT_CAUSES_REG_IML) {
446 irq = true;
447 break;
448 }
449 /* Keep the CPU and device busy. */
450 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
451 loops++;
452 }
453
454 IWL_DEBUG_INFO(trans,
455 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
456 irq, loops, value);
457
458 /* We don't fail here even if we timed out - maybe we get lucky and the
459 * interrupt comes in later (and we get alive from firmware) and then
460 * we're all happy - but if not we'll fail on alive timeout or get some
461 * other error out.
462 */
463 }
464
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)465 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
466 const struct fw_img *fw, bool run_in_rfkill)
467 {
468 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
469 bool hw_rfkill, keep_ram_busy;
470 int ret;
471
472 /* This may fail if AMT took ownership of the device */
473 if (iwl_pcie_prepare_card_hw(trans)) {
474 IWL_WARN(trans, "Exit HW not ready\n");
475 return -EIO;
476 }
477
478 iwl_enable_rfkill_int(trans);
479
480 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
481
482 /*
483 * We enabled the RF-Kill interrupt and the handler may very
484 * well be running. Disable the interrupts to make sure no other
485 * interrupt can be fired.
486 */
487 iwl_disable_interrupts(trans);
488
489 /* Make sure it finished running */
490 iwl_pcie_synchronize_irqs(trans);
491
492 mutex_lock(&trans_pcie->mutex);
493
494 /* If platform's RF_KILL switch is NOT set to KILL */
495 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
496 if (hw_rfkill && !run_in_rfkill) {
497 ret = -ERFKILL;
498 goto out;
499 }
500
501 /* Someone called stop_device, don't try to start_fw */
502 if (trans_pcie->is_down) {
503 IWL_WARN(trans,
504 "Can't start_fw since the HW hasn't been started\n");
505 ret = -EIO;
506 goto out;
507 }
508
509 /* make sure rfkill handshake bits are cleared */
510 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
511 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
512 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
513
514 /* clear (again), then enable host interrupts */
515 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
516
517 ret = iwl_pcie_gen2_nic_init(trans);
518 if (ret) {
519 IWL_ERR(trans, "Unable to init nic\n");
520 goto out;
521 }
522
523 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
524 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
525 else
526 ret = iwl_pcie_ctxt_info_init(trans, fw);
527 if (ret)
528 goto out;
529
530 keep_ram_busy = !iwl_pcie_set_ltr(trans);
531
532 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
533 IWL_DEBUG_POWER(trans, "function scratch register value is 0x%08x\n",
534 iwl_read32(trans, CSR_FUNC_SCRATCH));
535 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
536 iwl_set_bit(trans, CSR_GP_CNTRL,
537 CSR_GP_CNTRL_REG_FLAG_ROM_START);
538 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
539 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
540 } else {
541 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
542 }
543
544 if (keep_ram_busy)
545 iwl_pcie_spin_for_iml(trans);
546
547 /* re-check RF-Kill state since we may have missed the interrupt */
548 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
549 if (hw_rfkill && !run_in_rfkill)
550 ret = -ERFKILL;
551
552 out:
553 mutex_unlock(&trans_pcie->mutex);
554 return ret;
555 }
556