1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * HD audio codec driver for Cirrus Logic CS8409 HDA bridge chip 4 * 5 * Copyright (C) 2021 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #ifndef __CS8409_PATCH_H 10 #define __CS8409_PATCH_H 11 12 #include <linux/pci.h> 13 #include <sound/tlv.h> 14 #include <linux/workqueue.h> 15 #include <sound/cs42l42.h> 16 #include <sound/hda_codec.h> 17 #include "hda_local.h" 18 #include "hda_auto_parser.h" 19 #include "hda_jack.h" 20 #include "../generic.h" 21 #include "../side-codecs/hda_component.h" 22 23 /* CS8409 Specific Definitions */ 24 25 enum cs8409_pins { 26 CS8409_PIN_ROOT, 27 CS8409_PIN_AFG, 28 CS8409_PIN_ASP1_OUT_A, 29 CS8409_PIN_ASP1_OUT_B, 30 CS8409_PIN_ASP1_OUT_C, 31 CS8409_PIN_ASP1_OUT_D, 32 CS8409_PIN_ASP1_OUT_E, 33 CS8409_PIN_ASP1_OUT_F, 34 CS8409_PIN_ASP1_OUT_G, 35 CS8409_PIN_ASP1_OUT_H, 36 CS8409_PIN_ASP2_OUT_A, 37 CS8409_PIN_ASP2_OUT_B, 38 CS8409_PIN_ASP2_OUT_C, 39 CS8409_PIN_ASP2_OUT_D, 40 CS8409_PIN_ASP2_OUT_E, 41 CS8409_PIN_ASP2_OUT_F, 42 CS8409_PIN_ASP2_OUT_G, 43 CS8409_PIN_ASP2_OUT_H, 44 CS8409_PIN_ASP1_IN_A, 45 CS8409_PIN_ASP1_IN_B, 46 CS8409_PIN_ASP1_IN_C, 47 CS8409_PIN_ASP1_IN_D, 48 CS8409_PIN_ASP1_IN_E, 49 CS8409_PIN_ASP1_IN_F, 50 CS8409_PIN_ASP1_IN_G, 51 CS8409_PIN_ASP1_IN_H, 52 CS8409_PIN_ASP2_IN_A, 53 CS8409_PIN_ASP2_IN_B, 54 CS8409_PIN_ASP2_IN_C, 55 CS8409_PIN_ASP2_IN_D, 56 CS8409_PIN_ASP2_IN_E, 57 CS8409_PIN_ASP2_IN_F, 58 CS8409_PIN_ASP2_IN_G, 59 CS8409_PIN_ASP2_IN_H, 60 CS8409_PIN_DMIC1, 61 CS8409_PIN_DMIC2, 62 CS8409_PIN_ASP1_TRANSMITTER_A, 63 CS8409_PIN_ASP1_TRANSMITTER_B, 64 CS8409_PIN_ASP1_TRANSMITTER_C, 65 CS8409_PIN_ASP1_TRANSMITTER_D, 66 CS8409_PIN_ASP1_TRANSMITTER_E, 67 CS8409_PIN_ASP1_TRANSMITTER_F, 68 CS8409_PIN_ASP1_TRANSMITTER_G, 69 CS8409_PIN_ASP1_TRANSMITTER_H, 70 CS8409_PIN_ASP2_TRANSMITTER_A, 71 CS8409_PIN_ASP2_TRANSMITTER_B, 72 CS8409_PIN_ASP2_TRANSMITTER_C, 73 CS8409_PIN_ASP2_TRANSMITTER_D, 74 CS8409_PIN_ASP2_TRANSMITTER_E, 75 CS8409_PIN_ASP2_TRANSMITTER_F, 76 CS8409_PIN_ASP2_TRANSMITTER_G, 77 CS8409_PIN_ASP2_TRANSMITTER_H, 78 CS8409_PIN_ASP1_RECEIVER_A, 79 CS8409_PIN_ASP1_RECEIVER_B, 80 CS8409_PIN_ASP1_RECEIVER_C, 81 CS8409_PIN_ASP1_RECEIVER_D, 82 CS8409_PIN_ASP1_RECEIVER_E, 83 CS8409_PIN_ASP1_RECEIVER_F, 84 CS8409_PIN_ASP1_RECEIVER_G, 85 CS8409_PIN_ASP1_RECEIVER_H, 86 CS8409_PIN_ASP2_RECEIVER_A, 87 CS8409_PIN_ASP2_RECEIVER_B, 88 CS8409_PIN_ASP2_RECEIVER_C, 89 CS8409_PIN_ASP2_RECEIVER_D, 90 CS8409_PIN_ASP2_RECEIVER_E, 91 CS8409_PIN_ASP2_RECEIVER_F, 92 CS8409_PIN_ASP2_RECEIVER_G, 93 CS8409_PIN_ASP2_RECEIVER_H, 94 CS8409_PIN_DMIC1_IN, 95 CS8409_PIN_DMIC2_IN, 96 CS8409_PIN_BEEP_GEN, 97 CS8409_PIN_VENDOR_WIDGET 98 }; 99 100 enum cs8409_coefficient_index_registers { 101 CS8409_DEV_CFG1, 102 CS8409_DEV_CFG2, 103 CS8409_DEV_CFG3, 104 CS8409_ASP1_CLK_CTRL1, 105 CS8409_ASP1_CLK_CTRL2, 106 CS8409_ASP1_CLK_CTRL3, 107 CS8409_ASP2_CLK_CTRL1, 108 CS8409_ASP2_CLK_CTRL2, 109 CS8409_ASP2_CLK_CTRL3, 110 CS8409_DMIC_CFG, 111 CS8409_BEEP_CFG, 112 ASP1_RX_NULL_INS_RMV, 113 ASP1_Rx_RATE1, 114 ASP1_Rx_RATE2, 115 ASP1_Tx_NULL_INS_RMV, 116 ASP1_Tx_RATE1, 117 ASP1_Tx_RATE2, 118 ASP2_Rx_NULL_INS_RMV, 119 ASP2_Rx_RATE1, 120 ASP2_Rx_RATE2, 121 ASP2_Tx_NULL_INS_RMV, 122 ASP2_Tx_RATE1, 123 ASP2_Tx_RATE2, 124 ASP1_SYNC_CTRL, 125 ASP2_SYNC_CTRL, 126 ASP1_A_TX_CTRL1, 127 ASP1_A_TX_CTRL2, 128 ASP1_B_TX_CTRL1, 129 ASP1_B_TX_CTRL2, 130 ASP1_C_TX_CTRL1, 131 ASP1_C_TX_CTRL2, 132 ASP1_D_TX_CTRL1, 133 ASP1_D_TX_CTRL2, 134 ASP1_E_TX_CTRL1, 135 ASP1_E_TX_CTRL2, 136 ASP1_F_TX_CTRL1, 137 ASP1_F_TX_CTRL2, 138 ASP1_G_TX_CTRL1, 139 ASP1_G_TX_CTRL2, 140 ASP1_H_TX_CTRL1, 141 ASP1_H_TX_CTRL2, 142 ASP2_A_TX_CTRL1, 143 ASP2_A_TX_CTRL2, 144 ASP2_B_TX_CTRL1, 145 ASP2_B_TX_CTRL2, 146 ASP2_C_TX_CTRL1, 147 ASP2_C_TX_CTRL2, 148 ASP2_D_TX_CTRL1, 149 ASP2_D_TX_CTRL2, 150 ASP2_E_TX_CTRL1, 151 ASP2_E_TX_CTRL2, 152 ASP2_F_TX_CTRL1, 153 ASP2_F_TX_CTRL2, 154 ASP2_G_TX_CTRL1, 155 ASP2_G_TX_CTRL2, 156 ASP2_H_TX_CTRL1, 157 ASP2_H_TX_CTRL2, 158 ASP1_A_RX_CTRL1, 159 ASP1_A_RX_CTRL2, 160 ASP1_B_RX_CTRL1, 161 ASP1_B_RX_CTRL2, 162 ASP1_C_RX_CTRL1, 163 ASP1_C_RX_CTRL2, 164 ASP1_D_RX_CTRL1, 165 ASP1_D_RX_CTRL2, 166 ASP1_E_RX_CTRL1, 167 ASP1_E_RX_CTRL2, 168 ASP1_F_RX_CTRL1, 169 ASP1_F_RX_CTRL2, 170 ASP1_G_RX_CTRL1, 171 ASP1_G_RX_CTRL2, 172 ASP1_H_RX_CTRL1, 173 ASP1_H_RX_CTRL2, 174 ASP2_A_RX_CTRL1, 175 ASP2_A_RX_CTRL2, 176 ASP2_B_RX_CTRL1, 177 ASP2_B_RX_CTRL2, 178 ASP2_C_RX_CTRL1, 179 ASP2_C_RX_CTRL2, 180 ASP2_D_RX_CTRL1, 181 ASP2_D_RX_CTRL2, 182 ASP2_E_RX_CTRL1, 183 ASP2_E_RX_CTRL2, 184 ASP2_F_RX_CTRL1, 185 ASP2_F_RX_CTRL2, 186 ASP2_G_RX_CTRL1, 187 ASP2_G_RX_CTRL2, 188 ASP2_H_RX_CTRL1, 189 ASP2_H_RX_CTRL2, 190 CS8409_I2C_ADDR, 191 CS8409_I2C_DATA, 192 CS8409_I2C_CTRL, 193 CS8409_I2C_STS, 194 CS8409_I2C_QWRITE, 195 CS8409_I2C_QREAD, 196 CS8409_SPI_CTRL, 197 CS8409_SPI_TX_DATA, 198 CS8409_SPI_RX_DATA, 199 CS8409_SPI_STS, 200 CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/ 201 CS8409_PFE_COEF_W2, 202 CS8409_PFE_CTRL1, 203 CS8409_PFE_CTRL2, 204 CS8409_PRE_SCALE_ATTN1, 205 CS8409_PRE_SCALE_ATTN2, 206 CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/ 207 CS8409_PFE_COEF_MON2, 208 CS8409_ASP1_INTRN_STS, 209 CS8409_ASP2_INTRN_STS, 210 CS8409_ASP1_RX_SCLK_COUNT, 211 CS8409_ASP1_TX_SCLK_COUNT, 212 CS8409_ASP2_RX_SCLK_COUNT, 213 CS8409_ASP2_TX_SCLK_COUNT, 214 CS8409_ASP_UNS_RESP_MASK, 215 CS8409_LOOPBACK_CTRL = 0x80, 216 CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */ 217 }; 218 219 /* CS42L42 Specific Definitions */ 220 221 #define CS8409_MAX_CODECS 8 222 #define CS42L42_VOLUMES (4U) 223 #define CS42L42_HP_VOL_REAL_MIN (-63) 224 #define CS42L42_HP_VOL_REAL_MAX (0) 225 #define CS42L42_AMIC_VOL_REAL_MIN (-97) 226 #define CS42L42_AMIC_VOL_REAL_MAX (12) 227 #define CS42L42_REG_AMIC_VOL_MASK (0x00FF) 228 #define CS42L42_HSTYPE_MASK (0x03) 229 #define CS42L42_I2C_TIMEOUT_US (20000) 230 #define CS42L42_I2C_SLEEP_US (2000) 231 #define CS42L42_PDN_TIMEOUT_US (250000) 232 #define CS42L42_PDN_SLEEP_US (2000) 233 #define CS42L42_ANA_MUTE_AB (0x0C) 234 #define CS42L42_FULL_SCALE_VOL_MASK (2) 235 #define CS42L42_FULL_SCALE_VOL_0DB (0) 236 #define CS42L42_FULL_SCALE_VOL_MINUS6DB (1) 237 238 /* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */ 239 240 #define CS42L42_I2C_ADDR (0x48 << 1) 241 #define CS8409_CS42L42_RESET GENMASK(5, 5) /* CS8409_GPIO5 */ 242 #define CS8409_CS42L42_INT GENMASK(4, 4) /* CS8409_GPIO4 */ 243 #define CS8409_CYBORG_SPEAKER_PDN GENMASK(2, 2) /* CS8409_GPIO2 */ 244 #define CS8409_WARLOCK_SPEAKER_PDN GENMASK(1, 1) /* CS8409_GPIO1 */ 245 #define CS8409_CS42L42_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A 246 #define CS8409_CS42L42_SPK_PIN_NID CS8409_PIN_ASP2_TRANSMITTER_A 247 #define CS8409_CS42L42_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A 248 #define CS8409_CS42L42_DMIC_PIN_NID CS8409_PIN_DMIC1_IN 249 #define CS8409_CS42L42_DMIC_ADC_PIN_NID CS8409_PIN_DMIC1 250 251 /* Dolphin */ 252 253 #define DOLPHIN_C0_I2C_ADDR (0x48 << 1) 254 #define DOLPHIN_C1_I2C_ADDR (0x49 << 1) 255 #define DOLPHIN_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A 256 #define DOLPHIN_LO_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_B 257 #define DOLPHIN_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A 258 259 #define DOLPHIN_C0_INT GENMASK(4, 4) 260 #define DOLPHIN_C1_INT GENMASK(0, 0) 261 #define DOLPHIN_C0_RESET GENMASK(5, 5) 262 #define DOLPHIN_C1_RESET GENMASK(1, 1) 263 #define DOLPHIN_WAKE (DOLPHIN_C0_INT | DOLPHIN_C1_INT) 264 265 enum { 266 CS8409_BULLSEYE, 267 CS8409_WARLOCK, 268 CS8409_WARLOCK_MLK, 269 CS8409_WARLOCK_MLK_DUAL_MIC, 270 CS8409_CYBORG, 271 CS8409_FIXUPS, 272 CS8409_DOLPHIN, 273 CS8409_DOLPHIN_FIXUPS, 274 CS8409_ODIN, 275 CS8409_CDB35L56_FOUR_HD, 276 CS8409_CDB35L56_FOUR_HD_FIXUP, 277 }; 278 279 enum { 280 CS8409_CODEC0, 281 CS8409_CODEC1 282 }; 283 284 enum { 285 CS42L42_VOL_ADC, 286 CS42L42_VOL_DAC, 287 }; 288 289 #define CS42L42_ADC_VOL_OFFSET (CS42L42_VOL_ADC) 290 #define CS42L42_DAC_CH0_VOL_OFFSET (CS42L42_VOL_DAC) 291 #define CS42L42_DAC_CH1_VOL_OFFSET (CS42L42_VOL_DAC + 1) 292 293 struct cs8409_i2c_param { 294 unsigned int addr; 295 unsigned int value; 296 unsigned int delay; 297 }; 298 299 struct cs8409_cir_param { 300 unsigned int nid; 301 unsigned int cir; 302 unsigned int coeff; 303 }; 304 305 struct sub_codec { 306 struct hda_codec *codec; 307 unsigned int addr; 308 unsigned int reset_gpio; 309 unsigned int irq_mask; 310 const struct cs8409_i2c_param *init_seq; 311 unsigned int init_seq_num; 312 313 unsigned int hp_jack_in:1; 314 unsigned int mic_jack_in:1; 315 unsigned int suspended:1; 316 unsigned int paged:1; 317 unsigned int last_page; 318 unsigned int hsbias_hiz; 319 unsigned int full_scale_vol:1; 320 unsigned int no_type_dect:1; 321 322 s8 vol[CS42L42_VOLUMES]; 323 }; 324 325 struct cs8409_spec { 326 struct hda_gen_spec gen; 327 struct hda_codec *codec; 328 329 struct sub_codec *scodecs[CS8409_MAX_CODECS]; 330 unsigned int num_scodecs; 331 332 unsigned int gpio_mask; 333 unsigned int gpio_dir; 334 unsigned int gpio_data; 335 336 int speaker_pdn_gpio; 337 338 struct mutex i2c_mux; 339 unsigned int i2c_clck_enabled; 340 unsigned int dev_addr; 341 struct delayed_work i2c_clk_work; 342 343 unsigned int playback_started:1; 344 unsigned int capture_started:1; 345 unsigned int init_done:1; 346 unsigned int build_ctrl_done:1; 347 unsigned int speaker_muted:1; 348 349 /* verb exec op override */ 350 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags, 351 unsigned int *res); 352 /* unsol_event op override */ 353 void (*unsol_event)(struct hda_codec *codec, unsigned int res); 354 355 /* component binding */ 356 struct component_match *match; 357 struct hda_component_parent comps; 358 }; 359 360 extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer; 361 extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer; 362 363 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo); 364 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl); 365 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl); 366 367 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback; 368 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture; 369 extern const struct hda_quirk cs8409_fixup_tbl[]; 370 extern const struct hda_model_fixup cs8409_models[]; 371 extern const struct hda_fixup cs8409_fixups[]; 372 extern const struct hda_verb cs8409_cs42l42_init_verbs[]; 373 extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[]; 374 extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[]; 375 extern struct sub_codec cs8409_cs42l42_codec; 376 377 extern const struct hda_verb dolphin_init_verbs[]; 378 extern const struct cs8409_cir_param dolphin_hw_cfg[]; 379 extern struct sub_codec dolphin_cs42l42_0; 380 extern struct sub_codec dolphin_cs42l42_1; 381 382 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action); 383 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action); 384 385 extern const struct cs8409_cir_param cs8409_cdb35l56_four_hw_cfg[]; 386 extern const struct hda_verb cs8409_cdb35l56_four_init_verbs[]; 387 void cs8409_cdb35l56_four_autodet_fixup(struct hda_codec *codec, const struct hda_fixup *fix, 388 int action); 389 390 #endif 391