1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cadence QSPI Controller 4 // 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 8 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/jiffies.h> 21 #include <linux/kernel.h> 22 #include <linux/log2.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/sched.h> 29 #include <linux/spi/spi.h> 30 #include <linux/spi/spi-mem.h> 31 #include <linux/timer.h> 32 33 #define CQSPI_NAME "cadence-qspi" 34 #define CQSPI_MAX_CHIPSELECT 4 35 36 static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX); 37 38 /* Quirks */ 39 #define CQSPI_NEEDS_WR_DELAY BIT(0) 40 #define CQSPI_DISABLE_DAC_MODE BIT(1) 41 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 42 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 43 #define CQSPI_SLOW_SRAM BIT(4) 44 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) 45 #define CQSPI_RD_NO_IRQ BIT(6) 46 #define CQSPI_DMA_SET_MASK BIT(7) 47 #define CQSPI_SUPPORT_DEVICE_RESET BIT(8) 48 #define CQSPI_DISABLE_STIG_MODE BIT(9) 49 #define CQSPI_DISABLE_RUNTIME_PM BIT(10) 50 #define CQSPI_NO_INDIRECT_MODE BIT(11) 51 #define CQSPI_HAS_WR_PROTECT BIT(12) 52 53 /* Capabilities */ 54 #define CQSPI_SUPPORTS_OCTAL BIT(0) 55 #define CQSPI_SUPPORTS_QUAD BIT(1) 56 57 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 58 59 enum { 60 CLK_QSPI_REF = 0, 61 CLK_QSPI_APB, 62 CLK_QSPI_AHB, 63 CLK_QSPI_NUM, 64 }; 65 66 struct cqspi_st; 67 68 struct cqspi_flash_pdata { 69 struct cqspi_st *cqspi; 70 u32 clk_rate; 71 u32 read_delay; 72 u32 tshsl_ns; 73 u32 tsd2d_ns; 74 u32 tchsh_ns; 75 u32 tslch_ns; 76 u8 cs; 77 }; 78 79 struct cqspi_st { 80 struct platform_device *pdev; 81 struct spi_controller *host; 82 struct clk_bulk_data clks[CLK_QSPI_NUM]; 83 unsigned int sclk; 84 85 void __iomem *iobase; 86 void __iomem *ahb_base; 87 resource_size_t ahb_size; 88 struct completion transfer_complete; 89 90 struct dma_chan *rx_chan; 91 struct completion rx_dma_complete; 92 dma_addr_t mmap_phys_base; 93 94 int current_cs; 95 unsigned long master_ref_clk_hz; 96 bool is_decoded_cs; 97 u32 fifo_depth; 98 u32 fifo_width; 99 u32 num_chipselect; 100 bool rclk_en; 101 u32 trigger_address; 102 u32 wr_delay; 103 bool use_direct_mode; 104 bool use_direct_mode_wr; 105 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 106 bool use_dma_read; 107 u32 pd_dev_id; 108 bool wr_completion; 109 bool slow_sram; 110 bool apb_ahb_hazard; 111 112 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ 113 bool is_rzn1; /* Flag for Renesas RZ/N1 SoC */ 114 bool disable_stig_mode; 115 refcount_t refcount; 116 refcount_t inflight_ops; 117 118 const struct cqspi_driver_platdata *ddata; 119 }; 120 121 struct cqspi_driver_platdata { 122 u32 hwcaps_mask; 123 u16 quirks; 124 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 125 u_char *rxbuf, loff_t from_addr, size_t n_rx); 126 u32 (*get_dma_status)(struct cqspi_st *cqspi); 127 }; 128 129 /* Operation timeout value */ 130 #define CQSPI_TIMEOUT_MS 500 131 #define CQSPI_READ_TIMEOUT_MS 10 132 #define CQSPI_BUSYWAIT_TIMEOUT_US 500 133 134 /* Runtime_pm autosuspend delay */ 135 #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 136 137 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 138 #define CQSPI_DUMMY_BYTES_MAX 4 139 #define CQSPI_DUMMY_CLKS_MAX 31 140 141 #define CQSPI_STIG_DATA_LEN_MAX 8 142 143 /* Register map */ 144 #define CQSPI_REG_CONFIG 0x00 145 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 146 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 147 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 148 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 149 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 150 #define CQSPI_REG_CONFIG_BAUD_LSB 19 151 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 152 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 153 #define CQSPI_REG_CONFIG_IDLE_LSB 31 154 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 155 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 156 #define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5) 157 #define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6) 158 159 #define CQSPI_REG_RD_INSTR 0x04 160 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 161 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 162 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 163 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 164 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 165 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 166 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 167 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 168 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 169 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 170 171 #define CQSPI_REG_WR_INSTR 0x08 172 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 173 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 174 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 175 176 #define CQSPI_REG_DELAY 0x0C 177 #define CQSPI_REG_DELAY_TSLCH_LSB 0 178 #define CQSPI_REG_DELAY_TCHSH_LSB 8 179 #define CQSPI_REG_DELAY_TSD2D_LSB 16 180 #define CQSPI_REG_DELAY_TSHSL_LSB 24 181 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 182 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 183 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 184 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 185 186 #define CQSPI_REG_READCAPTURE 0x10 187 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 188 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 189 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 190 191 #define CQSPI_REG_SIZE 0x14 192 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 193 #define CQSPI_REG_SIZE_PAGE_LSB 4 194 #define CQSPI_REG_SIZE_BLOCK_LSB 16 195 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 196 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 197 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 198 199 #define CQSPI_REG_SRAMPARTITION 0x18 200 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 201 202 #define CQSPI_REG_DMA 0x20 203 #define CQSPI_REG_DMA_SINGLE_LSB 0 204 #define CQSPI_REG_DMA_BURST_LSB 8 205 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 206 #define CQSPI_REG_DMA_BURST_MASK 0xFF 207 208 #define CQSPI_REG_REMAP 0x24 209 #define CQSPI_REG_MODE_BIT 0x28 210 211 #define CQSPI_REG_SDRAMLEVEL 0x2C 212 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 213 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 214 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 215 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 216 217 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 218 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 219 220 #define CQSPI_REG_IRQSTATUS 0x40 221 #define CQSPI_REG_IRQMASK 0x44 222 223 #define CQSPI_REG_WR_PROT_CTRL 0x58 224 225 #define CQSPI_REG_INDIRECTRD 0x60 226 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 227 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 228 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 229 230 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 231 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 232 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 233 234 #define CQSPI_REG_CMDCTRL 0x90 235 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 236 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 237 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 238 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 239 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 240 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 241 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 242 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 243 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 244 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 245 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 246 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 247 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 248 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 249 250 #define CQSPI_REG_INDIRECTWR 0x70 251 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 252 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 253 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 254 255 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 256 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 257 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 258 259 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 260 261 #define CQSPI_REG_CMDADDRESS 0x94 262 #define CQSPI_REG_CMDREADDATALOWER 0xA0 263 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 264 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 265 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 266 267 #define CQSPI_REG_POLLING_STATUS 0xB0 268 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 269 270 #define CQSPI_REG_OP_EXT_LOWER 0xE0 271 #define CQSPI_REG_OP_EXT_READ_LSB 24 272 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 273 #define CQSPI_REG_OP_EXT_STIG_LSB 0 274 275 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 276 277 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 278 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 279 280 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 281 282 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 283 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 284 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 285 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 286 287 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 288 289 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 290 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 291 292 /* Interrupt status bits */ 293 #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 294 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 295 #define CQSPI_REG_IRQ_IND_COMP BIT(2) 296 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 297 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 298 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 299 #define CQSPI_REG_IRQ_WATERMARK BIT(6) 300 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 301 302 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 303 CQSPI_REG_IRQ_IND_SRAM_FULL | \ 304 CQSPI_REG_IRQ_IND_COMP) 305 306 #define CQSPI_IRQ_MASK_RD_SLOW_SRAM (CQSPI_REG_IRQ_WATERMARK | \ 307 CQSPI_REG_IRQ_IND_COMP) 308 309 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 310 CQSPI_REG_IRQ_WATERMARK | \ 311 CQSPI_REG_IRQ_UNDERFLOW) 312 313 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 314 #define CQSPI_DMA_UNALIGN 0x3 315 316 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 317 318 static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata, 319 void __iomem *reg, const u32 mask, bool clr, 320 bool busywait) 321 { 322 u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC; 323 u32 val; 324 325 if (busywait) { 326 int ret = readl_relaxed_poll_timeout(reg, val, 327 (((clr ? ~val : val) & mask) == mask), 328 0, CQSPI_BUSYWAIT_TIMEOUT_US); 329 330 if (ret != -ETIMEDOUT) 331 return ret; 332 333 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; 334 } 335 336 return readl_relaxed_poll_timeout(reg, val, 337 (((clr ? ~val : val) & mask) == mask), 338 10, timeout_us); 339 } 340 341 static bool cqspi_is_idle(struct cqspi_st *cqspi) 342 { 343 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 344 345 return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB); 346 } 347 348 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 349 { 350 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 351 352 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 353 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 354 } 355 356 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 357 { 358 u32 dma_status; 359 360 dma_status = readl(cqspi->iobase + 361 CQSPI_REG_VERSAL_DMA_DST_I_STS); 362 writel(dma_status, cqspi->iobase + 363 CQSPI_REG_VERSAL_DMA_DST_I_STS); 364 365 return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 366 } 367 368 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 369 { 370 struct cqspi_st *cqspi = dev; 371 const struct cqspi_driver_platdata *ddata = cqspi->ddata; 372 unsigned int irq_status; 373 374 /* Read interrupt status */ 375 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 376 377 /* Clear interrupt */ 378 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 379 380 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) 381 irq_status = ddata->get_dma_status(cqspi); 382 else if (cqspi->slow_sram) 383 irq_status &= CQSPI_IRQ_MASK_RD_SLOW_SRAM | CQSPI_IRQ_MASK_WR; 384 else 385 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 386 387 if (irq_status) 388 complete(&cqspi->transfer_complete); 389 390 return IRQ_HANDLED; 391 } 392 393 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 394 { 395 u32 rdreg = 0; 396 397 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 398 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 399 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 400 401 return rdreg; 402 } 403 404 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 405 { 406 unsigned int dummy_clk; 407 408 if (!op->dummy.nbytes) 409 return 0; 410 411 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 412 if (op->cmd.dtr) 413 dummy_clk /= 2; 414 415 return dummy_clk; 416 } 417 418 static int cqspi_wait_idle(struct cqspi_st *cqspi) 419 { 420 const unsigned int poll_idle_retry = 3; 421 unsigned int count = 0; 422 unsigned long timeout; 423 424 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 425 while (1) { 426 /* 427 * Read few times in succession to ensure the controller 428 * is indeed idle, that is, the bit does not transition 429 * low again. 430 */ 431 if (cqspi_is_idle(cqspi)) 432 count++; 433 else 434 count = 0; 435 436 if (count >= poll_idle_retry) 437 return 0; 438 439 if (time_after(jiffies, timeout)) { 440 /* Timeout, in busy mode. */ 441 dev_err(&cqspi->pdev->dev, 442 "QSPI is still busy after %dms timeout.\n", 443 CQSPI_TIMEOUT_MS); 444 return -ETIMEDOUT; 445 } 446 447 cpu_relax(); 448 } 449 } 450 451 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 452 { 453 void __iomem *reg_base = cqspi->iobase; 454 int ret; 455 456 /* Write the CMDCTRL without start execution. */ 457 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 458 /* Start execute */ 459 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 460 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 461 462 /* Polling for completion. */ 463 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, 464 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true); 465 if (ret) { 466 dev_err(&cqspi->pdev->dev, 467 "Flash command execution timed out.\n"); 468 return ret; 469 } 470 471 /* Polling QSPI idle status. */ 472 return cqspi_wait_idle(cqspi); 473 } 474 475 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 476 const struct spi_mem_op *op, 477 unsigned int shift) 478 { 479 struct cqspi_st *cqspi = f_pdata->cqspi; 480 void __iomem *reg_base = cqspi->iobase; 481 unsigned int reg; 482 u8 ext; 483 484 if (op->cmd.nbytes != 2) 485 return -EINVAL; 486 487 /* Opcode extension is the LSB. */ 488 ext = op->cmd.opcode & 0xff; 489 490 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 491 reg &= ~(0xff << shift); 492 reg |= ext << shift; 493 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 494 495 return 0; 496 } 497 498 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 499 const struct spi_mem_op *op, unsigned int shift) 500 { 501 struct cqspi_st *cqspi = f_pdata->cqspi; 502 void __iomem *reg_base = cqspi->iobase; 503 unsigned int reg; 504 int ret; 505 506 reg = readl(reg_base + CQSPI_REG_CONFIG); 507 508 /* 509 * We enable dual byte opcode here. The callers have to set up the 510 * extension opcode based on which type of operation it is. 511 */ 512 if (op->cmd.dtr) { 513 reg |= CQSPI_REG_CONFIG_DTR_PROTO; 514 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 515 516 /* Set up command opcode extension. */ 517 ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 518 if (ret) 519 return ret; 520 } else { 521 unsigned int mask = CQSPI_REG_CONFIG_DTR_PROTO | CQSPI_REG_CONFIG_DUAL_OPCODE; 522 /* Shortcut if DTR is already disabled. */ 523 if ((reg & mask) == 0) 524 return 0; 525 reg &= ~mask; 526 } 527 528 writel(reg, reg_base + CQSPI_REG_CONFIG); 529 530 return cqspi_wait_idle(cqspi); 531 } 532 533 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 534 const struct spi_mem_op *op) 535 { 536 struct cqspi_st *cqspi = f_pdata->cqspi; 537 void __iomem *reg_base = cqspi->iobase; 538 u8 *rxbuf = op->data.buf.in; 539 u8 opcode; 540 size_t n_rx = op->data.nbytes; 541 unsigned int rdreg; 542 unsigned int reg; 543 unsigned int dummy_clk; 544 size_t read_len; 545 int status; 546 547 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 548 if (status) 549 return status; 550 551 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 552 dev_err(&cqspi->pdev->dev, 553 "Invalid input argument, len %zu rxbuf 0x%p\n", 554 n_rx, rxbuf); 555 return -EINVAL; 556 } 557 558 if (op->cmd.dtr) 559 opcode = op->cmd.opcode >> 8; 560 else 561 opcode = op->cmd.opcode; 562 563 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 564 565 rdreg = cqspi_calc_rdreg(op); 566 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 567 568 dummy_clk = cqspi_calc_dummy(op); 569 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 570 return -EOPNOTSUPP; 571 572 if (dummy_clk) 573 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 574 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 575 576 reg |= BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB); 577 578 /* 0 means 1 byte. */ 579 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 580 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 581 582 /* setup ADDR BIT field */ 583 if (op->addr.nbytes) { 584 reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 585 reg |= ((op->addr.nbytes - 1) & 586 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 587 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 588 589 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 590 } 591 592 status = cqspi_exec_flash_cmd(cqspi, reg); 593 if (status) 594 return status; 595 596 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 597 598 /* Put the read value into rx_buf */ 599 read_len = (n_rx > 4) ? 4 : n_rx; 600 memcpy(rxbuf, ®, read_len); 601 rxbuf += read_len; 602 603 if (n_rx > 4) { 604 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 605 606 read_len = n_rx - read_len; 607 memcpy(rxbuf, ®, read_len); 608 } 609 610 /* Reset CMD_CTRL Reg once command read completes */ 611 writel(0, reg_base + CQSPI_REG_CMDCTRL); 612 613 return 0; 614 } 615 616 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 617 const struct spi_mem_op *op) 618 { 619 struct cqspi_st *cqspi = f_pdata->cqspi; 620 void __iomem *reg_base = cqspi->iobase; 621 u8 opcode; 622 const u8 *txbuf = op->data.buf.out; 623 size_t n_tx = op->data.nbytes; 624 unsigned int reg; 625 unsigned int data; 626 size_t write_len; 627 int ret; 628 629 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 630 if (ret) 631 return ret; 632 633 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 634 dev_err(&cqspi->pdev->dev, 635 "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 636 n_tx, txbuf); 637 return -EINVAL; 638 } 639 640 reg = cqspi_calc_rdreg(op); 641 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 642 643 if (op->cmd.dtr) 644 opcode = op->cmd.opcode >> 8; 645 else 646 opcode = op->cmd.opcode; 647 648 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 649 650 if (op->addr.nbytes) { 651 reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 652 reg |= ((op->addr.nbytes - 1) & 653 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 654 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 655 656 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 657 } 658 659 if (n_tx) { 660 reg |= BIT(CQSPI_REG_CMDCTRL_WR_EN_LSB); 661 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 662 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 663 data = 0; 664 write_len = (n_tx > 4) ? 4 : n_tx; 665 memcpy(&data, txbuf, write_len); 666 txbuf += write_len; 667 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 668 669 if (n_tx > 4) { 670 data = 0; 671 write_len = n_tx - 4; 672 memcpy(&data, txbuf, write_len); 673 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 674 } 675 } 676 677 ret = cqspi_exec_flash_cmd(cqspi, reg); 678 679 /* Reset CMD_CTRL Reg once command write completes */ 680 writel(0, reg_base + CQSPI_REG_CMDCTRL); 681 682 return ret; 683 } 684 685 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 686 const struct spi_mem_op *op) 687 { 688 struct cqspi_st *cqspi = f_pdata->cqspi; 689 void __iomem *reg_base = cqspi->iobase; 690 unsigned int dummy_clk = 0; 691 unsigned int reg; 692 int ret; 693 u8 opcode; 694 695 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 696 if (ret) 697 return ret; 698 699 if (op->cmd.dtr) 700 opcode = op->cmd.opcode >> 8; 701 else 702 opcode = op->cmd.opcode; 703 704 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 705 reg |= cqspi_calc_rdreg(op); 706 707 /* Setup dummy clock cycles */ 708 dummy_clk = cqspi_calc_dummy(op); 709 710 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 711 return -EOPNOTSUPP; 712 713 if (dummy_clk) 714 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 715 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 716 717 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 718 719 /* Set address width */ 720 reg = readl(reg_base + CQSPI_REG_SIZE); 721 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 722 reg |= (op->addr.nbytes - 1); 723 writel(reg, reg_base + CQSPI_REG_SIZE); 724 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ 725 return 0; 726 } 727 728 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 729 u8 *rxbuf, loff_t from_addr, 730 const size_t n_rx) 731 { 732 struct cqspi_st *cqspi = f_pdata->cqspi; 733 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); 734 struct device *dev = &cqspi->pdev->dev; 735 void __iomem *reg_base = cqspi->iobase; 736 void __iomem *ahb_base = cqspi->ahb_base; 737 unsigned int remaining = n_rx; 738 unsigned int mod_bytes = n_rx % 4; 739 unsigned int bytes_to_read = 0; 740 u8 *rxbuf_end = rxbuf + n_rx; 741 int ret = 0; 742 743 if (!refcount_read(&cqspi->refcount)) 744 return -ENODEV; 745 746 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 747 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 748 749 /* Clear all interrupts. */ 750 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 751 752 /* 753 * On SoCFPGA platform reading the SRAM is slow due to 754 * hardware limitation and causing read interrupt storm to CPU, 755 * so enabling only watermark interrupt to disable all read 756 * interrupts later as we want to run "bytes to read" loop with 757 * all the read interrupts disabled for max performance. 758 */ 759 760 if (use_irq && cqspi->slow_sram) 761 writel(CQSPI_IRQ_MASK_RD_SLOW_SRAM, reg_base + CQSPI_REG_IRQMASK); 762 else if (use_irq) 763 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 764 else 765 writel(0, reg_base + CQSPI_REG_IRQMASK); 766 767 reinit_completion(&cqspi->transfer_complete); 768 writel(CQSPI_REG_INDIRECTRD_START_MASK, 769 reg_base + CQSPI_REG_INDIRECTRD); 770 readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ 771 772 while (remaining > 0) { 773 ret = 0; 774 if (use_irq && 775 !wait_for_completion_timeout(&cqspi->transfer_complete, 776 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 777 ret = -ETIMEDOUT; 778 779 /* 780 * Prevent lost interrupt and race condition by reinitializing early. 781 * A spurious wakeup and another wait cycle can occur here, 782 * which is preferable to waiting until timeout if interrupt is lost. 783 */ 784 if (use_irq) 785 reinit_completion(&cqspi->transfer_complete); 786 787 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 788 789 if (ret && bytes_to_read == 0) { 790 dev_err(dev, "Indirect read timeout, no bytes\n"); 791 goto failrd; 792 } 793 794 while (bytes_to_read != 0) { 795 unsigned int word_remain = round_down(remaining, 4); 796 797 bytes_to_read *= cqspi->fifo_width; 798 bytes_to_read = bytes_to_read > remaining ? 799 remaining : bytes_to_read; 800 bytes_to_read = round_down(bytes_to_read, 4); 801 /* Read 4 byte word chunks then single bytes */ 802 if (bytes_to_read) { 803 ioread32_rep(ahb_base, rxbuf, 804 (bytes_to_read / 4)); 805 } else if (!word_remain && mod_bytes) { 806 unsigned int temp = ioread32(ahb_base); 807 808 bytes_to_read = mod_bytes; 809 memcpy(rxbuf, &temp, min((unsigned int) 810 (rxbuf_end - rxbuf), 811 bytes_to_read)); 812 } 813 rxbuf += bytes_to_read; 814 remaining -= bytes_to_read; 815 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 816 } 817 } 818 819 /* Check indirect done status */ 820 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, 821 CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true); 822 if (ret) { 823 dev_err(dev, "Indirect read completion error (%i)\n", ret); 824 goto failrd; 825 } 826 827 /* Disable interrupt */ 828 writel(0, reg_base + CQSPI_REG_IRQMASK); 829 830 /* Clear indirect completion status */ 831 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 832 833 return 0; 834 835 failrd: 836 /* Disable interrupt */ 837 writel(0, reg_base + CQSPI_REG_IRQMASK); 838 839 /* Cancel the indirect read */ 840 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 841 reg_base + CQSPI_REG_INDIRECTRD); 842 return ret; 843 } 844 845 static void cqspi_device_reset(struct cqspi_st *cqspi) 846 { 847 u32 reg; 848 849 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 850 reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK; 851 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 852 /* 853 * NOTE: Delay timing implementation is derived from 854 * spi_nor_hw_reset() 855 */ 856 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 857 usleep_range(1, 5); 858 writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 859 usleep_range(100, 150); 860 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 861 usleep_range(1000, 1200); 862 } 863 864 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 865 { 866 void __iomem *reg_base = cqspi->iobase; 867 unsigned int reg; 868 869 reg = readl(reg_base + CQSPI_REG_CONFIG); 870 871 if (enable) 872 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 873 else 874 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 875 876 writel(reg, reg_base + CQSPI_REG_CONFIG); 877 } 878 879 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 880 u_char *rxbuf, loff_t from_addr, 881 size_t n_rx) 882 { 883 struct cqspi_st *cqspi = f_pdata->cqspi; 884 struct device *dev = &cqspi->pdev->dev; 885 void __iomem *reg_base = cqspi->iobase; 886 u32 reg, bytes_to_dma; 887 loff_t addr = from_addr; 888 void *buf = rxbuf; 889 dma_addr_t dma_addr; 890 u8 bytes_rem; 891 int ret = 0; 892 893 bytes_rem = n_rx % 4; 894 bytes_to_dma = (n_rx - bytes_rem); 895 896 if (!bytes_to_dma) 897 goto nondmard; 898 899 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 900 if (ret) 901 return ret; 902 903 cqspi_controller_enable(cqspi, 0); 904 905 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 906 reg |= CQSPI_REG_CONFIG_DMA_MASK; 907 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 908 909 cqspi_controller_enable(cqspi, 1); 910 911 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 912 if (dma_mapping_error(dev, dma_addr)) { 913 dev_err(dev, "dma mapping failed\n"); 914 return -ENOMEM; 915 } 916 917 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 918 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 919 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 920 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 921 922 /* Clear all interrupts. */ 923 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 924 925 /* Enable DMA done interrupt */ 926 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 927 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 928 929 /* Default DMA periph configuration */ 930 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 931 932 /* Configure DMA Dst address */ 933 writel(lower_32_bits(dma_addr), 934 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 935 writel(upper_32_bits(dma_addr), 936 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 937 938 /* Configure DMA Src address */ 939 writel(cqspi->trigger_address, reg_base + 940 CQSPI_REG_VERSAL_DMA_SRC_ADDR); 941 942 /* Set DMA destination size */ 943 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 944 945 /* Set DMA destination control */ 946 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 947 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 948 949 writel(CQSPI_REG_INDIRECTRD_START_MASK, 950 reg_base + CQSPI_REG_INDIRECTRD); 951 952 reinit_completion(&cqspi->transfer_complete); 953 954 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 955 msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { 956 ret = -ETIMEDOUT; 957 goto failrd; 958 } 959 960 /* Disable DMA interrupt */ 961 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 962 963 /* Clear indirect completion status */ 964 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 965 cqspi->iobase + CQSPI_REG_INDIRECTRD); 966 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 967 968 cqspi_controller_enable(cqspi, 0); 969 970 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 971 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 972 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 973 974 cqspi_controller_enable(cqspi, 1); 975 976 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 977 PM_OSPI_MUX_SEL_LINEAR); 978 if (ret) 979 return ret; 980 981 nondmard: 982 if (bytes_rem) { 983 addr += bytes_to_dma; 984 buf += bytes_to_dma; 985 ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 986 bytes_rem); 987 if (ret) 988 return ret; 989 } 990 991 return 0; 992 993 failrd: 994 /* Disable DMA interrupt */ 995 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 996 997 /* Cancel the indirect read */ 998 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 999 reg_base + CQSPI_REG_INDIRECTRD); 1000 1001 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 1002 1003 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1004 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 1005 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1006 1007 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 1008 1009 return ret; 1010 } 1011 1012 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 1013 const struct spi_mem_op *op) 1014 { 1015 unsigned int reg; 1016 int ret; 1017 struct cqspi_st *cqspi = f_pdata->cqspi; 1018 void __iomem *reg_base = cqspi->iobase; 1019 u8 opcode; 1020 1021 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 1022 if (ret) 1023 return ret; 1024 1025 if (op->cmd.dtr) 1026 opcode = op->cmd.opcode >> 8; 1027 else 1028 opcode = op->cmd.opcode; 1029 1030 /* Set opcode. */ 1031 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 1032 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 1033 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 1034 writel(reg, reg_base + CQSPI_REG_WR_INSTR); 1035 reg = cqspi_calc_rdreg(op); 1036 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 1037 1038 /* 1039 * SPI NAND flashes require the address of the status register to be 1040 * passed in the Read SR command. Also, some SPI NOR flashes like the 1041 * cypress Semper flash expect a 4-byte dummy address in the Read SR 1042 * command in DTR mode. 1043 * 1044 * But this controller does not support address phase in the Read SR 1045 * command when doing auto-HW polling. So, disable write completion 1046 * polling on the controller's side. spinand and spi-nor will take 1047 * care of polling the status register. 1048 */ 1049 if (cqspi->wr_completion) { 1050 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 1051 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 1052 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 1053 /* 1054 * DAC mode require auto polling as flash needs to be polled 1055 * for write completion in case of bubble in SPI transaction 1056 * due to slow CPU/DMA master. 1057 */ 1058 cqspi->use_direct_mode_wr = false; 1059 } 1060 1061 reg = readl(reg_base + CQSPI_REG_SIZE); 1062 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 1063 reg |= (op->addr.nbytes - 1); 1064 writel(reg, reg_base + CQSPI_REG_SIZE); 1065 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ 1066 return 0; 1067 } 1068 1069 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 1070 loff_t to_addr, const u8 *txbuf, 1071 const size_t n_tx) 1072 { 1073 struct cqspi_st *cqspi = f_pdata->cqspi; 1074 struct device *dev = &cqspi->pdev->dev; 1075 void __iomem *reg_base = cqspi->iobase; 1076 unsigned int remaining = n_tx; 1077 unsigned int write_bytes; 1078 int ret; 1079 1080 if (!refcount_read(&cqspi->refcount)) 1081 return -ENODEV; 1082 1083 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 1084 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 1085 1086 /* Clear all interrupts. */ 1087 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 1088 1089 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 1090 1091 reinit_completion(&cqspi->transfer_complete); 1092 writel(CQSPI_REG_INDIRECTWR_START_MASK, 1093 reg_base + CQSPI_REG_INDIRECTWR); 1094 readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ 1095 1096 /* 1097 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 1098 * Controller programming sequence, couple of cycles of 1099 * QSPI_REF_CLK delay is required for the above bit to 1100 * be internally synchronized by the QSPI module. Provide 5 1101 * cycles of delay. 1102 */ 1103 if (cqspi->wr_delay) 1104 ndelay(cqspi->wr_delay); 1105 1106 /* 1107 * If a hazard exists between the APB and AHB interfaces, perform a 1108 * dummy readback from the controller to ensure synchronization. 1109 */ 1110 if (cqspi->apb_ahb_hazard) 1111 readl(reg_base + CQSPI_REG_INDIRECTWR); 1112 1113 while (remaining > 0) { 1114 size_t write_words, mod_bytes; 1115 1116 write_bytes = remaining; 1117 write_words = write_bytes / 4; 1118 mod_bytes = write_bytes % 4; 1119 /* Write 4 bytes at a time then single bytes. */ 1120 if (write_words) { 1121 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 1122 txbuf += (write_words * 4); 1123 } 1124 if (mod_bytes) { 1125 unsigned int temp = 0xFFFFFFFF; 1126 1127 memcpy(&temp, txbuf, mod_bytes); 1128 iowrite32(temp, cqspi->ahb_base); 1129 txbuf += mod_bytes; 1130 } 1131 1132 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 1133 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 1134 dev_err(dev, "Indirect write timeout\n"); 1135 ret = -ETIMEDOUT; 1136 goto failwr; 1137 } 1138 1139 remaining -= write_bytes; 1140 1141 if (remaining > 0) 1142 reinit_completion(&cqspi->transfer_complete); 1143 } 1144 1145 /* Check indirect done status */ 1146 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, 1147 CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false); 1148 if (ret) { 1149 dev_err(dev, "Indirect write completion error (%i)\n", ret); 1150 goto failwr; 1151 } 1152 1153 /* Disable interrupt. */ 1154 writel(0, reg_base + CQSPI_REG_IRQMASK); 1155 1156 /* Clear indirect completion status */ 1157 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 1158 1159 cqspi_wait_idle(cqspi); 1160 1161 return 0; 1162 1163 failwr: 1164 /* Disable interrupt. */ 1165 writel(0, reg_base + CQSPI_REG_IRQMASK); 1166 1167 /* Cancel the indirect write */ 1168 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1169 reg_base + CQSPI_REG_INDIRECTWR); 1170 return ret; 1171 } 1172 1173 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 1174 { 1175 struct cqspi_st *cqspi = f_pdata->cqspi; 1176 void __iomem *reg_base = cqspi->iobase; 1177 unsigned int chip_select = f_pdata->cs; 1178 unsigned int reg; 1179 1180 reg = readl(reg_base + CQSPI_REG_CONFIG); 1181 if (cqspi->is_decoded_cs) { 1182 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 1183 } else { 1184 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 1185 1186 /* Convert CS if without decoder. 1187 * CS0 to 4b'1110 1188 * CS1 to 4b'1101 1189 * CS2 to 4b'1011 1190 * CS3 to 4b'0111 1191 */ 1192 chip_select = 0xF & ~BIT(chip_select); 1193 } 1194 1195 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 1196 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 1197 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 1198 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 1199 writel(reg, reg_base + CQSPI_REG_CONFIG); 1200 } 1201 1202 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 1203 const unsigned int ns_val) 1204 { 1205 unsigned int ticks; 1206 1207 ticks = ref_clk_hz / 1000; /* kHz */ 1208 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 1209 1210 return ticks; 1211 } 1212 1213 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 1214 { 1215 struct cqspi_st *cqspi = f_pdata->cqspi; 1216 void __iomem *iobase = cqspi->iobase; 1217 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1218 unsigned int tshsl, tchsh, tslch, tsd2d; 1219 unsigned int reg; 1220 unsigned int tsclk; 1221 1222 /* calculate the number of ref ticks for one sclk tick */ 1223 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 1224 1225 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 1226 /* this particular value must be at least one sclk */ 1227 if (tshsl < tsclk) 1228 tshsl = tsclk; 1229 1230 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 1231 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 1232 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 1233 1234 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 1235 << CQSPI_REG_DELAY_TSHSL_LSB; 1236 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 1237 << CQSPI_REG_DELAY_TCHSH_LSB; 1238 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 1239 << CQSPI_REG_DELAY_TSLCH_LSB; 1240 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 1241 << CQSPI_REG_DELAY_TSD2D_LSB; 1242 writel(reg, iobase + CQSPI_REG_DELAY); 1243 } 1244 1245 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 1246 { 1247 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1248 void __iomem *reg_base = cqspi->iobase; 1249 u32 reg, div; 1250 1251 /* Recalculate the baudrate divisor based on QSPI specification. */ 1252 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 1253 1254 /* Maximum baud divisor */ 1255 if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1256 div = CQSPI_REG_CONFIG_BAUD_MASK; 1257 dev_warn(&cqspi->pdev->dev, 1258 "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1259 cqspi->sclk, ref_clk_hz/((div+1)*2)); 1260 } 1261 1262 reg = readl(reg_base + CQSPI_REG_CONFIG); 1263 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 1264 reg |= div << CQSPI_REG_CONFIG_BAUD_LSB; 1265 writel(reg, reg_base + CQSPI_REG_CONFIG); 1266 } 1267 1268 static void cqspi_readdata_capture(struct cqspi_st *cqspi, 1269 const bool bypass, 1270 const unsigned int delay) 1271 { 1272 void __iomem *reg_base = cqspi->iobase; 1273 unsigned int reg; 1274 1275 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1276 1277 if (bypass) 1278 reg |= BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); 1279 else 1280 reg &= ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); 1281 1282 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1283 << CQSPI_REG_READCAPTURE_DELAY_LSB); 1284 1285 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 1286 << CQSPI_REG_READCAPTURE_DELAY_LSB; 1287 1288 writel(reg, reg_base + CQSPI_REG_READCAPTURE); 1289 } 1290 1291 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 1292 unsigned long sclk) 1293 { 1294 struct cqspi_st *cqspi = f_pdata->cqspi; 1295 int switch_cs = (cqspi->current_cs != f_pdata->cs); 1296 int switch_ck = (cqspi->sclk != sclk); 1297 1298 if (switch_cs || switch_ck) 1299 cqspi_controller_enable(cqspi, 0); 1300 1301 /* Switch chip select. */ 1302 if (switch_cs) { 1303 cqspi->current_cs = f_pdata->cs; 1304 cqspi_chipselect(f_pdata); 1305 } 1306 1307 /* Setup baudrate divisor and delays */ 1308 if (switch_ck) { 1309 cqspi->sclk = sclk; 1310 cqspi_config_baudrate_div(cqspi); 1311 cqspi_delay(f_pdata); 1312 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 1313 f_pdata->read_delay); 1314 } 1315 1316 if (switch_cs || switch_ck) 1317 cqspi_controller_enable(cqspi, 1); 1318 } 1319 1320 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 1321 const struct spi_mem_op *op) 1322 { 1323 struct cqspi_st *cqspi = f_pdata->cqspi; 1324 loff_t to = op->addr.val; 1325 size_t len = op->data.nbytes; 1326 const u_char *buf = op->data.buf.out; 1327 int ret; 1328 1329 ret = cqspi_write_setup(f_pdata, op); 1330 if (ret) 1331 return ret; 1332 1333 /* 1334 * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1335 * address (all 0s) with the read status register command in DTR mode. 1336 * But this controller does not support sending dummy address bytes to 1337 * the flash when it is polling the write completion register in DTR 1338 * mode. So, we can not use direct mode when in DTR mode for writing 1339 * data. 1340 */ 1341 if ((!op->cmd.dtr && cqspi->use_direct_mode && 1342 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) || 1343 (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1344 memcpy_toio(cqspi->ahb_base + to, buf, len); 1345 return cqspi_wait_idle(cqspi); 1346 } 1347 1348 return cqspi_indirect_write_execute(f_pdata, to, buf, len); 1349 } 1350 1351 static void cqspi_rx_dma_callback(void *param) 1352 { 1353 struct cqspi_st *cqspi = param; 1354 1355 complete(&cqspi->rx_dma_complete); 1356 } 1357 1358 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 1359 u_char *buf, loff_t from, size_t len) 1360 { 1361 struct cqspi_st *cqspi = f_pdata->cqspi; 1362 struct device *dev = &cqspi->pdev->dev; 1363 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 1364 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 1365 int ret = 0; 1366 struct dma_async_tx_descriptor *tx; 1367 dma_cookie_t cookie; 1368 dma_addr_t dma_dst; 1369 struct device *ddev; 1370 1371 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 1372 memcpy_fromio(buf, cqspi->ahb_base + from, len); 1373 return 0; 1374 } 1375 1376 ddev = cqspi->rx_chan->device->dev; 1377 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 1378 if (dma_mapping_error(ddev, dma_dst)) { 1379 dev_err(dev, "dma mapping failed\n"); 1380 return -ENOMEM; 1381 } 1382 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 1383 len, flags); 1384 if (!tx) { 1385 dev_err(dev, "device_prep_dma_memcpy error\n"); 1386 ret = -EIO; 1387 goto err_unmap; 1388 } 1389 1390 tx->callback = cqspi_rx_dma_callback; 1391 tx->callback_param = cqspi; 1392 cookie = tx->tx_submit(tx); 1393 reinit_completion(&cqspi->rx_dma_complete); 1394 1395 ret = dma_submit_error(cookie); 1396 if (ret) { 1397 dev_err(dev, "dma_submit_error %d\n", cookie); 1398 ret = -EIO; 1399 goto err_unmap; 1400 } 1401 1402 dma_async_issue_pending(cqspi->rx_chan); 1403 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 1404 msecs_to_jiffies(max_t(size_t, len, 500)))) { 1405 dmaengine_terminate_sync(cqspi->rx_chan); 1406 dev_err(dev, "DMA wait_for_completion_timeout\n"); 1407 ret = -ETIMEDOUT; 1408 goto err_unmap; 1409 } 1410 1411 err_unmap: 1412 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 1413 1414 return ret; 1415 } 1416 1417 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 1418 const struct spi_mem_op *op) 1419 { 1420 struct cqspi_st *cqspi = f_pdata->cqspi; 1421 const struct cqspi_driver_platdata *ddata = cqspi->ddata; 1422 loff_t from = op->addr.val; 1423 size_t len = op->data.nbytes; 1424 u_char *buf = op->data.buf.in; 1425 u64 dma_align = (u64)(uintptr_t)buf; 1426 int ret; 1427 1428 ret = cqspi_read_setup(f_pdata, op); 1429 if (ret) 1430 return ret; 1431 1432 if ((cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) || 1433 (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) 1434 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1435 1436 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 1437 virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 1438 return ddata->indirect_read_dma(f_pdata, buf, from, len); 1439 1440 return cqspi_indirect_read_execute(f_pdata, buf, from, len); 1441 } 1442 1443 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 1444 { 1445 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1446 struct cqspi_flash_pdata *f_pdata; 1447 1448 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; 1449 cqspi_configure(f_pdata, op->max_freq); 1450 1451 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1452 /* 1453 * Performing reads in DAC mode forces to read minimum 4 bytes 1454 * which is unsupported on some flash devices during register 1455 * reads, prefer STIG mode for such small reads. 1456 */ 1457 if (!op->addr.nbytes || 1458 (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && 1459 !cqspi->disable_stig_mode)) 1460 return cqspi_command_read(f_pdata, op); 1461 1462 return cqspi_read(f_pdata, op); 1463 } 1464 1465 if (!op->addr.nbytes || !op->data.buf.out) 1466 return cqspi_command_write(f_pdata, op); 1467 1468 return cqspi_write(f_pdata, op); 1469 } 1470 1471 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 1472 { 1473 int ret; 1474 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1475 struct device *dev = &cqspi->pdev->dev; 1476 const struct cqspi_driver_platdata *ddata = of_device_get_match_data(dev); 1477 1478 if (refcount_read(&cqspi->inflight_ops) == 0) 1479 return -ENODEV; 1480 1481 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 1482 ret = pm_runtime_resume_and_get(dev); 1483 if (ret) { 1484 dev_err(&mem->spi->dev, "resume failed with %d\n", ret); 1485 return ret; 1486 } 1487 } 1488 1489 if (!refcount_read(&cqspi->refcount)) 1490 return -EBUSY; 1491 1492 refcount_inc(&cqspi->inflight_ops); 1493 1494 if (!refcount_read(&cqspi->refcount)) { 1495 if (refcount_read(&cqspi->inflight_ops)) 1496 refcount_dec(&cqspi->inflight_ops); 1497 return -EBUSY; 1498 } 1499 1500 ret = cqspi_mem_process(mem, op); 1501 1502 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 1503 pm_runtime_put_autosuspend(dev); 1504 1505 if (ret) 1506 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 1507 1508 if (refcount_read(&cqspi->inflight_ops) > 1) 1509 refcount_dec(&cqspi->inflight_ops); 1510 1511 return ret; 1512 } 1513 1514 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1515 const struct spi_mem_op *op) 1516 { 1517 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1518 bool all_true, all_false; 1519 1520 /* 1521 * op->dummy.dtr is required for converting nbytes into ncycles. 1522 * Also, don't check the dtr field of the op phase having zero nbytes. 1523 */ 1524 all_true = op->cmd.dtr && 1525 (!op->addr.nbytes || op->addr.dtr) && 1526 (!op->dummy.nbytes || op->dummy.dtr) && 1527 (!op->data.nbytes || op->data.dtr); 1528 1529 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1530 !op->data.dtr; 1531 1532 if (all_true) { 1533 /* Right now we only support 8-8-8 DTR mode. */ 1534 if (op->cmd.nbytes && op->cmd.buswidth != 8) 1535 return false; 1536 if (op->addr.nbytes && op->addr.buswidth != 8) 1537 return false; 1538 if (op->data.nbytes && op->data.buswidth != 8) 1539 return false; 1540 1541 /* A single opcode is supported, it will be repeated */ 1542 if ((op->cmd.opcode >> 8) != (op->cmd.opcode & 0xFF)) 1543 return false; 1544 1545 if (cqspi->is_rzn1) 1546 return false; 1547 } else if (!all_false) { 1548 /* Mixed DTR modes are not supported. */ 1549 return false; 1550 } 1551 1552 return spi_mem_default_supports_op(mem, op); 1553 } 1554 1555 static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 1556 struct cqspi_flash_pdata *f_pdata, 1557 struct device_node *np) 1558 { 1559 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 1560 dev_err(&pdev->dev, "couldn't determine read-delay\n"); 1561 return -ENXIO; 1562 } 1563 1564 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 1565 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 1566 return -ENXIO; 1567 } 1568 1569 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 1570 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 1571 return -ENXIO; 1572 } 1573 1574 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 1575 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 1576 return -ENXIO; 1577 } 1578 1579 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 1580 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 1581 return -ENXIO; 1582 } 1583 1584 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 1585 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 1586 return -ENXIO; 1587 } 1588 1589 return 0; 1590 } 1591 1592 static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 1593 { 1594 struct device *dev = &cqspi->pdev->dev; 1595 struct device_node *np = dev->of_node; 1596 u32 id[2]; 1597 1598 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1599 1600 if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1601 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1602 /* Zero signals FIFO depth should be runtime detected. */ 1603 cqspi->fifo_depth = 0; 1604 } 1605 1606 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) 1607 cqspi->fifo_width = 4; 1608 1609 if (of_property_read_u32(np, "cdns,trigger-address", 1610 &cqspi->trigger_address)) { 1611 dev_err(dev, "couldn't determine trigger-address\n"); 1612 return -ENXIO; 1613 } 1614 } 1615 1616 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1617 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1618 1619 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 1620 1621 if (!of_property_read_u32_array(np, "power-domains", id, 1622 ARRAY_SIZE(id))) 1623 cqspi->pd_dev_id = id[1]; 1624 1625 return 0; 1626 } 1627 1628 static void cqspi_controller_init(struct cqspi_st *cqspi) 1629 { 1630 u32 reg; 1631 1632 /* Configure the remap address register, no remap */ 1633 writel(0, cqspi->iobase + CQSPI_REG_REMAP); 1634 1635 /* Disable all interrupts. */ 1636 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1637 1638 if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1639 /* Configure the SRAM split to 1:1 . */ 1640 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1641 /* Load indirect trigger address. */ 1642 writel(cqspi->trigger_address, 1643 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1644 1645 /* Program read watermark -- 1/2 of the FIFO. */ 1646 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1647 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1648 /* Program write watermark -- 1/8 of the FIFO. */ 1649 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1650 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1651 } 1652 1653 /* Disable write protection at controller level */ 1654 if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT) 1655 writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL); 1656 1657 /* Disable direct access controller */ 1658 if (!cqspi->use_direct_mode) { 1659 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1660 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 1661 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1662 } 1663 1664 /* Enable DMA interface */ 1665 if (cqspi->use_dma_read) { 1666 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1667 reg |= CQSPI_REG_CONFIG_DMA_MASK; 1668 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1669 } 1670 } 1671 1672 static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi) 1673 { 1674 struct device *dev = &cqspi->pdev->dev; 1675 u32 reg, fifo_depth; 1676 1677 if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE) 1678 return; 1679 1680 /* 1681 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N 1682 * the FIFO depth. 1683 */ 1684 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1685 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1686 fifo_depth = reg + 1; 1687 1688 /* FIFO depth of zero means no value from devicetree was provided. */ 1689 if (cqspi->fifo_depth == 0) { 1690 cqspi->fifo_depth = fifo_depth; 1691 dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth); 1692 } else if (fifo_depth != cqspi->fifo_depth) { 1693 dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n", 1694 fifo_depth, cqspi->fifo_depth); 1695 } 1696 } 1697 1698 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 1699 { 1700 dma_cap_mask_t mask; 1701 1702 dma_cap_zero(mask); 1703 dma_cap_set(DMA_MEMCPY, mask); 1704 1705 cqspi->rx_chan = dma_request_chan_by_mask(&mask); 1706 if (IS_ERR(cqspi->rx_chan)) { 1707 int ret = PTR_ERR(cqspi->rx_chan); 1708 1709 cqspi->rx_chan = NULL; 1710 if (ret == -ENODEV) { 1711 /* DMA support is not mandatory */ 1712 dev_info(&cqspi->pdev->dev, "No Rx DMA available\n"); 1713 return 0; 1714 } 1715 1716 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 1717 } 1718 init_completion(&cqspi->rx_dma_complete); 1719 1720 return 0; 1721 } 1722 1723 static const char *cqspi_get_name(struct spi_mem *mem) 1724 { 1725 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1726 struct device *dev = &cqspi->pdev->dev; 1727 1728 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 1729 spi_get_chipselect(mem->spi, 0)); 1730 } 1731 1732 static const struct spi_controller_mem_ops cqspi_mem_ops = { 1733 .exec_op = cqspi_exec_mem_op, 1734 .get_name = cqspi_get_name, 1735 .supports_op = cqspi_supports_mem_op, 1736 }; 1737 1738 static const struct spi_controller_mem_caps cqspi_mem_caps = { 1739 .dtr = true, 1740 .per_op_freq = true, 1741 }; 1742 1743 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1744 { 1745 struct platform_device *pdev = cqspi->pdev; 1746 struct device *dev = &pdev->dev; 1747 struct cqspi_flash_pdata *f_pdata; 1748 int ret, cs, max_cs = -1; 1749 1750 /* Get flash device data */ 1751 for_each_available_child_of_node_scoped(dev->of_node, np) { 1752 ret = of_property_read_u32(np, "reg", &cs); 1753 if (ret) { 1754 dev_err(dev, "Couldn't determine chip select.\n"); 1755 return ret; 1756 } 1757 1758 if (cs >= cqspi->num_chipselect) { 1759 dev_err(dev, "Chip select %d out of range.\n", cs); 1760 return -EINVAL; 1761 } 1762 1763 max_cs = max_t(int, cs, max_cs); 1764 1765 f_pdata = &cqspi->f_pdata[cs]; 1766 f_pdata->cqspi = cqspi; 1767 f_pdata->cs = cs; 1768 1769 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1770 if (ret) 1771 return ret; 1772 } 1773 1774 if (max_cs < 0) { 1775 dev_err(dev, "No flash device declared\n"); 1776 return -ENODEV; 1777 } 1778 1779 cqspi->num_chipselect = max_cs + 1; 1780 return 0; 1781 } 1782 1783 static int cqspi_probe(struct platform_device *pdev) 1784 { 1785 const struct cqspi_driver_platdata *ddata; 1786 struct reset_control *rstc, *rstc_ocp, *rstc_ref; 1787 struct device *dev = &pdev->dev; 1788 struct spi_controller *host; 1789 struct resource *res_ahb; 1790 struct cqspi_st *cqspi; 1791 int ret, irq; 1792 1793 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); 1794 if (!host) 1795 return -ENOMEM; 1796 1797 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 1798 host->mem_ops = &cqspi_mem_ops; 1799 host->mem_caps = &cqspi_mem_caps; 1800 1801 cqspi = spi_controller_get_devdata(host); 1802 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) 1803 cqspi->is_jh7110 = true; 1804 if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi")) 1805 cqspi->is_rzn1 = true; 1806 1807 cqspi->pdev = pdev; 1808 cqspi->host = host; 1809 cqspi->ddata = ddata = of_device_get_match_data(dev); 1810 platform_set_drvdata(pdev, cqspi); 1811 1812 /* Obtain configuration from OF. */ 1813 ret = cqspi_of_get_pdata(cqspi); 1814 if (ret) { 1815 dev_err(dev, "Cannot get mandatory OF data.\n"); 1816 return -ENODEV; 1817 } 1818 1819 ret = cqspi_setup_flash(cqspi); 1820 if (ret) { 1821 dev_err(dev, "failed to setup flash parameters %d\n", ret); 1822 return ret; 1823 } 1824 1825 /* Obtain QSPI clocks. */ 1826 ret = devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); 1827 if (ret) 1828 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1829 1830 if (!cqspi->clks[CLK_QSPI_REF].clk) { 1831 dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); 1832 return -ENODEV; 1833 } 1834 1835 /* Obtain and remap controller address. */ 1836 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 1837 if (IS_ERR(cqspi->iobase)) { 1838 dev_err(dev, "Cannot remap controller address.\n"); 1839 ret = PTR_ERR(cqspi->iobase); 1840 return ret; 1841 } 1842 1843 /* Obtain and remap AHB address. */ 1844 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 1845 if (IS_ERR(cqspi->ahb_base)) { 1846 dev_err(dev, "Cannot remap AHB address.\n"); 1847 ret = PTR_ERR(cqspi->ahb_base); 1848 return ret; 1849 } 1850 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 1851 cqspi->ahb_size = resource_size(res_ahb); 1852 1853 init_completion(&cqspi->transfer_complete); 1854 1855 /* Obtain IRQ line. */ 1856 irq = platform_get_irq(pdev, 0); 1857 if (irq < 0) 1858 return -ENXIO; 1859 1860 ret = pm_runtime_set_active(dev); 1861 if (ret) 1862 return ret; 1863 1864 ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 1865 if (ret) { 1866 dev_err(dev, "Cannot enable QSPI clocks.\n"); 1867 goto disable_rpm; 1868 } 1869 1870 /* Obtain QSPI reset control */ 1871 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 1872 if (IS_ERR(rstc)) { 1873 ret = PTR_ERR(rstc); 1874 dev_err(dev, "Cannot get QSPI reset.\n"); 1875 goto disable_clks; 1876 } 1877 1878 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1879 if (IS_ERR(rstc_ocp)) { 1880 ret = PTR_ERR(rstc_ocp); 1881 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1882 goto disable_clks; 1883 } 1884 1885 if (cqspi->is_jh7110) { 1886 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 1887 if (IS_ERR(rstc_ref)) { 1888 ret = PTR_ERR(rstc_ref); 1889 dev_err(dev, "Cannot get QSPI REF reset.\n"); 1890 goto disable_clks; 1891 } 1892 reset_control_assert(rstc_ref); 1893 reset_control_deassert(rstc_ref); 1894 } 1895 1896 reset_control_assert(rstc); 1897 reset_control_deassert(rstc); 1898 1899 reset_control_assert(rstc_ocp); 1900 reset_control_deassert(rstc_ocp); 1901 1902 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); 1903 if (!cqspi->is_rzn1) { 1904 host->max_speed_hz = cqspi->master_ref_clk_hz; 1905 } else { 1906 host->max_speed_hz = cqspi->master_ref_clk_hz / 2; 1907 host->min_speed_hz = cqspi->master_ref_clk_hz / 32; 1908 } 1909 1910 /* write completion is supported by default */ 1911 cqspi->wr_completion = true; 1912 1913 if (ddata) { 1914 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1915 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 1916 cqspi->master_ref_clk_hz); 1917 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1918 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1919 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD) 1920 host->mode_bits |= SPI_TX_QUAD; 1921 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 1922 cqspi->use_direct_mode = true; 1923 cqspi->use_direct_mode_wr = true; 1924 } 1925 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 1926 cqspi->use_dma_read = true; 1927 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 1928 cqspi->wr_completion = false; 1929 if (ddata->quirks & CQSPI_SLOW_SRAM) 1930 cqspi->slow_sram = true; 1931 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) 1932 cqspi->apb_ahb_hazard = true; 1933 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) 1934 cqspi->disable_stig_mode = true; 1935 1936 if (ddata->quirks & CQSPI_DMA_SET_MASK) { 1937 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1938 if (ret) 1939 goto disable_clks; 1940 } 1941 } 1942 1943 refcount_set(&cqspi->refcount, 1); 1944 refcount_set(&cqspi->inflight_ops, 1); 1945 1946 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 1947 pdev->name, cqspi); 1948 if (ret) { 1949 dev_err(dev, "Cannot request IRQ.\n"); 1950 goto disable_clks; 1951 } 1952 1953 cqspi_wait_idle(cqspi); 1954 cqspi_controller_enable(cqspi, 0); 1955 cqspi_controller_detect_fifo_depth(cqspi); 1956 cqspi_controller_init(cqspi); 1957 cqspi_controller_enable(cqspi, 1); 1958 cqspi->current_cs = -1; 1959 cqspi->sclk = 0; 1960 1961 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 1962 pm_runtime_enable(dev); 1963 pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT); 1964 pm_runtime_use_autosuspend(dev); 1965 pm_runtime_get_noresume(dev); 1966 } 1967 1968 host->num_chipselect = cqspi->num_chipselect; 1969 1970 if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) 1971 cqspi_device_reset(cqspi); 1972 1973 if (cqspi->use_direct_mode && !cqspi->is_rzn1) { 1974 ret = cqspi_request_mmap_dma(cqspi); 1975 if (ret == -EPROBE_DEFER) { 1976 dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); 1977 goto disable_controller; 1978 } 1979 } 1980 1981 ret = spi_register_controller(host); 1982 if (ret) { 1983 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 1984 goto release_dma_chan; 1985 } 1986 1987 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 1988 pm_runtime_put_autosuspend(dev); 1989 1990 return 0; 1991 1992 release_dma_chan: 1993 if (cqspi->rx_chan) 1994 dma_release_channel(cqspi->rx_chan); 1995 disable_controller: 1996 cqspi_controller_enable(cqspi, 0); 1997 disable_clks: 1998 if (pm_runtime_get_sync(&pdev->dev) >= 0) 1999 clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2000 disable_rpm: 2001 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2002 pm_runtime_disable(dev); 2003 2004 return ret; 2005 } 2006 2007 static void cqspi_remove(struct platform_device *pdev) 2008 { 2009 const struct cqspi_driver_platdata *ddata; 2010 struct cqspi_st *cqspi = platform_get_drvdata(pdev); 2011 struct device *dev = &pdev->dev; 2012 int ret = 0; 2013 2014 ddata = of_device_get_match_data(dev); 2015 2016 refcount_set(&cqspi->refcount, 0); 2017 2018 if (!refcount_dec_and_test(&cqspi->inflight_ops)) 2019 cqspi_wait_idle(cqspi); 2020 2021 spi_unregister_controller(cqspi->host); 2022 2023 if (cqspi->rx_chan) 2024 dma_release_channel(cqspi->rx_chan); 2025 2026 cqspi_controller_enable(cqspi, 0); 2027 2028 2029 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2030 ret = pm_runtime_get_sync(&pdev->dev); 2031 2032 if (ret >= 0) 2033 clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2034 2035 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 2036 pm_runtime_put_sync(&pdev->dev); 2037 pm_runtime_disable(&pdev->dev); 2038 } 2039 } 2040 2041 static int cqspi_runtime_suspend(struct device *dev) 2042 { 2043 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2044 2045 cqspi_controller_enable(cqspi, 0); 2046 clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2047 return 0; 2048 } 2049 2050 static int cqspi_runtime_resume(struct device *dev) 2051 { 2052 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2053 int ret; 2054 2055 ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 2056 if (ret) 2057 return ret; 2058 2059 cqspi_wait_idle(cqspi); 2060 cqspi_controller_enable(cqspi, 0); 2061 cqspi_controller_init(cqspi); 2062 cqspi_controller_enable(cqspi, 1); 2063 2064 cqspi->current_cs = -1; 2065 cqspi->sclk = 0; 2066 return 0; 2067 } 2068 2069 static int cqspi_suspend(struct device *dev) 2070 { 2071 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2072 int ret; 2073 2074 ret = spi_controller_suspend(cqspi->host); 2075 if (ret) 2076 return ret; 2077 2078 return pm_runtime_force_suspend(dev); 2079 } 2080 2081 static int cqspi_resume(struct device *dev) 2082 { 2083 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2084 int ret; 2085 2086 ret = pm_runtime_force_resume(dev); 2087 if (ret) { 2088 dev_err(dev, "pm_runtime_force_resume failed on resume\n"); 2089 return ret; 2090 } 2091 2092 return spi_controller_resume(cqspi->host); 2093 } 2094 2095 static const struct dev_pm_ops cqspi_dev_pm_ops = { 2096 RUNTIME_PM_OPS(cqspi_runtime_suspend, cqspi_runtime_resume, NULL) 2097 SYSTEM_SLEEP_PM_OPS(cqspi_suspend, cqspi_resume) 2098 }; 2099 2100 static const struct cqspi_driver_platdata cdns_qspi = { 2101 .quirks = CQSPI_DISABLE_DAC_MODE, 2102 }; 2103 2104 static const struct cqspi_driver_platdata k2g_qspi = { 2105 .quirks = CQSPI_NEEDS_WR_DELAY, 2106 }; 2107 2108 static const struct cqspi_driver_platdata am654_ospi = { 2109 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD, 2110 .quirks = CQSPI_NEEDS_WR_DELAY, 2111 }; 2112 2113 static const struct cqspi_driver_platdata intel_lgm_qspi = { 2114 .quirks = CQSPI_DISABLE_DAC_MODE, 2115 }; 2116 2117 static const struct cqspi_driver_platdata socfpga_qspi = { 2118 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | 2119 CQSPI_SLOW_SRAM | CQSPI_DISABLE_STIG_MODE | 2120 CQSPI_DISABLE_RUNTIME_PM, 2121 }; 2122 2123 static const struct cqspi_driver_platdata versal_ospi = { 2124 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2125 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | 2126 CQSPI_DMA_SET_MASK, 2127 .indirect_read_dma = cqspi_versal_indirect_read_dma, 2128 .get_dma_status = cqspi_get_versal_dma_status, 2129 }; 2130 2131 static const struct cqspi_driver_platdata versal2_ospi = { 2132 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2133 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | 2134 CQSPI_DMA_SET_MASK | CQSPI_SUPPORT_DEVICE_RESET, 2135 .indirect_read_dma = cqspi_versal_indirect_read_dma, 2136 .get_dma_status = cqspi_get_versal_dma_status, 2137 }; 2138 2139 static const struct cqspi_driver_platdata jh7110_qspi = { 2140 .quirks = CQSPI_DISABLE_DAC_MODE, 2141 }; 2142 2143 static const struct cqspi_driver_platdata pensando_cdns_qspi = { 2144 .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, 2145 }; 2146 2147 static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = { 2148 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2149 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | 2150 CQSPI_RD_NO_IRQ, 2151 }; 2152 2153 static const struct cqspi_driver_platdata renesas_rzn1_qspi = { 2154 .hwcaps_mask = CQSPI_SUPPORTS_QUAD, 2155 .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ | 2156 CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE, 2157 }; 2158 2159 static const struct of_device_id cqspi_dt_ids[] = { 2160 { 2161 .compatible = "cdns,qspi-nor", 2162 .data = &cdns_qspi, 2163 }, 2164 { 2165 .compatible = "ti,k2g-qspi", 2166 .data = &k2g_qspi, 2167 }, 2168 { 2169 .compatible = "ti,am654-ospi", 2170 .data = &am654_ospi, 2171 }, 2172 { 2173 .compatible = "intel,lgm-qspi", 2174 .data = &intel_lgm_qspi, 2175 }, 2176 { 2177 .compatible = "xlnx,versal-ospi-1.0", 2178 .data = &versal_ospi, 2179 }, 2180 { 2181 .compatible = "intel,socfpga-qspi", 2182 .data = &socfpga_qspi, 2183 }, 2184 { 2185 .compatible = "starfive,jh7110-qspi", 2186 .data = &jh7110_qspi, 2187 }, 2188 { 2189 .compatible = "amd,pensando-elba-qspi", 2190 .data = &pensando_cdns_qspi, 2191 }, 2192 { 2193 .compatible = "mobileye,eyeq5-ospi", 2194 .data = &mobileye_eyeq5_ospi, 2195 }, 2196 { 2197 .compatible = "amd,versal2-ospi", 2198 .data = &versal2_ospi, 2199 }, 2200 { 2201 .compatible = "renesas,rzn1-qspi", 2202 .data = &renesas_rzn1_qspi, 2203 }, 2204 { /* end of table */ } 2205 }; 2206 2207 MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 2208 2209 static struct platform_driver cqspi_platform_driver = { 2210 .probe = cqspi_probe, 2211 .remove = cqspi_remove, 2212 .driver = { 2213 .name = CQSPI_NAME, 2214 .pm = pm_ptr(&cqspi_dev_pm_ops), 2215 .of_match_table = cqspi_dt_ids, 2216 }, 2217 }; 2218 2219 module_platform_driver(cqspi_platform_driver); 2220 2221 MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 2222 MODULE_LICENSE("GPL v2"); 2223 MODULE_ALIAS("platform:" CQSPI_NAME); 2224 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 2225 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 2226 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 2227 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 2228 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 2229