Searched refs:CP_MEC_CNTL (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v11_0.c | 3876 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); in gfx_v11_0_cp_compute_enable()
3878 data = REG_SET_FIELD(data, CP_MEC_CNTL, in gfx_v11_0_cp_compute_enable()
3881 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); in gfx_v11_0_cp_compute_enable()
3882 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); in gfx_v11_0_cp_compute_enable()
6977 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v11_0_reset_compute_pipe()
6979 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, in gfx_v11_0_reset_compute_pipe()
6983 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v11_0_reset_compute_pipe()
6985 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, in gfx_v11_0_reset_compute_pipe()
6989 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v11_0_reset_compute_pipe()
6991 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, in gfx_v11_0_reset_compute_pipe()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 1208 pipe_reset_data = REG_SET_FIELD(pipe_reset_data, CP_MEC_CNTL, MEC_ME1_PIPE0_RESET, 1); in kgd_gfx_v9_hqd_reset()
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| H A D | gfx_v12_0.c | 5402 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v12_0_reset_compute_pipe()
5404 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, in gfx_v12_0_reset_compute_pipe()
5408 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v12_0_reset_compute_pipe()
5410 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, in gfx_v12_0_reset_compute_pipe()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | smu8_smumgr.c | 193 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); in smu8_load_mec_firmware()
194 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); in smu8_load_mec_firmware()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 1094 #define CP_MEC_CNTL 0x8234 macro
1098 #define CP_MEC_CNTL 0x8234 macro
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