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Searched refs:CP_ME1_PIPE0_INT_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c6489 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6491 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6497 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6499 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6629 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_priv_reg_fault_state()
6675 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_bad_op_fault_state()
6825 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6835 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
H A Dgfx_v12_0.c4826 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4828 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4834 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4836 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4966 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_priv_reg_fault_state()
5012 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_bad_op_fault_state()
H A Dgfx_v9_4_3.c3206 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3212 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3269 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_set_priv_reg_fault_state()
3309 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_set_bad_op_fault_state()
H A Dgfx_v12_1.c3930 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3932 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3938 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3940 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c6057 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
6063 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
6118 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_priv_reg_fault_state()
6154 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_bad_op_fault_state()
H A Dgfx_v10_0.c9136 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9142 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9264 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_priv_reg_fault_state()
9310 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_bad_op_fault_state()
H A Dgfx_v8_0.c6437 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro