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Searched refs:CP_ME1_PIPE0_INT_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c6465 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6467 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6473 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6475 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6590 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_priv_reg_fault_state()
6636 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_bad_op_fault_state()
6777 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6787 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
H A Dgfx_v12_0.c4796 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4798 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4804 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4806 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4921 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_priv_reg_fault_state()
4967 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_bad_op_fault_state()
H A Dgfx_v12_1.c3581 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3583 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3589 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3591 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c6004 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
6010 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
6065 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_priv_reg_fault_state()
6101 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_bad_op_fault_state()
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro