Home
last modified time | relevance | path

Searched refs:CP_INT_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c5136 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
5137 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
5138 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
5139 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
5246 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); in gfx_v11_0_get_gpu_clock_counter()
5247 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v11_0_get_gpu_clock_counter()
5248 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); in gfx_v11_0_get_gpu_clock_counter()
5249 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); in gfx_v11_0_get_gpu_clock_counter()
5612 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v11_0_update_coarse_grain_clock_gating()
5613 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABL in gfx_v11_0_update_coarse_grain_clock_gating()
[all...]
H A Dgfx_v12_1.c3184 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v12_1_xcc_update_repeater_fgcg()
3185 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); in gfx_v12_1_xcc_update_repeater_fgcg()
3186 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); in gfx_v12_1_xcc_update_repeater_fgcg()
3187 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); in gfx_v12_1_xcc_update_repeater_fgcg()
H A Dgfx_v12_0.c4189 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
4190 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
4191 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
4192 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu72_discrete.h499 uint32_t CP_INT_CNTL; member
H A Dsmu74_discrete.h490 uint32_t CP_INT_CNTL; member
H A Dsmu73_discrete.h481 uint32_t CP_INT_CNTL; member
H A Dsmu75_discrete.h501 uint32_t CP_INT_CNTL; member
/linux/drivers/gpu/drm/radeon/
H A Dnid.h494 #define CP_INT_CNTL 0xC124 macro
H A Devergreend.h1246 #define CP_INT_CNTL 0xc124 macro
H A Dr600d.h714 #define CP_INT_CNTL 0xc124 macro
H A Dni.c1370 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
H A Dr600.c3622 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in r600_disable_interrupt_state()
3873 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()