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Searched refs:CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c191 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
H A Dkfd_mqd_manager_v10.c177 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
H A Dkfd_mqd_manager_v11.c216 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
H A Dkfd_mqd_manager_v9.c265 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3339 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f macro
H A Dgfx_8_1_sh_mask.h4475 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f macro
H A Dgfx_8_0_sh_mask.h3953 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12907 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_9_1_sh_mask.h14207 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_9_2_1_sh_mask.h14072 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_9_4_2_sh_mask.h4004 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_11_5_0_sh_mask.h14078 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_11_0_0_sh_mask.h17384 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_12_0_0_sh_mask.h13283 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_10_1_0_sh_mask.h20318 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro
H A Dgc_11_0_3_sh_mask.h19623 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK … macro