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Searched refs:CPG_PLL_MON_LOCK (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/renesas/
H A Drzv2h-cpg.c66 #define CPG_PLL_MON_LOCK BIT(4) macro
417 val, !(val & CPG_PLL_MON_LOCK), in rzv2h_cpg_pll_set_rate()
445 val, (val & CPG_PLL_MON_LOCK), in rzv2h_cpg_pll_set_rate()
633 return (val & (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) == in rzv2h_cpg_pll_clk_is_enabled()
634 (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK); in rzv2h_cpg_pll_clk_is_enabled()
665 (val & (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) == in rzv2h_cpg_pll_clk_enable()
666 (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK), 200, 2000); in rzv2h_cpg_pll_clk_enable()
H A Dr9a09g077-cpg.c88 #define CPG_PLL_MON_LOCK BIT(0) macro
640 val, !(val & CPG_PLL_MON_LOCK), in r9a09g077_cpg_pll3_set_rate()
663 val, (val & CPG_PLL_MON_LOCK), in r9a09g077_cpg_pll3_set_rate()
H A Drzg2l-cpg.c67 #define CPG_PLL_MON_LOCK BIT(4) macro
1183 u32 mon_val = CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK; in rzg3l_cpg_pll_clk_is_enabled()
1193 u32 mon_mask = CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK; in rzg3l_cpg_pll_clk_endisable()