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Searched refs:CP0 (Results 1 – 10 of 10) sorted by relevance

/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9132-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9132-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9131-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9131-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9130-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
/linux/arch/arm/kernel/
H A Diwmmxt.S73 @ CP0 and CP1 accessible?
76 @ enable access to CP0 and CP1
204 @ enable access to CP0 and CP1
215 @ disable access to CP0 and CP1
313 @ CP0 and CP1 accessible?
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-opp-mowgli.dts524 /* CP0 VDD & VCS : IR35221 */
525 /* CP0 VDN & VIO : IR35221 */
526 /* CP0 VDDR : IR35221 */
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h850 #define CP0 (1 << 0) macro
H A Dcik.c3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()