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Searched refs:CP0 (Results 1 – 10 of 10) sorted by relevance

/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9132-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9132-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9131-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9131-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9130-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Darmada-8040-clearfog-gt-8k.dts271 * [35-38] CP0 I2C1 and I2C0
441 * [29] CP0 10G SFP TX Disable
/linux/arch/arm/kernel/
H A Diwmmxt.S73 @ CP0 and CP1 accessible?
76 @ enable access to CP0 and CP1
204 @ enable access to CP0 and CP1
215 @ disable access to CP0 and CP1
313 @ CP0 and CP1 accessible?
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h850 #define CP0 (1 << 0) macro
/linux/Documentation/virt/kvm/
H A Dapi.rst2721 MIPS CP0 registers (see KVM_REG_MIPS_CP0_* above) have the following id bit