1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 *
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 */
7
8 #include <linux/module.h>
9 #include <linux/delay.h>
10 #include <linux/mmc/mmc.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/pm_opp.h>
13 #include <linux/slab.h>
14 #include <linux/iopoll.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/of.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/reset.h>
20
21 #include <soc/qcom/ice.h>
22
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
25 #include "cqhci.h"
26
27 #define CORE_MCI_VERSION 0x50
28 #define CORE_VERSION_MAJOR_SHIFT 28
29 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK 0xff
31
32 #define CORE_MCI_GENERICS 0x70
33 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
34
35 #define HC_MODE_EN 0x1
36 #define CORE_POWER 0x0
37 #define CORE_SW_RST BIT(7)
38 #define FF_CLK_SW_RST_DIS BIT(13)
39
40 #define CORE_PWRCTL_BUS_OFF BIT(0)
41 #define CORE_PWRCTL_BUS_ON BIT(1)
42 #define CORE_PWRCTL_IO_LOW BIT(2)
43 #define CORE_PWRCTL_IO_HIGH BIT(3)
44 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
45 #define CORE_PWRCTL_BUS_FAIL BIT(1)
46 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
47 #define CORE_PWRCTL_IO_FAIL BIT(3)
48 #define REQ_BUS_OFF BIT(0)
49 #define REQ_BUS_ON BIT(1)
50 #define REQ_IO_LOW BIT(2)
51 #define REQ_IO_HIGH BIT(3)
52 #define INT_MASK 0xf
53 #define MAX_PHASES 16
54 #define CORE_DLL_LOCK BIT(7)
55 #define CORE_DDR_DLL_LOCK BIT(11)
56 #define CORE_DLL_EN BIT(16)
57 #define CORE_CDR_EN BIT(17)
58 #define CORE_CK_OUT_EN BIT(18)
59 #define CORE_CDR_EXT_EN BIT(19)
60 #define CORE_DLL_PDN BIT(29)
61 #define CORE_DLL_RST BIT(30)
62 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
63
64 #define CORE_DDR_CAL_EN BIT(0)
65 #define CORE_FLL_CYCLE_CNT BIT(18)
66 #define CORE_DLL_CLOCK_DISABLE BIT(21)
67
68 #define DLL_USR_CTL_POR_VAL 0x10800
69 #define ENABLE_DLL_LOCK_STATUS BIT(26)
70 #define FINE_TUNE_MODE_EN BIT(27)
71 #define BIAS_OK_SIGNAL BIT(29)
72
73 #define DLL_CONFIG_3_LOW_FREQ_VAL 0x08
74 #define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10
75
76 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
77 #define CORE_CLK_PWRSAVE BIT(1)
78 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
79 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
80 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
81 #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
82 #define CORE_IO_PAD_PWR_SWITCH BIT(16)
83 #define CORE_HC_SELECT_IN_EN BIT(18)
84 #define CORE_HC_SELECT_IN_SDR50 (4 << 19)
85 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
86 #define CORE_HC_SELECT_IN_MASK (7 << 19)
87
88 #define CORE_3_0V_SUPPORT BIT(25)
89 #define CORE_1_8V_SUPPORT BIT(26)
90 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
91
92 #define CORE_CSR_CDC_CTLR_CFG0 0x130
93 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
94 #define CORE_HW_AUTOCAL_ENA BIT(17)
95
96 #define CORE_CSR_CDC_CTLR_CFG1 0x134
97 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
98 #define CORE_TIMER_ENA BIT(16)
99
100 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
101 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
102 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
103 #define CORE_CDC_OFFSET_CFG 0x14C
104 #define CORE_CSR_CDC_DELAY_CFG 0x150
105 #define CORE_CDC_SLAVE_DDA_CFG 0x160
106 #define CORE_CSR_CDC_STATUS0 0x164
107 #define CORE_CALIBRATION_DONE BIT(0)
108
109 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
110
111 #define CORE_CSR_CDC_GEN_CFG 0x178
112 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
113 #define CORE_CDC_SWITCH_RC_EN BIT(1)
114
115 #define CORE_CDC_T4_DLY_SEL BIT(0)
116 #define CORE_CMDIN_RCLK_EN BIT(1)
117 #define CORE_START_CDC_TRAFFIC BIT(6)
118
119 #define CORE_PWRSAVE_DLL BIT(3)
120
121 #define DDR_CONFIG_POR_VAL 0x80040873
122
123
124 #define INVALID_TUNING_PHASE -1
125 #define SDHCI_MSM_MIN_CLOCK 400000
126 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
127
128 #define CDR_SELEXT_SHIFT 20
129 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
130 #define CMUX_SHIFT_PHASE_SHIFT 24
131 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
132
133 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
134
135 /* Timeout value to avoid infinite waiting for pwr_irq */
136 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
137
138 /* Max load for eMMC Vdd supply */
139 #define MMC_VMMC_MAX_LOAD_UA 570000
140
141 /* Max load for eMMC Vdd-io supply */
142 #define MMC_VQMMC_MAX_LOAD_UA 325000
143
144 /* Max load for SD Vdd supply */
145 #define SD_VMMC_MAX_LOAD_UA 800000
146
147 /* Max load for SD Vdd-io supply */
148 #define SD_VQMMC_MAX_LOAD_UA 22000
149
150 #define msm_host_readl(msm_host, host, offset) \
151 msm_host->var_ops->msm_readl_relaxed(host, offset)
152
153 #define msm_host_writel(msm_host, val, host, offset) \
154 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
155
156 /* CQHCI vendor specific registers */
157 #define CQHCI_VENDOR_CFG1 0xA00
158 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
159
160 /* non command queue crypto enable register*/
161 #define NONCQ_CRYPTO_PARM 0x70
162 #define NONCQ_CRYPTO_DUN 0x74
163
164 #define DISABLE_CRYPTO BIT(15)
165 #define CRYPTO_GENERAL_ENABLE BIT(1)
166 #define HC_VENDOR_SPECIFIC_FUNC4 0x260
167
168 #define ICE_HCI_PARAM_CCI GENMASK(7, 0)
169 #define ICE_HCI_PARAM_CE GENMASK(8, 8)
170
171 struct sdhci_msm_offset {
172 u32 core_hc_mode;
173 u32 core_mci_data_cnt;
174 u32 core_mci_status;
175 u32 core_mci_fifo_cnt;
176 u32 core_mci_version;
177 u32 core_generics;
178 u32 core_testbus_config;
179 u32 core_testbus_sel2_bit;
180 u32 core_testbus_ena;
181 u32 core_testbus_sel2;
182 u32 core_pwrctl_status;
183 u32 core_pwrctl_mask;
184 u32 core_pwrctl_clear;
185 u32 core_pwrctl_ctl;
186 u32 core_sdcc_debug_reg;
187 u32 core_dll_config;
188 u32 core_dll_status;
189 u32 core_vendor_spec;
190 u32 core_vendor_spec_adma_err_addr0;
191 u32 core_vendor_spec_adma_err_addr1;
192 u32 core_vendor_spec_func2;
193 u32 core_vendor_spec_capabilities0;
194 u32 core_ddr_200_cfg;
195 u32 core_vendor_spec3;
196 u32 core_dll_config_2;
197 u32 core_dll_config_3;
198 u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
199 u32 core_ddr_config;
200 u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
201 };
202
203 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
204 .core_mci_data_cnt = 0x35c,
205 .core_mci_status = 0x324,
206 .core_mci_fifo_cnt = 0x308,
207 .core_mci_version = 0x318,
208 .core_generics = 0x320,
209 .core_testbus_config = 0x32c,
210 .core_testbus_sel2_bit = 3,
211 .core_testbus_ena = (1 << 31),
212 .core_testbus_sel2 = (1 << 3),
213 .core_pwrctl_status = 0x240,
214 .core_pwrctl_mask = 0x244,
215 .core_pwrctl_clear = 0x248,
216 .core_pwrctl_ctl = 0x24c,
217 .core_sdcc_debug_reg = 0x358,
218 .core_dll_config = 0x200,
219 .core_dll_status = 0x208,
220 .core_vendor_spec = 0x20c,
221 .core_vendor_spec_adma_err_addr0 = 0x214,
222 .core_vendor_spec_adma_err_addr1 = 0x218,
223 .core_vendor_spec_func2 = 0x210,
224 .core_vendor_spec_capabilities0 = 0x21c,
225 .core_ddr_200_cfg = 0x224,
226 .core_vendor_spec3 = 0x250,
227 .core_dll_config_2 = 0x254,
228 .core_dll_config_3 = 0x258,
229 .core_ddr_config = 0x25c,
230 .core_dll_usr_ctl = 0x388,
231 };
232
233 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
234 .core_hc_mode = 0x78,
235 .core_mci_data_cnt = 0x30,
236 .core_mci_status = 0x34,
237 .core_mci_fifo_cnt = 0x44,
238 .core_mci_version = 0x050,
239 .core_generics = 0x70,
240 .core_testbus_config = 0x0cc,
241 .core_testbus_sel2_bit = 4,
242 .core_testbus_ena = (1 << 3),
243 .core_testbus_sel2 = (1 << 4),
244 .core_pwrctl_status = 0xdc,
245 .core_pwrctl_mask = 0xe0,
246 .core_pwrctl_clear = 0xe4,
247 .core_pwrctl_ctl = 0xe8,
248 .core_sdcc_debug_reg = 0x124,
249 .core_dll_config = 0x100,
250 .core_dll_status = 0x108,
251 .core_vendor_spec = 0x10c,
252 .core_vendor_spec_adma_err_addr0 = 0x114,
253 .core_vendor_spec_adma_err_addr1 = 0x118,
254 .core_vendor_spec_func2 = 0x110,
255 .core_vendor_spec_capabilities0 = 0x11c,
256 .core_ddr_200_cfg = 0x184,
257 .core_vendor_spec3 = 0x1b0,
258 .core_dll_config_2 = 0x1b4,
259 .core_ddr_config_old = 0x1b8,
260 .core_ddr_config = 0x1bc,
261 };
262
263 struct sdhci_msm_variant_ops {
264 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
265 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
266 u32 offset);
267 };
268
269 /*
270 * From V5, register spaces have changed. Wrap this info in a structure
271 * and choose the data_structure based on version info mentioned in DT.
272 */
273 struct sdhci_msm_variant_info {
274 bool mci_removed;
275 bool restore_dll_config;
276 const struct sdhci_msm_variant_ops *var_ops;
277 const struct sdhci_msm_offset *offset;
278 };
279
280 struct sdhci_msm_host {
281 struct platform_device *pdev;
282 void __iomem *core_mem; /* MSM SDCC mapped address */
283 int pwr_irq; /* power irq */
284 struct clk *bus_clk; /* SDHC bus voter clock */
285 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
286 /* core, iface, cal and sleep clocks */
287 struct clk_bulk_data bulk_clks[4];
288 #ifdef CONFIG_MMC_CRYPTO
289 struct qcom_ice *ice;
290 #endif
291 unsigned long clk_rate;
292 struct mmc_host *mmc;
293 bool use_14lpp_dll_reset;
294 bool tuning_done;
295 bool calibration_done;
296 u8 saved_tuning_phase;
297 bool use_cdclp533;
298 u32 curr_pwr_state;
299 u32 curr_io_level;
300 wait_queue_head_t pwr_irq_wait;
301 bool pwr_irq_flag;
302 u32 caps_0;
303 bool mci_removed;
304 bool restore_dll_config;
305 const struct sdhci_msm_variant_ops *var_ops;
306 const struct sdhci_msm_offset *offset;
307 bool use_cdr;
308 u32 transfer_mode;
309 bool updated_ddr_cfg;
310 bool uses_tassadar_dll;
311 u32 dll_config;
312 u32 ddr_config;
313 bool vqmmc_enabled;
314 bool non_cqe_ice_init_done;
315 };
316
sdhci_priv_msm_offset(struct sdhci_host * host)317 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
318 {
319 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
320 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
321
322 return msm_host->offset;
323 }
324
325 /*
326 * APIs to read/write to vendor specific registers which were there in the
327 * core_mem region before MCI was removed.
328 */
sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host * host,u32 offset)329 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
330 u32 offset)
331 {
332 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
333 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
334
335 return readl_relaxed(msm_host->core_mem + offset);
336 }
337
sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host * host,u32 offset)338 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
339 u32 offset)
340 {
341 return readl_relaxed(host->ioaddr + offset);
342 }
343
sdhci_msm_mci_variant_writel_relaxed(u32 val,struct sdhci_host * host,u32 offset)344 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
345 struct sdhci_host *host, u32 offset)
346 {
347 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
348 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
349
350 writel_relaxed(val, msm_host->core_mem + offset);
351 }
352
sdhci_msm_v5_variant_writel_relaxed(u32 val,struct sdhci_host * host,u32 offset)353 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
354 struct sdhci_host *host, u32 offset)
355 {
356 writel_relaxed(val, host->ioaddr + offset);
357 }
358
msm_get_clock_mult_for_bus_mode(struct sdhci_host * host,unsigned int clock,unsigned int timing)359 static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host,
360 unsigned int clock,
361 unsigned int timing)
362 {
363 /*
364 * The SDHC requires internal clock frequency to be double the
365 * actual clock that will be set for DDR mode. The controller
366 * uses the faster clock(100/400MHz) for some of its parts and
367 * send the actual required clock (50/200MHz) to the card.
368 */
369 if (timing == MMC_TIMING_UHS_DDR50 ||
370 timing == MMC_TIMING_MMC_DDR52 ||
371 (timing == MMC_TIMING_MMC_HS400 &&
372 clock == MMC_HS200_MAX_DTR) ||
373 host->flags & SDHCI_HS400_TUNING)
374 return 2;
375 return 1;
376 }
377
msm_set_clock_rate_for_bus_mode(struct sdhci_host * host,unsigned int clock,unsigned int timing)378 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
379 unsigned int clock,
380 unsigned int timing)
381 {
382 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
383 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
384 struct clk *core_clk = msm_host->bulk_clks[0].clk;
385 unsigned long achieved_rate;
386 unsigned int desired_rate;
387 unsigned int mult;
388 int rc;
389
390 mult = msm_get_clock_mult_for_bus_mode(host, clock, timing);
391 desired_rate = clock * mult;
392 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate);
393 if (rc) {
394 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
395 mmc_hostname(host->mmc), desired_rate, timing);
396 return;
397 }
398
399 /*
400 * Qualcomm clock drivers by default round clock _up_ if they can't
401 * make the requested rate. This is not good for SD. Yell if we
402 * encounter it.
403 */
404 achieved_rate = clk_get_rate(core_clk);
405 if (achieved_rate > desired_rate)
406 pr_warn("%s: Card appears overclocked; req %u Hz, actual %lu Hz\n",
407 mmc_hostname(host->mmc), desired_rate, achieved_rate);
408 host->mmc->actual_clock = achieved_rate / mult;
409
410 /* Stash the rate we requested to use in sdhci_msm_runtime_resume() */
411 msm_host->clk_rate = desired_rate;
412
413 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
414 mmc_hostname(host->mmc), achieved_rate, timing);
415 }
416
417 /* Platform specific tuning */
msm_dll_poll_ck_out_en(struct sdhci_host * host,u8 poll)418 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
419 {
420 u32 wait_cnt = 50;
421 u8 ck_out_en;
422 struct mmc_host *mmc = host->mmc;
423 const struct sdhci_msm_offset *msm_offset =
424 sdhci_priv_msm_offset(host);
425
426 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
427 ck_out_en = !!(readl_relaxed(host->ioaddr +
428 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
429
430 while (ck_out_en != poll) {
431 if (--wait_cnt == 0) {
432 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
433 mmc_hostname(mmc), poll);
434 return -ETIMEDOUT;
435 }
436 udelay(1);
437
438 ck_out_en = !!(readl_relaxed(host->ioaddr +
439 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
440 }
441
442 return 0;
443 }
444
msm_config_cm_dll_phase(struct sdhci_host * host,u8 phase)445 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
446 {
447 int rc;
448 static const u8 grey_coded_phase_table[] = {
449 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
450 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
451 };
452 unsigned long flags;
453 u32 config;
454 struct mmc_host *mmc = host->mmc;
455 const struct sdhci_msm_offset *msm_offset =
456 sdhci_priv_msm_offset(host);
457
458 if (phase > 0xf)
459 return -EINVAL;
460
461 spin_lock_irqsave(&host->lock, flags);
462
463 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
464 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
465 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
466 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
467
468 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
469 rc = msm_dll_poll_ck_out_en(host, 0);
470 if (rc)
471 goto err_out;
472
473 /*
474 * Write the selected DLL clock output phase (0 ... 15)
475 * to CDR_SELEXT bit field of DLL_CONFIG register.
476 */
477 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
478 config &= ~CDR_SELEXT_MASK;
479 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
480 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
481
482 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
483 config |= CORE_CK_OUT_EN;
484 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
485
486 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
487 rc = msm_dll_poll_ck_out_en(host, 1);
488 if (rc)
489 goto err_out;
490
491 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
492 config |= CORE_CDR_EN;
493 config &= ~CORE_CDR_EXT_EN;
494 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
495 goto out;
496
497 err_out:
498 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
499 mmc_hostname(mmc), phase);
500 out:
501 spin_unlock_irqrestore(&host->lock, flags);
502 return rc;
503 }
504
505 /*
506 * Find out the greatest range of consecuitive selected
507 * DLL clock output phases that can be used as sampling
508 * setting for SD3.0 UHS-I card read operation (in SDR104
509 * timing mode) or for eMMC4.5 card read operation (in
510 * HS400/HS200 timing mode).
511 * Select the 3/4 of the range and configure the DLL with the
512 * selected DLL clock output phase.
513 */
514
msm_find_most_appropriate_phase(struct sdhci_host * host,u8 * phase_table,u8 total_phases)515 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
516 u8 *phase_table, u8 total_phases)
517 {
518 int ret;
519 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
520 u8 phases_per_row[MAX_PHASES] = { 0 };
521 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
522 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
523 bool phase_0_found = false, phase_15_found = false;
524 struct mmc_host *mmc = host->mmc;
525
526 if (!total_phases || (total_phases > MAX_PHASES)) {
527 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
528 mmc_hostname(mmc), total_phases);
529 return -EINVAL;
530 }
531
532 for (cnt = 0; cnt < total_phases; cnt++) {
533 ranges[row_index][col_index] = phase_table[cnt];
534 phases_per_row[row_index] += 1;
535 col_index++;
536
537 if ((cnt + 1) == total_phases) {
538 continue;
539 /* check if next phase in phase_table is consecutive or not */
540 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
541 row_index++;
542 col_index = 0;
543 }
544 }
545
546 if (row_index >= MAX_PHASES)
547 return -EINVAL;
548
549 /* Check if phase-0 is present in first valid window? */
550 if (!ranges[0][0]) {
551 phase_0_found = true;
552 phase_0_raw_index = 0;
553 /* Check if cycle exist between 2 valid windows */
554 for (cnt = 1; cnt <= row_index; cnt++) {
555 if (phases_per_row[cnt]) {
556 for (i = 0; i < phases_per_row[cnt]; i++) {
557 if (ranges[cnt][i] == 15) {
558 phase_15_found = true;
559 phase_15_raw_index = cnt;
560 break;
561 }
562 }
563 }
564 }
565 }
566
567 /* If 2 valid windows form cycle then merge them as single window */
568 if (phase_0_found && phase_15_found) {
569 /* number of phases in raw where phase 0 is present */
570 u8 phases_0 = phases_per_row[phase_0_raw_index];
571 /* number of phases in raw where phase 15 is present */
572 u8 phases_15 = phases_per_row[phase_15_raw_index];
573
574 if (phases_0 + phases_15 >= MAX_PHASES)
575 /*
576 * If there are more than 1 phase windows then total
577 * number of phases in both the windows should not be
578 * more than or equal to MAX_PHASES.
579 */
580 return -EINVAL;
581
582 /* Merge 2 cyclic windows */
583 i = phases_15;
584 for (cnt = 0; cnt < phases_0; cnt++) {
585 ranges[phase_15_raw_index][i] =
586 ranges[phase_0_raw_index][cnt];
587 if (++i >= MAX_PHASES)
588 break;
589 }
590
591 phases_per_row[phase_0_raw_index] = 0;
592 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
593 }
594
595 for (cnt = 0; cnt <= row_index; cnt++) {
596 if (phases_per_row[cnt] > curr_max) {
597 curr_max = phases_per_row[cnt];
598 selected_row_index = cnt;
599 }
600 }
601
602 i = (curr_max * 3) / 4;
603 if (i)
604 i--;
605
606 ret = ranges[selected_row_index][i];
607
608 if (ret >= MAX_PHASES) {
609 ret = -EINVAL;
610 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
611 mmc_hostname(mmc), ret);
612 }
613
614 return ret;
615 }
616
msm_cm_dll_set_freq(struct sdhci_host * host)617 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
618 {
619 u32 mclk_freq = 0, config;
620 const struct sdhci_msm_offset *msm_offset =
621 sdhci_priv_msm_offset(host);
622
623 /* Program the MCLK value to MCLK_FREQ bit field */
624 if (host->clock <= 112000000)
625 mclk_freq = 0;
626 else if (host->clock <= 125000000)
627 mclk_freq = 1;
628 else if (host->clock <= 137000000)
629 mclk_freq = 2;
630 else if (host->clock <= 150000000)
631 mclk_freq = 3;
632 else if (host->clock <= 162000000)
633 mclk_freq = 4;
634 else if (host->clock <= 175000000)
635 mclk_freq = 5;
636 else if (host->clock <= 187000000)
637 mclk_freq = 6;
638 else if (host->clock <= 200000000)
639 mclk_freq = 7;
640
641 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
642 config &= ~CMUX_SHIFT_PHASE_MASK;
643 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
644 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
645 }
646
647 /* Initialize the DLL (Programmable Delay Line) */
msm_init_cm_dll(struct sdhci_host * host)648 static int msm_init_cm_dll(struct sdhci_host *host)
649 {
650 struct mmc_host *mmc = host->mmc;
651 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
652 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
653 int wait_cnt = 50;
654 unsigned long flags, xo_clk = 0;
655 u32 config;
656 const struct sdhci_msm_offset *msm_offset =
657 msm_host->offset;
658
659 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
660 xo_clk = clk_get_rate(msm_host->xo_clk);
661
662 spin_lock_irqsave(&host->lock, flags);
663
664 /*
665 * Make sure that clock is always enabled when DLL
666 * tuning is in progress. Keeping PWRSAVE ON may
667 * turn off the clock.
668 */
669 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
670 config &= ~CORE_CLK_PWRSAVE;
671 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
672
673 if (msm_host->dll_config)
674 writel_relaxed(msm_host->dll_config,
675 host->ioaddr + msm_offset->core_dll_config);
676
677 if (msm_host->use_14lpp_dll_reset) {
678 config = readl_relaxed(host->ioaddr +
679 msm_offset->core_dll_config);
680 config &= ~CORE_CK_OUT_EN;
681 writel_relaxed(config, host->ioaddr +
682 msm_offset->core_dll_config);
683
684 config = readl_relaxed(host->ioaddr +
685 msm_offset->core_dll_config_2);
686 config |= CORE_DLL_CLOCK_DISABLE;
687 writel_relaxed(config, host->ioaddr +
688 msm_offset->core_dll_config_2);
689 }
690
691 config = readl_relaxed(host->ioaddr +
692 msm_offset->core_dll_config);
693 config |= CORE_DLL_RST;
694 writel_relaxed(config, host->ioaddr +
695 msm_offset->core_dll_config);
696
697 config = readl_relaxed(host->ioaddr +
698 msm_offset->core_dll_config);
699 config |= CORE_DLL_PDN;
700 writel_relaxed(config, host->ioaddr +
701 msm_offset->core_dll_config);
702
703 if (!msm_host->dll_config)
704 msm_cm_dll_set_freq(host);
705
706 if (msm_host->use_14lpp_dll_reset &&
707 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
708 u32 mclk_freq = 0;
709
710 config = readl_relaxed(host->ioaddr +
711 msm_offset->core_dll_config_2);
712 config &= CORE_FLL_CYCLE_CNT;
713 if (config)
714 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
715 xo_clk);
716 else
717 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
718 xo_clk);
719
720 config = readl_relaxed(host->ioaddr +
721 msm_offset->core_dll_config_2);
722 config &= ~(0xFF << 10);
723 config |= mclk_freq << 10;
724
725 writel_relaxed(config, host->ioaddr +
726 msm_offset->core_dll_config_2);
727 /* wait for 5us before enabling DLL clock */
728 udelay(5);
729 }
730
731 config = readl_relaxed(host->ioaddr +
732 msm_offset->core_dll_config);
733 config &= ~CORE_DLL_RST;
734 writel_relaxed(config, host->ioaddr +
735 msm_offset->core_dll_config);
736
737 config = readl_relaxed(host->ioaddr +
738 msm_offset->core_dll_config);
739 config &= ~CORE_DLL_PDN;
740 writel_relaxed(config, host->ioaddr +
741 msm_offset->core_dll_config);
742
743 if (msm_host->use_14lpp_dll_reset) {
744 if (!msm_host->dll_config)
745 msm_cm_dll_set_freq(host);
746 config = readl_relaxed(host->ioaddr +
747 msm_offset->core_dll_config_2);
748 config &= ~CORE_DLL_CLOCK_DISABLE;
749 writel_relaxed(config, host->ioaddr +
750 msm_offset->core_dll_config_2);
751 }
752
753 /*
754 * Configure DLL user control register to enable DLL status.
755 * This setting is applicable to SDCC v5.1 onwards only.
756 */
757 if (msm_host->uses_tassadar_dll) {
758 config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
759 ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
760 writel_relaxed(config, host->ioaddr +
761 msm_offset->core_dll_usr_ctl);
762
763 config = readl_relaxed(host->ioaddr +
764 msm_offset->core_dll_config_3);
765 config &= ~0xFF;
766 if (msm_host->clk_rate < 150000000)
767 config |= DLL_CONFIG_3_LOW_FREQ_VAL;
768 else
769 config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
770 writel_relaxed(config, host->ioaddr +
771 msm_offset->core_dll_config_3);
772 }
773
774 config = readl_relaxed(host->ioaddr +
775 msm_offset->core_dll_config);
776 config |= CORE_DLL_EN;
777 writel_relaxed(config, host->ioaddr +
778 msm_offset->core_dll_config);
779
780 config = readl_relaxed(host->ioaddr +
781 msm_offset->core_dll_config);
782 config |= CORE_CK_OUT_EN;
783 writel_relaxed(config, host->ioaddr +
784 msm_offset->core_dll_config);
785
786 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
787 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
788 CORE_DLL_LOCK)) {
789 /* max. wait for 50us sec for LOCK bit to be set */
790 if (--wait_cnt == 0) {
791 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
792 mmc_hostname(mmc));
793 spin_unlock_irqrestore(&host->lock, flags);
794 return -ETIMEDOUT;
795 }
796 udelay(1);
797 }
798
799 spin_unlock_irqrestore(&host->lock, flags);
800 return 0;
801 }
802
msm_hc_select_default(struct sdhci_host * host)803 static void msm_hc_select_default(struct sdhci_host *host)
804 {
805 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
806 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
807 u32 config;
808 const struct sdhci_msm_offset *msm_offset =
809 msm_host->offset;
810
811 if (!msm_host->use_cdclp533) {
812 config = readl_relaxed(host->ioaddr +
813 msm_offset->core_vendor_spec3);
814 config &= ~CORE_PWRSAVE_DLL;
815 writel_relaxed(config, host->ioaddr +
816 msm_offset->core_vendor_spec3);
817 }
818
819 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
820 config &= ~CORE_HC_MCLK_SEL_MASK;
821 config |= CORE_HC_MCLK_SEL_DFLT;
822 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
823
824 /*
825 * Disable HC_SELECT_IN to be able to use the UHS mode select
826 * configuration from Host Control2 register for all other
827 * modes.
828 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
829 * in VENDOR_SPEC_FUNC
830 */
831 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
832 config &= ~CORE_HC_SELECT_IN_EN;
833 config &= ~CORE_HC_SELECT_IN_MASK;
834 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
835
836 /*
837 * Make sure above writes impacting free running MCLK are completed
838 * before changing the clk_rate at GCC.
839 */
840 wmb();
841 }
842
msm_hc_select_hs400(struct sdhci_host * host)843 static void msm_hc_select_hs400(struct sdhci_host *host)
844 {
845 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
846 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
847 struct mmc_ios ios = host->mmc->ios;
848 u32 config, dll_lock;
849 int rc;
850 const struct sdhci_msm_offset *msm_offset =
851 msm_host->offset;
852
853 /* Select the divided clock (free running MCLK/2) */
854 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
855 config &= ~CORE_HC_MCLK_SEL_MASK;
856 config |= CORE_HC_MCLK_SEL_HS400;
857
858 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
859 /*
860 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
861 * register
862 */
863 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
864 !msm_host->calibration_done) {
865 config = readl_relaxed(host->ioaddr +
866 msm_offset->core_vendor_spec);
867 config |= CORE_HC_SELECT_IN_HS400;
868 config |= CORE_HC_SELECT_IN_EN;
869 writel_relaxed(config, host->ioaddr +
870 msm_offset->core_vendor_spec);
871 }
872 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
873 /*
874 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
875 * core_dll_status to be set. This should get set
876 * within 15 us at 200 MHz.
877 */
878 rc = readl_relaxed_poll_timeout(host->ioaddr +
879 msm_offset->core_dll_status,
880 dll_lock,
881 (dll_lock &
882 (CORE_DLL_LOCK |
883 CORE_DDR_DLL_LOCK)), 10,
884 1000);
885 if (rc == -ETIMEDOUT)
886 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
887 mmc_hostname(host->mmc), dll_lock);
888 }
889 /*
890 * Make sure above writes impacting free running MCLK are completed
891 * before changing the clk_rate at GCC.
892 */
893 wmb();
894 }
895
896 /*
897 * sdhci_msm_hc_select_mode :- In general all timing modes are
898 * controlled via UHS mode select in Host Control2 register.
899 * eMMC specific HS200/HS400 doesn't have their respective modes
900 * defined here, hence we use these values.
901 *
902 * HS200 - SDR104 (Since they both are equivalent in functionality)
903 * HS400 - This involves multiple configurations
904 * Initially SDR104 - when tuning is required as HS200
905 * Then when switching to DDR @ 400MHz (HS400) we use
906 * the vendor specific HC_SELECT_IN to control the mode.
907 *
908 * In addition to controlling the modes we also need to select the
909 * correct input clock for DLL depending on the mode.
910 *
911 * HS400 - divided clock (free running MCLK/2)
912 * All other modes - default (free running MCLK)
913 */
sdhci_msm_hc_select_mode(struct sdhci_host * host)914 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
915 {
916 struct mmc_ios ios = host->mmc->ios;
917
918 if (ios.timing == MMC_TIMING_MMC_HS400 ||
919 host->flags & SDHCI_HS400_TUNING)
920 msm_hc_select_hs400(host);
921 else
922 msm_hc_select_default(host);
923 }
924
sdhci_msm_cdclp533_calibration(struct sdhci_host * host)925 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
926 {
927 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
928 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
929 u32 config, calib_done;
930 int ret;
931 const struct sdhci_msm_offset *msm_offset =
932 msm_host->offset;
933
934 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
935
936 /*
937 * Retuning in HS400 (DDR mode) will fail, just reset the
938 * tuning block and restore the saved tuning phase.
939 */
940 ret = msm_init_cm_dll(host);
941 if (ret)
942 goto out;
943
944 /* Set the selected phase in delay line hw block */
945 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
946 if (ret)
947 goto out;
948
949 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
950 config |= CORE_CMD_DAT_TRACK_SEL;
951 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
952
953 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
954 config &= ~CORE_CDC_T4_DLY_SEL;
955 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
956
957 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
958 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
959 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
960
961 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
962 config |= CORE_CDC_SWITCH_RC_EN;
963 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
964
965 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
966 config &= ~CORE_START_CDC_TRAFFIC;
967 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
968
969 /* Perform CDC Register Initialization Sequence */
970
971 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
972 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
973 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
974 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
975 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
976 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
977 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
978 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
979 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
980
981 /* CDC HW Calibration */
982
983 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
984 config |= CORE_SW_TRIG_FULL_CALIB;
985 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
986
987 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
988 config &= ~CORE_SW_TRIG_FULL_CALIB;
989 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
990
991 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
992 config |= CORE_HW_AUTOCAL_ENA;
993 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
994
995 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
996 config |= CORE_TIMER_ENA;
997 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
998
999 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
1000 calib_done,
1001 (calib_done & CORE_CALIBRATION_DONE),
1002 1, 50);
1003
1004 if (ret == -ETIMEDOUT) {
1005 pr_err("%s: %s: CDC calibration was not completed\n",
1006 mmc_hostname(host->mmc), __func__);
1007 goto out;
1008 }
1009
1010 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
1011 & CORE_CDC_ERROR_CODE_MASK;
1012 if (ret) {
1013 pr_err("%s: %s: CDC error code %d\n",
1014 mmc_hostname(host->mmc), __func__, ret);
1015 ret = -EINVAL;
1016 goto out;
1017 }
1018
1019 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
1020 config |= CORE_START_CDC_TRAFFIC;
1021 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
1022 out:
1023 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1024 __func__, ret);
1025 return ret;
1026 }
1027
sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host * host)1028 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
1029 {
1030 struct mmc_host *mmc = host->mmc;
1031 u32 dll_status, config, ddr_cfg_offset;
1032 int ret;
1033 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1034 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1035 const struct sdhci_msm_offset *msm_offset =
1036 sdhci_priv_msm_offset(host);
1037
1038 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1039
1040 /*
1041 * Currently the core_ddr_config register defaults to desired
1042 * configuration on reset. Currently reprogramming the power on
1043 * reset (POR) value in case it might have been modified by
1044 * bootloaders. In the future, if this changes, then the desired
1045 * values will need to be programmed appropriately.
1046 */
1047 if (msm_host->updated_ddr_cfg)
1048 ddr_cfg_offset = msm_offset->core_ddr_config;
1049 else
1050 ddr_cfg_offset = msm_offset->core_ddr_config_old;
1051 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1052
1053 if (mmc->ios.enhanced_strobe) {
1054 config = readl_relaxed(host->ioaddr +
1055 msm_offset->core_ddr_200_cfg);
1056 config |= CORE_CMDIN_RCLK_EN;
1057 writel_relaxed(config, host->ioaddr +
1058 msm_offset->core_ddr_200_cfg);
1059 }
1060
1061 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1062 config |= CORE_DDR_CAL_EN;
1063 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1064
1065 ret = readl_relaxed_poll_timeout(host->ioaddr +
1066 msm_offset->core_dll_status,
1067 dll_status,
1068 (dll_status & CORE_DDR_DLL_LOCK),
1069 10, 1000);
1070
1071 if (ret == -ETIMEDOUT) {
1072 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
1073 mmc_hostname(host->mmc), __func__);
1074 goto out;
1075 }
1076
1077 /*
1078 * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1079 * When MCLK is gated OFF, it is not gated for less than 0.5us
1080 * and MCLK must be switched on for at-least 1us before DATA
1081 * starts coming. Controllers with 14lpp and later tech DLL cannot
1082 * guarantee above requirement. So PWRSAVE_DLL should not be
1083 * turned on for host controllers using this DLL.
1084 */
1085 if (!msm_host->use_14lpp_dll_reset) {
1086 config = readl_relaxed(host->ioaddr +
1087 msm_offset->core_vendor_spec3);
1088 config |= CORE_PWRSAVE_DLL;
1089 writel_relaxed(config, host->ioaddr +
1090 msm_offset->core_vendor_spec3);
1091 }
1092
1093 /*
1094 * Drain writebuffer to ensure above DLL calibration
1095 * and PWRSAVE DLL is enabled.
1096 */
1097 wmb();
1098 out:
1099 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1100 __func__, ret);
1101 return ret;
1102 }
1103
sdhci_msm_hs400_dll_calibration(struct sdhci_host * host)1104 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1105 {
1106 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1107 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1108 struct mmc_host *mmc = host->mmc;
1109 int ret;
1110 u32 config;
1111 const struct sdhci_msm_offset *msm_offset =
1112 msm_host->offset;
1113
1114 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1115
1116 /*
1117 * Retuning in HS400 (DDR mode) will fail, just reset the
1118 * tuning block and restore the saved tuning phase.
1119 */
1120 ret = msm_init_cm_dll(host);
1121 if (ret)
1122 goto out;
1123
1124 if (!mmc->ios.enhanced_strobe) {
1125 /* Set the selected phase in delay line hw block */
1126 ret = msm_config_cm_dll_phase(host,
1127 msm_host->saved_tuning_phase);
1128 if (ret)
1129 goto out;
1130 config = readl_relaxed(host->ioaddr +
1131 msm_offset->core_dll_config);
1132 config |= CORE_CMD_DAT_TRACK_SEL;
1133 writel_relaxed(config, host->ioaddr +
1134 msm_offset->core_dll_config);
1135 }
1136
1137 if (msm_host->use_cdclp533)
1138 ret = sdhci_msm_cdclp533_calibration(host);
1139 else
1140 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1141 out:
1142 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1143 __func__, ret);
1144 return ret;
1145 }
1146
sdhci_msm_is_tuning_needed(struct sdhci_host * host)1147 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1148 {
1149 struct mmc_ios *ios = &host->mmc->ios;
1150
1151 if (ios->timing == MMC_TIMING_UHS_SDR50 &&
1152 host->flags & SDHCI_SDR50_NEEDS_TUNING)
1153 return true;
1154
1155 /*
1156 * Tuning is required for SDR104, HS200 and HS400 cards and
1157 * if clock frequency is greater than 100MHz in these modes.
1158 */
1159 if (host->clock <= CORE_FREQ_100MHZ ||
1160 !(ios->timing == MMC_TIMING_MMC_HS400 ||
1161 ios->timing == MMC_TIMING_MMC_HS200 ||
1162 ios->timing == MMC_TIMING_UHS_SDR104) ||
1163 ios->enhanced_strobe)
1164 return false;
1165
1166 return true;
1167 }
1168
sdhci_msm_restore_sdr_dll_config(struct sdhci_host * host)1169 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1170 {
1171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1172 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1173 int ret;
1174
1175 /*
1176 * SDR DLL comes into picture only for timing modes which needs
1177 * tuning.
1178 */
1179 if (!sdhci_msm_is_tuning_needed(host))
1180 return 0;
1181
1182 /* Reset the tuning block */
1183 ret = msm_init_cm_dll(host);
1184 if (ret)
1185 return ret;
1186
1187 /* Restore the tuning block */
1188 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1189
1190 return ret;
1191 }
1192
sdhci_msm_set_cdr(struct sdhci_host * host,bool enable)1193 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1194 {
1195 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1196 u32 config, oldconfig = readl_relaxed(host->ioaddr +
1197 msm_offset->core_dll_config);
1198
1199 config = oldconfig;
1200 if (enable) {
1201 config |= CORE_CDR_EN;
1202 config &= ~CORE_CDR_EXT_EN;
1203 } else {
1204 config &= ~CORE_CDR_EN;
1205 config |= CORE_CDR_EXT_EN;
1206 }
1207
1208 if (config != oldconfig) {
1209 writel_relaxed(config, host->ioaddr +
1210 msm_offset->core_dll_config);
1211 }
1212 }
1213
sdhci_msm_execute_tuning(struct mmc_host * mmc,u32 opcode)1214 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1215 {
1216 struct sdhci_host *host = mmc_priv(mmc);
1217 int tuning_seq_cnt = 10;
1218 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1219 int rc;
1220 struct mmc_ios ios = host->mmc->ios;
1221 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1222 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1223 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1224 u32 config;
1225
1226 if (!sdhci_msm_is_tuning_needed(host)) {
1227 msm_host->use_cdr = false;
1228 sdhci_msm_set_cdr(host, false);
1229 return 0;
1230 }
1231
1232 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1233 msm_host->use_cdr = true;
1234
1235 /*
1236 * Clear tuning_done flag before tuning to ensure proper
1237 * HS400 settings.
1238 */
1239 msm_host->tuning_done = 0;
1240
1241 if (ios.timing == MMC_TIMING_UHS_SDR50 &&
1242 host->flags & SDHCI_SDR50_NEEDS_TUNING) {
1243 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
1244 config &= ~CORE_HC_SELECT_IN_MASK;
1245 config |= CORE_HC_SELECT_IN_EN | CORE_HC_SELECT_IN_SDR50;
1246 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
1247 }
1248
1249 /*
1250 * For HS400 tuning in HS200 timing requires:
1251 * - select MCLK/2 in VENDOR_SPEC
1252 * - program MCLK to 400MHz (or nearest supported) in GCC
1253 */
1254 if (host->flags & SDHCI_HS400_TUNING) {
1255 sdhci_msm_hc_select_mode(host);
1256 msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing);
1257 host->flags &= ~SDHCI_HS400_TUNING;
1258 }
1259
1260 retry:
1261 /* First of all reset the tuning block */
1262 rc = msm_init_cm_dll(host);
1263 if (rc)
1264 return rc;
1265
1266 phase = 0;
1267 do {
1268 /* Set the phase in delay line hw block */
1269 rc = msm_config_cm_dll_phase(host, phase);
1270 if (rc)
1271 return rc;
1272
1273 rc = mmc_send_tuning(mmc, opcode, NULL);
1274 if (!rc) {
1275 /* Tuning is successful at this tuning point */
1276 tuned_phases[tuned_phase_cnt++] = phase;
1277 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1278 mmc_hostname(mmc), phase);
1279 }
1280 } while (++phase < ARRAY_SIZE(tuned_phases));
1281
1282 if (tuned_phase_cnt) {
1283 if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
1284 /*
1285 * All phases valid is _almost_ as bad as no phases
1286 * valid. Probably all phases are not really reliable
1287 * but we didn't detect where the unreliable place is.
1288 * That means we'll essentially be guessing and hoping
1289 * we get a good phase. Better to try a few times.
1290 */
1291 dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
1292 mmc_hostname(mmc));
1293 if (--tuning_seq_cnt) {
1294 tuned_phase_cnt = 0;
1295 goto retry;
1296 }
1297 }
1298
1299 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1300 tuned_phase_cnt);
1301 if (rc < 0)
1302 return rc;
1303 else
1304 phase = rc;
1305
1306 /*
1307 * Finally set the selected phase in delay
1308 * line hw block.
1309 */
1310 rc = msm_config_cm_dll_phase(host, phase);
1311 if (rc)
1312 return rc;
1313 msm_host->saved_tuning_phase = phase;
1314 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1315 mmc_hostname(mmc), phase);
1316 } else {
1317 if (--tuning_seq_cnt)
1318 goto retry;
1319 /* Tuning failed */
1320 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1321 mmc_hostname(mmc));
1322 rc = -EIO;
1323 }
1324
1325 if (!rc)
1326 msm_host->tuning_done = true;
1327 return rc;
1328 }
1329
1330 /*
1331 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1332 * This needs to be done for both tuning and enhanced_strobe mode.
1333 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1334 * fixed feedback clock is used.
1335 */
sdhci_msm_hs400(struct sdhci_host * host,struct mmc_ios * ios)1336 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1337 {
1338 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1339 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1340 int ret;
1341
1342 if (host->clock > CORE_FREQ_100MHZ &&
1343 (msm_host->tuning_done || ios->enhanced_strobe) &&
1344 !msm_host->calibration_done) {
1345 ret = sdhci_msm_hs400_dll_calibration(host);
1346 if (!ret)
1347 msm_host->calibration_done = true;
1348 else
1349 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1350 mmc_hostname(host->mmc), ret);
1351 }
1352 }
1353
sdhci_msm_set_uhs_signaling(struct sdhci_host * host,unsigned int uhs)1354 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1355 unsigned int uhs)
1356 {
1357 struct mmc_host *mmc = host->mmc;
1358 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1359 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1360 u16 ctrl_2;
1361 u32 config;
1362 const struct sdhci_msm_offset *msm_offset =
1363 msm_host->offset;
1364
1365 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1366 /* Select Bus Speed Mode for host */
1367 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1368 switch (uhs) {
1369 case MMC_TIMING_UHS_SDR12:
1370 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1371 break;
1372 case MMC_TIMING_UHS_SDR25:
1373 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1374 break;
1375 case MMC_TIMING_UHS_SDR50:
1376 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1377 break;
1378 case MMC_TIMING_MMC_HS400:
1379 case MMC_TIMING_MMC_HS200:
1380 case MMC_TIMING_UHS_SDR104:
1381 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1382 break;
1383 case MMC_TIMING_UHS_DDR50:
1384 case MMC_TIMING_MMC_DDR52:
1385 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1386 break;
1387 }
1388
1389 /*
1390 * When clock frequency is less than 100MHz, the feedback clock must be
1391 * provided and DLL must not be used so that tuning can be skipped. To
1392 * provide feedback clock, the mode selection can be any value less
1393 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1394 */
1395 if (host->clock <= CORE_FREQ_100MHZ) {
1396 if (uhs == MMC_TIMING_MMC_HS400 ||
1397 uhs == MMC_TIMING_MMC_HS200 ||
1398 uhs == MMC_TIMING_UHS_SDR104)
1399 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1400 /*
1401 * DLL is not required for clock <= 100MHz
1402 * Thus, make sure DLL it is disabled when not required
1403 */
1404 config = readl_relaxed(host->ioaddr +
1405 msm_offset->core_dll_config);
1406 config |= CORE_DLL_RST;
1407 writel_relaxed(config, host->ioaddr +
1408 msm_offset->core_dll_config);
1409
1410 config = readl_relaxed(host->ioaddr +
1411 msm_offset->core_dll_config);
1412 config |= CORE_DLL_PDN;
1413 writel_relaxed(config, host->ioaddr +
1414 msm_offset->core_dll_config);
1415
1416 /*
1417 * The DLL needs to be restored and CDCLP533 recalibrated
1418 * when the clock frequency is set back to 400MHz.
1419 */
1420 msm_host->calibration_done = false;
1421 }
1422
1423 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1424 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1425 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1426
1427 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1428 sdhci_msm_hs400(host, &mmc->ios);
1429 }
1430
sdhci_msm_set_pincfg(struct sdhci_msm_host * msm_host,bool level)1431 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1432 {
1433 struct platform_device *pdev = msm_host->pdev;
1434 int ret;
1435
1436 if (level)
1437 ret = pinctrl_pm_select_default_state(&pdev->dev);
1438 else
1439 ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1440
1441 return ret;
1442 }
1443
msm_config_vmmc_regulator(struct mmc_host * mmc,bool hpm)1444 static void msm_config_vmmc_regulator(struct mmc_host *mmc, bool hpm)
1445 {
1446 int load;
1447
1448 if (!hpm)
1449 load = 0;
1450 else if (!mmc->card)
1451 load = max(MMC_VMMC_MAX_LOAD_UA, SD_VMMC_MAX_LOAD_UA);
1452 else if (mmc_card_mmc(mmc->card))
1453 load = MMC_VMMC_MAX_LOAD_UA;
1454 else if (mmc_card_sd(mmc->card))
1455 load = SD_VMMC_MAX_LOAD_UA;
1456 else
1457 return;
1458
1459 regulator_set_load(mmc->supply.vmmc, load);
1460 }
1461
msm_config_vqmmc_regulator(struct mmc_host * mmc,bool hpm)1462 static void msm_config_vqmmc_regulator(struct mmc_host *mmc, bool hpm)
1463 {
1464 int load;
1465
1466 if (!hpm)
1467 load = 0;
1468 else if (!mmc->card)
1469 load = max(MMC_VQMMC_MAX_LOAD_UA, SD_VQMMC_MAX_LOAD_UA);
1470 else if (mmc_card_sd(mmc->card))
1471 load = SD_VQMMC_MAX_LOAD_UA;
1472 else
1473 return;
1474
1475 regulator_set_load(mmc->supply.vqmmc, load);
1476 }
1477
sdhci_msm_set_vmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool hpm)1478 static int sdhci_msm_set_vmmc(struct sdhci_msm_host *msm_host,
1479 struct mmc_host *mmc, bool hpm)
1480 {
1481 if (IS_ERR(mmc->supply.vmmc))
1482 return 0;
1483
1484 msm_config_vmmc_regulator(mmc, hpm);
1485
1486 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
1487 }
1488
msm_toggle_vqmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool level)1489 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1490 struct mmc_host *mmc, bool level)
1491 {
1492 int ret;
1493 struct mmc_ios ios;
1494
1495 if (msm_host->vqmmc_enabled == level)
1496 return 0;
1497
1498 msm_config_vqmmc_regulator(mmc, level);
1499
1500 if (level) {
1501 /* Set the IO voltage regulator to default voltage level */
1502 if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1503 ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
1504 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1505 ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
1506
1507 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1508 ret = mmc_regulator_set_vqmmc(mmc, &ios);
1509 if (ret < 0) {
1510 dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
1511 mmc_hostname(mmc), ret);
1512 goto out;
1513 }
1514 }
1515 ret = regulator_enable(mmc->supply.vqmmc);
1516 } else {
1517 ret = regulator_disable(mmc->supply.vqmmc);
1518 }
1519
1520 if (ret)
1521 dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
1522 mmc_hostname(mmc), level ? "en":"dis", ret);
1523 else
1524 msm_host->vqmmc_enabled = level;
1525 out:
1526 return ret;
1527 }
1528
msm_config_vqmmc_mode(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool hpm)1529 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1530 struct mmc_host *mmc, bool hpm)
1531 {
1532 int load, ret;
1533
1534 load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
1535 ret = regulator_set_load(mmc->supply.vqmmc, load);
1536 if (ret)
1537 dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
1538 mmc_hostname(mmc), ret);
1539 return ret;
1540 }
1541
sdhci_msm_set_vqmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool level)1542 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1543 struct mmc_host *mmc, bool level)
1544 {
1545 int ret;
1546 bool always_on;
1547
1548 if (IS_ERR(mmc->supply.vqmmc) ||
1549 (mmc->ios.power_mode == MMC_POWER_UNDEFINED))
1550 return 0;
1551 /*
1552 * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
1553 * and HPM modes by setting the corresponding load.
1554 *
1555 * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
1556 * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
1557 * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
1558 * Vqmmc should remain ON, So just set the load instead of turning it
1559 * off/on.
1560 */
1561 always_on = !mmc_card_is_removable(mmc) &&
1562 mmc->card && mmc_card_mmc(mmc->card);
1563
1564 if (always_on)
1565 ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1566 else
1567 ret = msm_toggle_vqmmc(msm_host, mmc, level);
1568
1569 return ret;
1570 }
1571
sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host * msm_host)1572 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1573 {
1574 init_waitqueue_head(&msm_host->pwr_irq_wait);
1575 }
1576
sdhci_msm_complete_pwr_irq_wait(struct sdhci_msm_host * msm_host)1577 static inline void sdhci_msm_complete_pwr_irq_wait(
1578 struct sdhci_msm_host *msm_host)
1579 {
1580 wake_up(&msm_host->pwr_irq_wait);
1581 }
1582
1583 /*
1584 * sdhci_msm_check_power_status API should be called when registers writes
1585 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1586 * To what state the register writes will change the IO lines should be passed
1587 * as the argument req_type. This API will check whether the IO line's state
1588 * is already the expected state and will wait for power irq only if
1589 * power irq is expected to be triggered based on the current IO line state
1590 * and expected IO line state.
1591 */
sdhci_msm_check_power_status(struct sdhci_host * host,u32 req_type)1592 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1593 {
1594 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1595 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1596 struct mmc_host *mmc = host->mmc;
1597 bool done = false;
1598 u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1599 const struct sdhci_msm_offset *msm_offset =
1600 msm_host->offset;
1601
1602 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1603 mmc_hostname(host->mmc), __func__, req_type,
1604 msm_host->curr_pwr_state, msm_host->curr_io_level);
1605
1606 /*
1607 * The power interrupt will not be generated for signal voltage
1608 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1609 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1610 * it as always set.
1611 */
1612 if (!msm_host->mci_removed)
1613 val = msm_host_readl(msm_host, host,
1614 msm_offset->core_generics);
1615 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1616 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1617 return;
1618 }
1619
1620 /*
1621 * The IRQ for request type IO High/LOW will be generated when -
1622 * there is a state change in 1.8V enable bit (bit 3) of
1623 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1624 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1625 * to set it to 3.3V before card detection happens, the
1626 * IRQ doesn't get triggered as there is no state change in this bit.
1627 * The driver already handles this case by changing the IO voltage
1628 * level to high as part of controller power up sequence. Hence, check
1629 * for host->pwr to handle a case where IO voltage high request is
1630 * issued even before controller power up.
1631 */
1632 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1633 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1634 mmc_hostname(host->mmc), req_type);
1635 return;
1636 }
1637 if ((req_type & msm_host->curr_pwr_state) ||
1638 (req_type & msm_host->curr_io_level))
1639 done = true;
1640 /*
1641 * This is needed here to handle cases where register writes will
1642 * not change the current bus state or io level of the controller.
1643 * In this case, no power irq will be triggerred and we should
1644 * not wait.
1645 */
1646 if (!done) {
1647 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1648 msm_host->pwr_irq_flag,
1649 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1650 dev_warn(&msm_host->pdev->dev,
1651 "%s: pwr_irq for req: (%d) timed out\n",
1652 mmc_hostname(host->mmc), req_type);
1653 }
1654
1655 if ((req_type & REQ_BUS_ON) && mmc->card && !mmc->ops->get_cd(mmc)) {
1656 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1657 host->pwr = 0;
1658 }
1659
1660 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1661 __func__, req_type);
1662 }
1663
sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host * host)1664 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1665 {
1666 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1667 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1668 const struct sdhci_msm_offset *msm_offset =
1669 msm_host->offset;
1670
1671 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1672 mmc_hostname(host->mmc),
1673 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1674 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1675 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1676 }
1677
sdhci_msm_handle_pwr_irq(struct sdhci_host * host,int irq)1678 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1679 {
1680 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1681 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1682 struct mmc_host *mmc = host->mmc;
1683 u32 irq_status, irq_ack = 0;
1684 int retry = 10, ret;
1685 u32 pwr_state = 0, io_level = 0;
1686 u32 config;
1687 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1688
1689 irq_status = msm_host_readl(msm_host, host,
1690 msm_offset->core_pwrctl_status);
1691 irq_status &= INT_MASK;
1692
1693 msm_host_writel(msm_host, irq_status, host,
1694 msm_offset->core_pwrctl_clear);
1695
1696 /*
1697 * There is a rare HW scenario where the first clear pulse could be
1698 * lost when actual reset and clear/read of status register is
1699 * happening at a time. Hence, retry for at least 10 times to make
1700 * sure status register is cleared. Otherwise, this will result in
1701 * a spurious power IRQ resulting in system instability.
1702 */
1703 while (irq_status & msm_host_readl(msm_host, host,
1704 msm_offset->core_pwrctl_status)) {
1705 if (retry == 0) {
1706 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1707 mmc_hostname(host->mmc), irq_status);
1708 sdhci_msm_dump_pwr_ctrl_regs(host);
1709 WARN_ON(1);
1710 break;
1711 }
1712 msm_host_writel(msm_host, irq_status, host,
1713 msm_offset->core_pwrctl_clear);
1714 retry--;
1715 udelay(10);
1716 }
1717
1718 if ((irq_status & CORE_PWRCTL_BUS_ON) && mmc->card &&
1719 !mmc->ops->get_cd(mmc)) {
1720 msm_host_writel(msm_host, CORE_PWRCTL_BUS_FAIL, host,
1721 msm_offset->core_pwrctl_ctl);
1722 return;
1723 }
1724
1725 /* Handle BUS ON/OFF*/
1726 if (irq_status & CORE_PWRCTL_BUS_ON) {
1727 pwr_state = REQ_BUS_ON;
1728 io_level = REQ_IO_HIGH;
1729 }
1730 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1731 pwr_state = REQ_BUS_OFF;
1732 io_level = REQ_IO_LOW;
1733 }
1734
1735 if (pwr_state) {
1736 ret = sdhci_msm_set_vmmc(msm_host, mmc,
1737 pwr_state & REQ_BUS_ON);
1738 if (!ret)
1739 ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1740 pwr_state & REQ_BUS_ON);
1741 if (!ret)
1742 ret = sdhci_msm_set_pincfg(msm_host,
1743 pwr_state & REQ_BUS_ON);
1744 if (!ret)
1745 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1746 else
1747 irq_ack |= CORE_PWRCTL_BUS_FAIL;
1748 }
1749
1750 /* Handle IO LOW/HIGH */
1751 if (irq_status & CORE_PWRCTL_IO_LOW)
1752 io_level = REQ_IO_LOW;
1753
1754 if (irq_status & CORE_PWRCTL_IO_HIGH)
1755 io_level = REQ_IO_HIGH;
1756
1757 if (io_level)
1758 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1759
1760 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
1761 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
1762 if (ret < 0) {
1763 dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
1764 mmc_hostname(mmc), ret,
1765 mmc->ios.signal_voltage, mmc->ios.vdd,
1766 irq_status);
1767 irq_ack |= CORE_PWRCTL_IO_FAIL;
1768 }
1769 }
1770
1771 /*
1772 * The driver has to acknowledge the interrupt, switch voltages and
1773 * report back if it succeded or not to this register. The voltage
1774 * switches are handled by the sdhci core, so just report success.
1775 */
1776 msm_host_writel(msm_host, irq_ack, host,
1777 msm_offset->core_pwrctl_ctl);
1778
1779 /*
1780 * If we don't have info regarding the voltage levels supported by
1781 * regulators, don't change the IO PAD PWR SWITCH.
1782 */
1783 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1784 u32 new_config;
1785 /*
1786 * We should unset IO PAD PWR switch only if the register write
1787 * can set IO lines high and the regulator also switches to 3 V.
1788 * Else, we should keep the IO PAD PWR switch set.
1789 * This is applicable to certain targets where eMMC vccq supply
1790 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1791 * IO PAD PWR switch must be kept set to reflect actual
1792 * regulator voltage. This way, during initialization of
1793 * controllers with only 1.8V, we will set the IO PAD bit
1794 * without waiting for a REQ_IO_LOW.
1795 */
1796 config = readl_relaxed(host->ioaddr +
1797 msm_offset->core_vendor_spec);
1798 new_config = config;
1799
1800 if ((io_level & REQ_IO_HIGH) &&
1801 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1802 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1803 else if ((io_level & REQ_IO_LOW) ||
1804 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1805 new_config |= CORE_IO_PAD_PWR_SWITCH;
1806
1807 if (config ^ new_config)
1808 writel_relaxed(new_config, host->ioaddr +
1809 msm_offset->core_vendor_spec);
1810 }
1811
1812 if (pwr_state)
1813 msm_host->curr_pwr_state = pwr_state;
1814 if (io_level)
1815 msm_host->curr_io_level = io_level;
1816
1817 dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1818 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1819 irq_ack);
1820 }
1821
sdhci_msm_pwr_irq(int irq,void * data)1822 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1823 {
1824 struct sdhci_host *host = (struct sdhci_host *)data;
1825 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1826 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1827
1828 sdhci_msm_handle_pwr_irq(host, irq);
1829 msm_host->pwr_irq_flag = 1;
1830 sdhci_msm_complete_pwr_irq_wait(msm_host);
1831
1832
1833 return IRQ_HANDLED;
1834 }
1835
sdhci_msm_get_max_clock(struct sdhci_host * host)1836 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1837 {
1838 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1839 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1840 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1841
1842 return clk_round_rate(core_clk, ULONG_MAX);
1843 }
1844
sdhci_msm_get_min_clock(struct sdhci_host * host)1845 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1846 {
1847 return SDHCI_MSM_MIN_CLOCK;
1848 }
1849
1850 /*
1851 * __sdhci_msm_set_clock - sdhci_msm clock control.
1852 *
1853 * Description:
1854 * MSM controller does not use internal divider and
1855 * instead directly control the GCC clock as per
1856 * HW recommendation.
1857 **/
__sdhci_msm_set_clock(struct sdhci_host * host,unsigned int clock)1858 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1859 {
1860 u16 clk;
1861
1862 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1863
1864 if (clock == 0)
1865 return;
1866
1867 /*
1868 * MSM controller do not use clock divider.
1869 * Thus read SDHCI_CLOCK_CONTROL and only enable
1870 * clock with no divider value programmed.
1871 */
1872 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1873 sdhci_enable_clk(host, clk);
1874 }
1875
1876 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
sdhci_msm_set_clock(struct sdhci_host * host,unsigned int clock)1877 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1878 {
1879 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1880 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1881 struct mmc_ios ios = host->mmc->ios;
1882
1883 if (!clock) {
1884 host->mmc->actual_clock = msm_host->clk_rate = 0;
1885 goto out;
1886 }
1887
1888 sdhci_msm_hc_select_mode(host);
1889
1890 msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing);
1891 out:
1892 __sdhci_msm_set_clock(host, clock);
1893 }
1894
1895 /*****************************************************************************\
1896 * *
1897 * Inline Crypto Engine (ICE) support *
1898 * *
1899 \*****************************************************************************/
1900
1901 #ifdef CONFIG_MMC_CRYPTO
1902
1903 static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
1904
sdhci_msm_ice_init(struct sdhci_msm_host * msm_host,struct cqhci_host * cq_host)1905 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1906 struct cqhci_host *cq_host)
1907 {
1908 struct mmc_host *mmc = msm_host->mmc;
1909 struct blk_crypto_profile *profile = &mmc->crypto_profile;
1910 struct device *dev = mmc_dev(mmc);
1911 struct qcom_ice *ice;
1912 union cqhci_crypto_capabilities caps;
1913 union cqhci_crypto_cap_entry cap;
1914 int err;
1915 int i;
1916
1917 if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
1918 return 0;
1919
1920 ice = devm_of_qcom_ice_get(dev);
1921 if (IS_ERR(ice)) {
1922 if (ice != ERR_PTR(-EOPNOTSUPP))
1923 return PTR_ERR(ice);
1924
1925 dev_warn(dev, "Disabling inline encryption support\n");
1926 return 0;
1927 }
1928
1929 msm_host->ice = ice;
1930
1931 /* Initialize the blk_crypto_profile */
1932
1933 caps.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
1934
1935 /* The number of keyslots supported is (CFGC+1) */
1936 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1);
1937 if (err)
1938 return err;
1939
1940 profile->ll_ops = sdhci_msm_crypto_ops;
1941 profile->max_dun_bytes_supported = 4;
1942 profile->key_types_supported = qcom_ice_get_supported_key_type(ice);
1943 profile->dev = dev;
1944
1945 /*
1946 * Currently this driver only supports AES-256-XTS. All known versions
1947 * of ICE support it, but to be safe make sure it is really declared in
1948 * the crypto capability registers. The crypto capability registers
1949 * also give the supported data unit size(s).
1950 */
1951 for (i = 0; i < caps.num_crypto_cap; i++) {
1952 cap.reg_val = cpu_to_le32(cqhci_readl(cq_host,
1953 CQHCI_CRYPTOCAP +
1954 i * sizeof(__le32)));
1955 if (cap.algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS &&
1956 cap.key_size == CQHCI_CRYPTO_KEY_SIZE_256)
1957 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |=
1958 cap.sdus_mask * 512;
1959 }
1960
1961 mmc->caps2 |= MMC_CAP2_CRYPTO;
1962 return 0;
1963 }
1964
sdhci_msm_ice_enable(struct sdhci_msm_host * msm_host)1965 static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1966 {
1967 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1968 qcom_ice_enable(msm_host->ice);
1969 }
1970
sdhci_msm_ice_resume(struct sdhci_msm_host * msm_host)1971 static int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1972 {
1973 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1974 return qcom_ice_resume(msm_host->ice);
1975
1976 return 0;
1977 }
1978
sdhci_msm_ice_suspend(struct sdhci_msm_host * msm_host)1979 static int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
1980 {
1981 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1982 return qcom_ice_suspend(msm_host->ice);
1983
1984 return 0;
1985 }
1986
1987 static inline struct sdhci_msm_host *
sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile * profile)1988 sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile)
1989 {
1990 struct mmc_host *mmc = mmc_from_crypto_profile(profile);
1991 struct sdhci_host *host = mmc_priv(mmc);
1992 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1993 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1994
1995 return msm_host;
1996 }
1997
1998 /*
1999 * Program a key into a QC ICE keyslot. QC ICE requires a QC-specific SCM call
2000 * for this; it doesn't support the standard way.
2001 */
sdhci_msm_ice_keyslot_program(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)2002 static int sdhci_msm_ice_keyslot_program(struct blk_crypto_profile *profile,
2003 const struct blk_crypto_key *key,
2004 unsigned int slot)
2005 {
2006 struct sdhci_msm_host *msm_host =
2007 sdhci_msm_host_from_crypto_profile(profile);
2008
2009 return qcom_ice_program_key(msm_host->ice, slot, key);
2010 }
2011
sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)2012 static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile *profile,
2013 const struct blk_crypto_key *key,
2014 unsigned int slot)
2015 {
2016 struct sdhci_msm_host *msm_host =
2017 sdhci_msm_host_from_crypto_profile(profile);
2018
2019 return qcom_ice_evict_key(msm_host->ice, slot);
2020 }
2021
sdhci_msm_ice_derive_sw_secret(struct blk_crypto_profile * profile,const u8 * eph_key,size_t eph_key_size,u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE])2022 static int sdhci_msm_ice_derive_sw_secret(struct blk_crypto_profile *profile,
2023 const u8 *eph_key, size_t eph_key_size,
2024 u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE])
2025 {
2026 struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile);
2027
2028 return qcom_ice_derive_sw_secret(msm_host->ice, eph_key, eph_key_size,
2029 sw_secret);
2030 }
2031
sdhci_msm_ice_import_key(struct blk_crypto_profile * profile,const u8 * raw_key,size_t raw_key_size,u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])2032 static int sdhci_msm_ice_import_key(struct blk_crypto_profile *profile,
2033 const u8 *raw_key, size_t raw_key_size,
2034 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])
2035 {
2036 struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile);
2037
2038 return qcom_ice_import_key(msm_host->ice, raw_key, raw_key_size, lt_key);
2039 }
2040
sdhci_msm_ice_generate_key(struct blk_crypto_profile * profile,u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])2041 static int sdhci_msm_ice_generate_key(struct blk_crypto_profile *profile,
2042 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])
2043 {
2044 struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile);
2045
2046 return qcom_ice_generate_key(msm_host->ice, lt_key);
2047 }
2048
sdhci_msm_ice_prepare_key(struct blk_crypto_profile * profile,const u8 * lt_key,size_t lt_key_size,u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])2049 static int sdhci_msm_ice_prepare_key(struct blk_crypto_profile *profile,
2050 const u8 *lt_key, size_t lt_key_size,
2051 u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])
2052 {
2053 struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile);
2054
2055 return qcom_ice_prepare_key(msm_host->ice, lt_key, lt_key_size, eph_key);
2056 }
2057
sdhci_msm_non_cqe_ice_init(struct sdhci_host * host)2058 static void sdhci_msm_non_cqe_ice_init(struct sdhci_host *host)
2059 {
2060 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2061 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2062 struct mmc_host *mmc = msm_host->mmc;
2063 struct cqhci_host *cq_host = mmc->cqe_private;
2064 u32 config;
2065
2066 config = sdhci_readl(host, HC_VENDOR_SPECIFIC_FUNC4);
2067 config &= ~DISABLE_CRYPTO;
2068 sdhci_writel(host, config, HC_VENDOR_SPECIFIC_FUNC4);
2069 config = cqhci_readl(cq_host, CQHCI_CFG);
2070 config |= CRYPTO_GENERAL_ENABLE;
2071 cqhci_writel(cq_host, config, CQHCI_CFG);
2072 }
2073
sdhci_msm_ice_cfg(struct sdhci_host * host,struct mmc_request * mrq)2074 static void sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq)
2075 {
2076 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2077 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2078 struct mmc_host *mmc = msm_host->mmc;
2079 struct cqhci_host *cq_host = mmc->cqe_private;
2080 unsigned int crypto_params = 0;
2081 int key_index;
2082
2083 if (mrq->crypto_ctx) {
2084 if (!msm_host->non_cqe_ice_init_done) {
2085 sdhci_msm_non_cqe_ice_init(host);
2086 msm_host->non_cqe_ice_init_done = true;
2087 }
2088
2089 key_index = mrq->crypto_key_slot;
2090 crypto_params = FIELD_PREP(ICE_HCI_PARAM_CE, 1) |
2091 FIELD_PREP(ICE_HCI_PARAM_CCI, key_index);
2092
2093 cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM);
2094 cqhci_writel(cq_host, lower_32_bits(mrq->crypto_ctx->bc_dun[0]),
2095 NONCQ_CRYPTO_DUN);
2096 } else {
2097 cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM);
2098 }
2099
2100 /* Ensure crypto configuration is written before proceeding */
2101 wmb();
2102 }
2103
2104 /*
2105 * Handle non-CQE MMC requests with ICE crypto support.
2106 * Configures ICE registers before passing the request to
2107 * the standard SDHCI handler.
2108 */
sdhci_msm_request(struct mmc_host * mmc,struct mmc_request * mrq)2109 static void sdhci_msm_request(struct mmc_host *mmc, struct mmc_request *mrq)
2110 {
2111 struct sdhci_host *host = mmc_priv(mmc);
2112
2113 /* Only need to handle non-CQE crypto requests in this path */
2114 if (mmc->caps2 & MMC_CAP2_CRYPTO)
2115 sdhci_msm_ice_cfg(host, mrq);
2116
2117 sdhci_request(mmc, mrq);
2118 }
2119
2120 static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops = {
2121 .keyslot_program = sdhci_msm_ice_keyslot_program,
2122 .keyslot_evict = sdhci_msm_ice_keyslot_evict,
2123 .derive_sw_secret = sdhci_msm_ice_derive_sw_secret,
2124 .import_key = sdhci_msm_ice_import_key,
2125 .generate_key = sdhci_msm_ice_generate_key,
2126 .prepare_key = sdhci_msm_ice_prepare_key,
2127 };
2128
2129 #else /* CONFIG_MMC_CRYPTO */
2130
sdhci_msm_ice_init(struct sdhci_msm_host * msm_host,struct cqhci_host * cq_host)2131 static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
2132 struct cqhci_host *cq_host)
2133 {
2134 return 0;
2135 }
2136
sdhci_msm_ice_enable(struct sdhci_msm_host * msm_host)2137 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
2138 {
2139 }
2140
2141 static inline int
sdhci_msm_ice_resume(struct sdhci_msm_host * msm_host)2142 sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
2143 {
2144 return 0;
2145 }
2146
2147 static inline int
sdhci_msm_ice_suspend(struct sdhci_msm_host * msm_host)2148 sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
2149 {
2150 return 0;
2151 }
2152 #endif /* !CONFIG_MMC_CRYPTO */
2153
2154 /*****************************************************************************\
2155 * *
2156 * MSM Command Queue Engine (CQE) *
2157 * *
2158 \*****************************************************************************/
2159
sdhci_msm_cqe_irq(struct sdhci_host * host,u32 intmask)2160 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
2161 {
2162 int cmd_error = 0;
2163 int data_error = 0;
2164
2165 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
2166 return intmask;
2167
2168 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
2169 return 0;
2170 }
2171
sdhci_msm_cqe_enable(struct mmc_host * mmc)2172 static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
2173 {
2174 struct sdhci_host *host = mmc_priv(mmc);
2175 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2176 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2177
2178 sdhci_cqe_enable(mmc);
2179 sdhci_msm_ice_enable(msm_host);
2180 }
2181
sdhci_msm_cqe_disable(struct mmc_host * mmc,bool recovery)2182 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
2183 {
2184 struct sdhci_host *host = mmc_priv(mmc);
2185 unsigned long flags;
2186 u32 ctrl;
2187
2188 /*
2189 * When CQE is halted, the legacy SDHCI path operates only
2190 * on 16-byte descriptors in 64bit mode.
2191 */
2192 if (host->flags & SDHCI_USE_64_BIT_DMA)
2193 host->desc_sz = 16;
2194
2195 spin_lock_irqsave(&host->lock, flags);
2196
2197 /*
2198 * During CQE command transfers, command complete bit gets latched.
2199 * So s/w should clear command complete interrupt status when CQE is
2200 * either halted or disabled. Otherwise unexpected SDCHI legacy
2201 * interrupt gets triggered when CQE is halted/disabled.
2202 */
2203 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
2204 ctrl |= SDHCI_INT_RESPONSE;
2205 sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
2206 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
2207
2208 spin_unlock_irqrestore(&host->lock, flags);
2209
2210 sdhci_cqe_disable(mmc, recovery);
2211 }
2212
sdhci_msm_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)2213 static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
2214 {
2215 u32 count, start = 15;
2216
2217 __sdhci_set_timeout(host, cmd);
2218 count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
2219 /*
2220 * Update software timeout value if its value is less than hardware data
2221 * timeout value. Qcom SoC hardware data timeout value was calculated
2222 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
2223 */
2224 if (cmd && cmd->data && host->clock > 400000 &&
2225 host->clock <= 50000000 &&
2226 ((1 << (count + start)) > (10 * host->clock)))
2227 host->data_timeout = 22LL * NSEC_PER_SEC;
2228 }
2229
2230 static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
2231 .enable = sdhci_msm_cqe_enable,
2232 .disable = sdhci_msm_cqe_disable,
2233 #ifdef CONFIG_MMC_CRYPTO
2234 .uses_custom_crypto_profile = true,
2235 #endif
2236 };
2237
sdhci_msm_cqe_add_host(struct sdhci_host * host,struct platform_device * pdev)2238 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
2239 struct platform_device *pdev)
2240 {
2241 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2242 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2243 struct cqhci_host *cq_host;
2244 bool dma64;
2245 u32 cqcfg;
2246 int ret;
2247
2248 /*
2249 * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
2250 * So ensure ADMA table is allocated for 16byte descriptors.
2251 */
2252 if (host->caps & SDHCI_CAN_64BIT)
2253 host->alloc_desc_sz = 16;
2254
2255 ret = sdhci_setup_host(host);
2256 if (ret)
2257 return ret;
2258
2259 cq_host = cqhci_pltfm_init(pdev);
2260 if (IS_ERR(cq_host)) {
2261 ret = PTR_ERR(cq_host);
2262 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
2263 goto cleanup;
2264 }
2265
2266 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2267 cq_host->ops = &sdhci_msm_cqhci_ops;
2268
2269 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
2270
2271 ret = sdhci_msm_ice_init(msm_host, cq_host);
2272 if (ret)
2273 goto cleanup;
2274
2275 ret = cqhci_init(cq_host, host->mmc, dma64);
2276 if (ret) {
2277 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
2278 mmc_hostname(host->mmc), ret);
2279 goto cleanup;
2280 }
2281
2282 /* Disable cqe reset due to cqe enable signal */
2283 cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
2284 cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
2285 cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
2286
2287 /*
2288 * SDHC expects 12byte ADMA descriptors till CQE is enabled.
2289 * So limit desc_sz to 12 so that the data commands that are sent
2290 * during card initialization (before CQE gets enabled) would
2291 * get executed without any issues.
2292 */
2293 if (host->flags & SDHCI_USE_64_BIT_DMA)
2294 host->desc_sz = 12;
2295
2296 ret = __sdhci_add_host(host);
2297 if (ret)
2298 goto cleanup;
2299
2300 dev_info(&pdev->dev, "%s: CQE init: success\n",
2301 mmc_hostname(host->mmc));
2302 return ret;
2303
2304 cleanup:
2305 sdhci_cleanup_host(host);
2306 return ret;
2307 }
2308
2309 /*
2310 * Platform specific register write functions. This is so that, if any
2311 * register write needs to be followed up by platform specific actions,
2312 * they can be added here. These functions can go to sleep when writes
2313 * to certain registers are done.
2314 * These functions are relying on sdhci_set_ios not using spinlock.
2315 */
__sdhci_msm_check_write(struct sdhci_host * host,u16 val,int reg)2316 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
2317 {
2318 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2319 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2320 u32 req_type = 0;
2321
2322 switch (reg) {
2323 case SDHCI_HOST_CONTROL2:
2324 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
2325 REQ_IO_HIGH;
2326 break;
2327 case SDHCI_SOFTWARE_RESET:
2328 if (host->pwr && (val & SDHCI_RESET_ALL))
2329 req_type = REQ_BUS_OFF;
2330 break;
2331 case SDHCI_POWER_CONTROL:
2332 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
2333 break;
2334 case SDHCI_TRANSFER_MODE:
2335 msm_host->transfer_mode = val;
2336 break;
2337 case SDHCI_COMMAND:
2338 if (!msm_host->use_cdr)
2339 break;
2340 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
2341 !mmc_op_tuning(SDHCI_GET_CMD(val)))
2342 sdhci_msm_set_cdr(host, true);
2343 else
2344 sdhci_msm_set_cdr(host, false);
2345 break;
2346 }
2347
2348 if (req_type) {
2349 msm_host->pwr_irq_flag = 0;
2350 /*
2351 * Since this register write may trigger a power irq, ensure
2352 * all previous register writes are complete by this point.
2353 */
2354 mb();
2355 }
2356 return req_type;
2357 }
2358
2359 /* This function may sleep*/
sdhci_msm_writew(struct sdhci_host * host,u16 val,int reg)2360 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
2361 {
2362 u32 req_type = 0;
2363
2364 req_type = __sdhci_msm_check_write(host, val, reg);
2365 writew_relaxed(val, host->ioaddr + reg);
2366
2367 if (req_type)
2368 sdhci_msm_check_power_status(host, req_type);
2369 }
2370
2371 /* This function may sleep*/
sdhci_msm_writeb(struct sdhci_host * host,u8 val,int reg)2372 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
2373 {
2374 u32 req_type = 0;
2375
2376 req_type = __sdhci_msm_check_write(host, val, reg);
2377
2378 writeb_relaxed(val, host->ioaddr + reg);
2379
2380 if (req_type)
2381 sdhci_msm_check_power_status(host, req_type);
2382 }
2383
sdhci_msm_set_regulator_caps(struct sdhci_msm_host * msm_host)2384 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2385 {
2386 struct mmc_host *mmc = msm_host->mmc;
2387 struct regulator *supply = mmc->supply.vqmmc;
2388 u32 caps = 0, config;
2389 struct sdhci_host *host = mmc_priv(mmc);
2390 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2391
2392 if (!IS_ERR(mmc->supply.vqmmc)) {
2393 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
2394 caps |= CORE_1_8V_SUPPORT;
2395 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
2396 caps |= CORE_3_0V_SUPPORT;
2397
2398 if (!caps)
2399 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2400 mmc_hostname(mmc));
2401 }
2402
2403 if (caps) {
2404 /*
2405 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
2406 * bit can be used as required later on.
2407 */
2408 u32 io_level = msm_host->curr_io_level;
2409
2410 config = readl_relaxed(host->ioaddr +
2411 msm_offset->core_vendor_spec);
2412 config |= CORE_IO_PAD_PWR_SWITCH_EN;
2413
2414 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
2415 config &= ~CORE_IO_PAD_PWR_SWITCH;
2416 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
2417 config |= CORE_IO_PAD_PWR_SWITCH;
2418
2419 writel_relaxed(config,
2420 host->ioaddr + msm_offset->core_vendor_spec);
2421 }
2422 msm_host->caps_0 |= caps;
2423 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
2424 }
2425
sdhci_msm_register_vreg(struct sdhci_msm_host * msm_host)2426 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2427 {
2428 int ret;
2429
2430 ret = mmc_regulator_get_supply(msm_host->mmc);
2431 if (ret)
2432 return ret;
2433
2434 sdhci_msm_set_regulator_caps(msm_host);
2435
2436 return 0;
2437 }
2438
sdhci_msm_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)2439 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
2440 struct mmc_ios *ios)
2441 {
2442 struct sdhci_host *host = mmc_priv(mmc);
2443 u16 ctrl, status;
2444
2445 /*
2446 * Signal Voltage Switching is only applicable for Host Controllers
2447 * v3.00 and above.
2448 */
2449 if (host->version < SDHCI_SPEC_300)
2450 return 0;
2451
2452 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2453
2454 switch (ios->signal_voltage) {
2455 case MMC_SIGNAL_VOLTAGE_330:
2456 if (!(host->flags & SDHCI_SIGNALING_330))
2457 return -EINVAL;
2458
2459 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2460 ctrl &= ~SDHCI_CTRL_VDD_180;
2461 break;
2462 case MMC_SIGNAL_VOLTAGE_180:
2463 if (!(host->flags & SDHCI_SIGNALING_180))
2464 return -EINVAL;
2465
2466 /* Enable 1.8V Signal Enable in the Host Control2 register */
2467 ctrl |= SDHCI_CTRL_VDD_180;
2468 break;
2469
2470 default:
2471 return -EINVAL;
2472 }
2473
2474 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2475
2476 /* Wait for 5ms */
2477 usleep_range(5000, 5500);
2478
2479 /* regulator output should be stable within 5 ms */
2480 status = ctrl & SDHCI_CTRL_VDD_180;
2481 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2482 if ((ctrl & SDHCI_CTRL_VDD_180) == status)
2483 return 0;
2484
2485 dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
2486 mmc_hostname(mmc));
2487
2488 return -EAGAIN;
2489 }
2490
2491 #define DRIVER_NAME "sdhci_msm"
2492 #define SDHCI_MSM_DUMP(f, x...) \
2493 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2494
sdhci_msm_dump_vendor_regs(struct sdhci_host * host)2495 static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2496 {
2497 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2498 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2499 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2500
2501 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
2502
2503 SDHCI_MSM_DUMP(
2504 "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
2505 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2506 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2507 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2508 SDHCI_MSM_DUMP(
2509 "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
2510 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2511 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2512 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2513 SDHCI_MSM_DUMP(
2514 "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
2515 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2516 readl_relaxed(host->ioaddr +
2517 msm_offset->core_vendor_spec_func2),
2518 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2519 }
2520
2521 static const struct sdhci_msm_variant_ops mci_var_ops = {
2522 .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
2523 .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
2524 };
2525
2526 static const struct sdhci_msm_variant_ops v5_var_ops = {
2527 .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
2528 .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
2529 };
2530
2531 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
2532 .var_ops = &mci_var_ops,
2533 .offset = &sdhci_msm_mci_offset,
2534 };
2535
2536 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
2537 .mci_removed = true,
2538 .var_ops = &v5_var_ops,
2539 .offset = &sdhci_msm_v5_offset,
2540 };
2541
2542 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
2543 .mci_removed = true,
2544 .restore_dll_config = true,
2545 .var_ops = &v5_var_ops,
2546 .offset = &sdhci_msm_v5_offset,
2547 };
2548
2549 static const struct of_device_id sdhci_msm_dt_match[] = {
2550 /*
2551 * Do not add new variants to the driver which are compatible with
2552 * generic ones, unless they need customization.
2553 */
2554 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2555 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2556 {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
2557 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2558 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2559 {},
2560 };
2561
2562 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
2563
2564 static const struct sdhci_ops sdhci_msm_ops = {
2565 .reset = sdhci_and_cqhci_reset,
2566 .set_clock = sdhci_msm_set_clock,
2567 .get_min_clock = sdhci_msm_get_min_clock,
2568 .get_max_clock = sdhci_msm_get_max_clock,
2569 .set_bus_width = sdhci_set_bus_width,
2570 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
2571 .write_w = sdhci_msm_writew,
2572 .write_b = sdhci_msm_writeb,
2573 .irq = sdhci_msm_cqe_irq,
2574 .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
2575 .set_power = sdhci_set_power_noreg,
2576 .set_timeout = sdhci_msm_set_timeout,
2577 };
2578
2579 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
2580 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2581 SDHCI_QUIRK_SINGLE_POWER_WRITE |
2582 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
2583 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
2584
2585 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2586 .ops = &sdhci_msm_ops,
2587 };
2588
sdhci_msm_get_of_property(struct platform_device * pdev,struct sdhci_host * host)2589 static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
2590 struct sdhci_host *host)
2591 {
2592 struct device_node *node = pdev->dev.of_node;
2593 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2594 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2595
2596 if (of_property_read_u32(node, "qcom,ddr-config",
2597 &msm_host->ddr_config))
2598 msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2599
2600 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2601
2602 if (of_device_is_compatible(node, "qcom,msm8916-sdhci"))
2603 host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;
2604 }
2605
sdhci_msm_gcc_reset(struct device * dev,struct sdhci_host * host)2606 static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
2607 {
2608 struct reset_control *reset;
2609 int ret = 0;
2610
2611 reset = reset_control_get_optional_exclusive(dev, NULL);
2612 if (IS_ERR(reset))
2613 return dev_err_probe(dev, PTR_ERR(reset),
2614 "unable to acquire core_reset\n");
2615
2616 if (!reset)
2617 return ret;
2618
2619 ret = reset_control_assert(reset);
2620 if (ret) {
2621 reset_control_put(reset);
2622 return dev_err_probe(dev, ret, "core_reset assert failed\n");
2623 }
2624
2625 /*
2626 * The hardware requirement for delay between assert/deassert
2627 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
2628 * ~125us (4/32768). To be on the safe side add 200us delay.
2629 */
2630 usleep_range(200, 210);
2631
2632 ret = reset_control_deassert(reset);
2633 if (ret) {
2634 reset_control_put(reset);
2635 return dev_err_probe(dev, ret, "core_reset deassert failed\n");
2636 }
2637
2638 usleep_range(200, 210);
2639 reset_control_put(reset);
2640
2641 return ret;
2642 }
2643
sdhci_msm_probe(struct platform_device * pdev)2644 static int sdhci_msm_probe(struct platform_device *pdev)
2645 {
2646 struct sdhci_host *host;
2647 struct sdhci_pltfm_host *pltfm_host;
2648 struct sdhci_msm_host *msm_host;
2649 struct clk *clk;
2650 int ret;
2651 u16 host_version, core_minor;
2652 u32 core_version, config;
2653 u8 core_major;
2654 const struct sdhci_msm_offset *msm_offset;
2655 const struct sdhci_msm_variant_info *var_info;
2656 struct device_node *node = pdev->dev.of_node;
2657
2658 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2659 if (IS_ERR(host))
2660 return PTR_ERR(host);
2661
2662 host->sdma_boundary = 0;
2663 pltfm_host = sdhci_priv(host);
2664 msm_host = sdhci_pltfm_priv(pltfm_host);
2665 msm_host->mmc = host->mmc;
2666 msm_host->pdev = pdev;
2667
2668 ret = mmc_of_parse(host->mmc);
2669 if (ret)
2670 return ret;
2671
2672 /*
2673 * Based on the compatible string, load the required msm host info from
2674 * the data associated with the version info.
2675 */
2676 var_info = of_device_get_match_data(&pdev->dev);
2677
2678 msm_host->mci_removed = var_info->mci_removed;
2679 msm_host->restore_dll_config = var_info->restore_dll_config;
2680 msm_host->var_ops = var_info->var_ops;
2681 msm_host->offset = var_info->offset;
2682
2683 msm_offset = msm_host->offset;
2684
2685 sdhci_get_of_property(pdev);
2686 sdhci_msm_get_of_property(pdev, host);
2687
2688 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2689
2690 ret = sdhci_msm_gcc_reset(&pdev->dev, host);
2691 if (ret)
2692 return ret;
2693
2694 /* Setup SDCC bus voter clock. */
2695 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2696 if (!IS_ERR(msm_host->bus_clk)) {
2697 /* Vote for max. clk rate for max. performance */
2698 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2699 if (ret)
2700 return ret;
2701 ret = clk_prepare_enable(msm_host->bus_clk);
2702 if (ret)
2703 return ret;
2704 }
2705
2706 /* Setup main peripheral bus clock */
2707 clk = devm_clk_get(&pdev->dev, "iface");
2708 if (IS_ERR(clk)) {
2709 ret = PTR_ERR(clk);
2710 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
2711 goto bus_clk_disable;
2712 }
2713 msm_host->bulk_clks[1].clk = clk;
2714
2715 /* Setup SDC MMC clock */
2716 clk = devm_clk_get(&pdev->dev, "core");
2717 if (IS_ERR(clk)) {
2718 ret = PTR_ERR(clk);
2719 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
2720 goto bus_clk_disable;
2721 }
2722 msm_host->bulk_clks[0].clk = clk;
2723
2724 /* Check for optional interconnect paths */
2725 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
2726 if (ret)
2727 goto bus_clk_disable;
2728
2729 ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
2730 if (ret)
2731 goto bus_clk_disable;
2732
2733 /* OPP table is optional */
2734 ret = devm_pm_opp_of_add_table(&pdev->dev);
2735 if (ret && ret != -ENODEV) {
2736 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
2737 goto bus_clk_disable;
2738 }
2739
2740 /* Vote for maximum clock rate for maximum performance */
2741 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
2742 if (ret)
2743 dev_warn(&pdev->dev, "core clock boost failed\n");
2744
2745 clk = devm_clk_get(&pdev->dev, "cal");
2746 if (IS_ERR(clk))
2747 clk = NULL;
2748 msm_host->bulk_clks[2].clk = clk;
2749
2750 clk = devm_clk_get(&pdev->dev, "sleep");
2751 if (IS_ERR(clk))
2752 clk = NULL;
2753 msm_host->bulk_clks[3].clk = clk;
2754
2755 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2756 msm_host->bulk_clks);
2757 if (ret)
2758 goto bus_clk_disable;
2759
2760 /*
2761 * xo clock is needed for FLL feature of cm_dll.
2762 * In case if xo clock is not mentioned in DT, warn and proceed.
2763 */
2764 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2765 if (IS_ERR(msm_host->xo_clk)) {
2766 ret = PTR_ERR(msm_host->xo_clk);
2767 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
2768 }
2769
2770 if (!msm_host->mci_removed) {
2771 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2772 if (IS_ERR(msm_host->core_mem)) {
2773 ret = PTR_ERR(msm_host->core_mem);
2774 goto clk_disable;
2775 }
2776 }
2777
2778 /* Reset the vendor spec register to power on reset state */
2779 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2780 host->ioaddr + msm_offset->core_vendor_spec);
2781
2782 if (!msm_host->mci_removed) {
2783 /* Set HC_MODE_EN bit in HC_MODE register */
2784 msm_host_writel(msm_host, HC_MODE_EN, host,
2785 msm_offset->core_hc_mode);
2786 config = msm_host_readl(msm_host, host,
2787 msm_offset->core_hc_mode);
2788 config |= FF_CLK_SW_RST_DIS;
2789 msm_host_writel(msm_host, config, host,
2790 msm_offset->core_hc_mode);
2791 }
2792
2793 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2794 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
2795 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
2796 SDHCI_VENDOR_VER_SHIFT));
2797
2798 core_version = msm_host_readl(msm_host, host,
2799 msm_offset->core_mci_version);
2800 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
2801 CORE_VERSION_MAJOR_SHIFT;
2802 core_minor = core_version & CORE_VERSION_MINOR_MASK;
2803 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2804 core_version, core_major, core_minor);
2805
2806 if (core_major == 1 && core_minor >= 0x42)
2807 msm_host->use_14lpp_dll_reset = true;
2808
2809 /*
2810 * SDCC 5 controller with major version 1, minor version 0x34 and later
2811 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2812 */
2813 if (core_major == 1 && core_minor < 0x34)
2814 msm_host->use_cdclp533 = true;
2815
2816 /*
2817 * Support for some capabilities is not advertised by newer
2818 * controller versions and must be explicitly enabled.
2819 */
2820 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
2821 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2822 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
2823 writel_relaxed(config, host->ioaddr +
2824 msm_offset->core_vendor_spec_capabilities0);
2825 }
2826
2827 if (core_major == 1 && core_minor >= 0x49)
2828 msm_host->updated_ddr_cfg = true;
2829
2830 if (core_major == 1 && core_minor >= 0x71)
2831 msm_host->uses_tassadar_dll = true;
2832
2833 ret = sdhci_msm_register_vreg(msm_host);
2834 if (ret)
2835 goto clk_disable;
2836
2837 /*
2838 * Power on reset state may trigger power irq if previous status of
2839 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2840 * interrupt in GIC, any pending power irq interrupt should be
2841 * acknowledged. Otherwise power irq interrupt handler would be
2842 * fired prematurely.
2843 */
2844 sdhci_msm_handle_pwr_irq(host, 0);
2845
2846 /*
2847 * Ensure that above writes are propagated before interrupt enablement
2848 * in GIC.
2849 */
2850 mb();
2851
2852 /* Setup IRQ for handling power/voltage tasks with PMIC */
2853 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2854 if (msm_host->pwr_irq < 0) {
2855 ret = msm_host->pwr_irq;
2856 goto clk_disable;
2857 }
2858
2859 sdhci_msm_init_pwr_irq_wait(msm_host);
2860 /* Enable pwr irq interrupts */
2861 msm_host_writel(msm_host, INT_MASK, host,
2862 msm_offset->core_pwrctl_mask);
2863
2864 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2865 sdhci_msm_pwr_irq, IRQF_ONESHOT,
2866 dev_name(&pdev->dev), host);
2867 if (ret) {
2868 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2869 goto clk_disable;
2870 }
2871
2872 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2873
2874 #ifdef CONFIG_MMC_CRYPTO
2875 host->mmc_host_ops.request = sdhci_msm_request;
2876 #endif
2877 /* Set the timeout value to max possible */
2878 host->max_timeout_count = 0xF;
2879
2880 pm_runtime_get_noresume(&pdev->dev);
2881 pm_runtime_set_active(&pdev->dev);
2882 pm_runtime_enable(&pdev->dev);
2883 pm_runtime_set_autosuspend_delay(&pdev->dev,
2884 MSM_MMC_AUTOSUSPEND_DELAY_MS);
2885 pm_runtime_use_autosuspend(&pdev->dev);
2886
2887 host->mmc_host_ops.start_signal_voltage_switch =
2888 sdhci_msm_start_signal_voltage_switch;
2889 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2890 if (of_property_read_bool(node, "supports-cqe"))
2891 ret = sdhci_msm_cqe_add_host(host, pdev);
2892 else
2893 ret = sdhci_add_host(host);
2894 if (ret)
2895 goto pm_runtime_disable;
2896
2897 pm_runtime_put_autosuspend(&pdev->dev);
2898
2899 return 0;
2900
2901 pm_runtime_disable:
2902 pm_runtime_disable(&pdev->dev);
2903 pm_runtime_set_suspended(&pdev->dev);
2904 pm_runtime_put_noidle(&pdev->dev);
2905 clk_disable:
2906 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2907 msm_host->bulk_clks);
2908 bus_clk_disable:
2909 if (!IS_ERR(msm_host->bus_clk))
2910 clk_disable_unprepare(msm_host->bus_clk);
2911 return ret;
2912 }
2913
sdhci_msm_remove(struct platform_device * pdev)2914 static void sdhci_msm_remove(struct platform_device *pdev)
2915 {
2916 struct sdhci_host *host = platform_get_drvdata(pdev);
2917 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2918 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2919 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2920 0xffffffff);
2921
2922 sdhci_remove_host(host, dead);
2923
2924 pm_runtime_get_sync(&pdev->dev);
2925 pm_runtime_disable(&pdev->dev);
2926 pm_runtime_put_noidle(&pdev->dev);
2927
2928 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2929 msm_host->bulk_clks);
2930 if (!IS_ERR(msm_host->bus_clk))
2931 clk_disable_unprepare(msm_host->bus_clk);
2932 }
2933
sdhci_msm_runtime_suspend(struct device * dev)2934 static int sdhci_msm_runtime_suspend(struct device *dev)
2935 {
2936 struct sdhci_host *host = dev_get_drvdata(dev);
2937 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2938 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2939 unsigned long flags;
2940
2941 spin_lock_irqsave(&host->lock, flags);
2942 host->runtime_suspended = true;
2943 spin_unlock_irqrestore(&host->lock, flags);
2944
2945 /* Drop the performance vote */
2946 dev_pm_opp_set_rate(dev, 0);
2947 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2948 msm_host->bulk_clks);
2949
2950 return sdhci_msm_ice_suspend(msm_host);
2951 }
2952
sdhci_msm_runtime_resume(struct device * dev)2953 static int sdhci_msm_runtime_resume(struct device *dev)
2954 {
2955 struct sdhci_host *host = dev_get_drvdata(dev);
2956 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2957 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2958 unsigned long flags;
2959 int ret;
2960
2961 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2962 msm_host->bulk_clks);
2963 if (ret)
2964 return ret;
2965 /*
2966 * Whenever core-clock is gated dynamically, it's needed to
2967 * restore the SDR DLL settings when the clock is ungated.
2968 */
2969 if (msm_host->restore_dll_config && msm_host->clk_rate) {
2970 ret = sdhci_msm_restore_sdr_dll_config(host);
2971 if (ret)
2972 return ret;
2973 }
2974
2975 dev_pm_opp_set_rate(dev, msm_host->clk_rate);
2976
2977 ret = sdhci_msm_ice_resume(msm_host);
2978 if (ret)
2979 return ret;
2980
2981 spin_lock_irqsave(&host->lock, flags);
2982 host->runtime_suspended = false;
2983 spin_unlock_irqrestore(&host->lock, flags);
2984
2985 return ret;
2986 }
2987
2988 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2989 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
2990 RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, sdhci_msm_runtime_resume, NULL)
2991 };
2992
2993 static struct platform_driver sdhci_msm_driver = {
2994 .probe = sdhci_msm_probe,
2995 .remove = sdhci_msm_remove,
2996 .driver = {
2997 .name = "sdhci_msm",
2998 .of_match_table = sdhci_msm_dt_match,
2999 .pm = pm_ptr(&sdhci_msm_pm_ops),
3000 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3001 },
3002 };
3003
3004 module_platform_driver(sdhci_msm_driver);
3005
3006 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
3007 MODULE_LICENSE("GPL v2");
3008