Home
last modified time | relevance | path

Searched refs:CONTROL (Results 1 – 25 of 83) sorted by relevance

1234

/linux/net/devlink/
H A Dtrap.c987 DEVLINK_TRAP(STP, CONTROL),
988 DEVLINK_TRAP(LACP, CONTROL),
989 DEVLINK_TRAP(LLDP, CONTROL),
990 DEVLINK_TRAP(IGMP_QUERY, CONTROL),
991 DEVLINK_TRAP(IGMP_V1_REPORT, CONTROL),
992 DEVLINK_TRAP(IGMP_V2_REPORT, CONTROL),
993 DEVLINK_TRAP(IGMP_V3_REPORT, CONTROL),
994 DEVLINK_TRAP(IGMP_V2_LEAVE, CONTROL),
995 DEVLINK_TRAP(MLD_QUERY, CONTROL),
996 DEVLINK_TRAP(MLD_V1_REPORT, CONTROL),
[all …]
/linux/drivers/parport/
H A Dparport_gsc.c83 s->u.pc.ctr = parport_readb (CONTROL (p)); in parport_gsc_save_state()
88 parport_writeb (s->u.pc.ctr, CONTROL (p)); in parport_gsc_restore_state()
147 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
154 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
157 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
158 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
159 parport_writeb (0xc, CONTROL (pb)); in parport_SPP_supported()
H A Dparport_gsc.h47 #define CONTROL(p) ((p)->base + 0x2) macro
101 parport_writeb (ctr, CONTROL (p)); in __parport_gsc_frob_control()
H A Dparport_pc.c259 outb(c, CONTROL(p)); in parport_pc_restore_state()
1430 outb(w, CONTROL(pb)); in parport_SPP_supported()
1437 r = inb(CONTROL(pb)); in parport_SPP_supported()
1440 outb(w, CONTROL(pb)); in parport_SPP_supported()
1441 r = inb(CONTROL(pb)); in parport_SPP_supported()
1442 outb(0xc, CONTROL(pb)); in parport_SPP_supported()
1502 outb(r, CONTROL(pb)); in parport_ECR_present()
1504 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ in parport_ECR_present()
1506 r = inb(CONTROL(pb)); in parport_ECR_present()
1521 outb(0xc, CONTROL(pb)); in parport_ECR_present()
[all …]
/linux/drivers/clocksource/
H A Dtimer-digicolor.c48 #define CONTROL(t) ((t)*8) macro
72 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable()
78 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable()
180 writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
182 writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
/linux/include/linux/
H A Dparport_pc.h15 #define CONTROL(p) ((p)->base + 0x2) macro
89 unsigned char dcr = inb (CONTROL (p)); in dump_parport_state()
103 dcr = i ? priv->ctr : inb (CONTROL (p)); in dump_parport_state()
144 outb (ctr, CONTROL (p)); in __parport_pc_frob_control()
/linux/sound/pci/
H A Dens1370.c679 inl(ES_REG(ensoniq, CONTROL)); in snd_es1371_codec_read()
838 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_trigger()
873 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback1_prepare()
892 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback1_prepare()
914 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback2_prepare()
932 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback2_prepare()
954 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_capture_prepare()
970 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_capture_prepare()
984 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { in snd_ensoniq_playback1_pointer()
1001 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { in snd_ensoniq_playback2_pointer()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c104 REG_UPDATE(CONTROL, in optc31_enable_crtc()
141 REG_UPDATE(CONTROL, in optc31_disable_crtc()
163 REG_UPDATE(CONTROL, in optc31_immediate_disable_crtc()
/linux/drivers/bluetooth/
H A Dbt3c_cs.c113 #define CONTROL 4 macro
349 iir = inb(iobase + CONTROL); in bt3c_interrupt()
370 outb(iir, iobase + CONTROL); in bt3c_interrupt()
524 outb(inb(iobase + CONTROL) | 0x40, iobase + CONTROL); in bt3c_load_firmware()
/linux/drivers/watchdog/
H A Dmachzwd.c52 #define CONTROL 0x10 /* 16 */ macro
155 return zf_readw(CONTROL); in zf_get_control()
160 zf_writew(CONTROL, new); in zf_set_control()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.c114 REG_UPDATE(CONTROL, in optc314_enable_crtc()
141 REG_UPDATE(CONTROL, in optc314_disable_crtc()
/linux/drivers/media/usb/uvc/
H A Duvc_ctrl.c1000 uvc_dbg(chain->dev, CONTROL, "Control 0x%08x not found\n", in uvc_find_control()
2162 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2175 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2183 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2213 uvc_dbg(dev, CONTROL, in uvc_ctrl_init_xu_ctrl()
2244 uvc_dbg(chain->dev, CONTROL, "Extension unit %u not found\n", in uvc_xu_ctrl_query()
2260 uvc_dbg(chain->dev, CONTROL, "Control %pUl/%u not found\n", in uvc_xu_ctrl_query()
2409 uvc_dbg(dev, CONTROL, "Added control %pUl/%u to device %s entity %u\n", in uvc_ctrl_add_info()
2479 uvc_dbg(chain->dev, CONTROL, "Adding mapping '%s' to control %pUl/%u\n", in __uvc_ctrl_add_mapping()
2504 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dmarvell,orion-timer.txt5 - reg: base address of the timer register starting with TIMERS CONTROL register
/linux/Documentation/leds/
H A Dleds-lm3556.rst23 CONTROL REGISTER(0x09).Flash mode is activated by the ENABLE REGISTER(0x0A),
50 In Torch Mode, the current source(LED) is programmed via the CURRENT CONTROL
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.h78 SRI(CONTROL, FMT_MEMORY, id)
82 SRI(CONTROL, FMT_MEMORY, id)
296 uint32_t CONTROL; member
H A Ddce_opp.c586 REG_GET(CONTROL, in program_formatter_420_memory()
593 REG_UPDATE(CONTROL, in program_formatter_420_memory()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/
H A Ddcn32_optc.c154 REG_UPDATE(CONTROL, in optc32_enable_crtc()
191 REG_UPDATE(CONTROL, in optc32_disable_crtc()
/linux/drivers/net/ethernet/smsc/
H A Dsmc9194.c338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset()
398 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL ); in smc_shutdown()
H A Dsmc91c92_cs.c191 #define CONTROL 12 macro
553 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL); in mot_setup()
557 wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL)); in mot_setup()
775 outw(0, ioaddr + CONTROL); in check_sig()
1105 outw(CTL_POWERDOWN, ioaddr + CONTROL ); in smc_close()
1336 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL); in smc_eph_irq()
1338 ioaddr + CONTROL); in smc_eph_irq()
1664 ioaddr + CONTROL); in smc_reset()
H A Dsmc9194.h104 #define CONTROL 12 macro
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c278 REG_UPDATE(CONTROL, in optc1_program_timing()
384 REG_UPDATE_2(CONTROL,
388 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); in optc1_set_blank_data_double_buffer()
539 REG_UPDATE(CONTROL, in optc1_enable_crtc()
567 REG_UPDATE(CONTROL, in optc1_disable_crtc()
/linux/drivers/scsi/
H A Daha1542.h29 #define CONTROL(base) STATUS(base) macro
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c121 REG_UPDATE(CONTROL, in optc35_enable_crtc()
158 REG_UPDATE(CONTROL, in optc35_disable_crtc()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
H A Ddcn401_optc.c189 REG_UPDATE(CONTROL, in optc401_enable_crtc()
226 REG_UPDATE(CONTROL, in optc401_disable_crtc()
/linux/Documentation/driver-api/backlight/
H A Dlp855x-driver.rst44 Value of DEVICE CONTROL register.

1234