1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * A V4L2 driver for OmniVision OV7670 cameras.
4 *
5 * Copyright 2006 One Laptop Per Child Association, Inc. Written
6 * by Jonathan Corbet with substantial inspiration from Mark
7 * McClelland's ovcamchip code.
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 */
11 #include <linux/clk.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/i2c.h>
16 #include <linux/delay.h>
17 #include <linux/videodev2.h>
18 #include <linux/gpio/consumer.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-event.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-mediabus.h>
24 #include <media/v4l2-image-sizes.h>
25 #include <media/i2c/ov7670.h>
26
27 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
28 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
29 MODULE_LICENSE("GPL");
30
31 static bool debug;
32 module_param(debug, bool, 0644);
33 MODULE_PARM_DESC(debug, "Debug level (0-1)");
34
35 /*
36 * The 7670 sits on i2c with ID 0x42
37 */
38 #define OV7670_I2C_ADDR 0x42
39
40 #define PLL_FACTOR 4
41
42 /* Registers */
43 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
44 #define REG_BLUE 0x01 /* blue gain */
45 #define REG_RED 0x02 /* red gain */
46 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
47 #define REG_COM1 0x04 /* Control 1 */
48 #define COM1_CCIR656 0x40 /* CCIR656 enable */
49 #define REG_BAVE 0x05 /* U/B Average level */
50 #define REG_GbAVE 0x06 /* Y/Gb Average level */
51 #define REG_AECHH 0x07 /* AEC MS 5 bits */
52 #define REG_RAVE 0x08 /* V/R Average level */
53 #define REG_COM2 0x09 /* Control 2 */
54 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
55 #define REG_PID 0x0a /* Product ID MSB */
56 #define REG_VER 0x0b /* Product ID LSB */
57 #define REG_COM3 0x0c /* Control 3 */
58 #define COM3_SWAP 0x40 /* Byte swap */
59 #define COM3_SCALEEN 0x08 /* Enable scaling */
60 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
61 #define REG_COM4 0x0d /* Control 4 */
62 #define REG_COM5 0x0e /* All "reserved" */
63 #define REG_COM6 0x0f /* Control 6 */
64 #define REG_AECH 0x10 /* More bits of AEC value */
65 #define REG_CLKRC 0x11 /* Clocl control */
66 #define CLK_EXT 0x40 /* Use external clock directly */
67 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
68 #define REG_COM7 0x12 /* Control 7 */
69 #define COM7_RESET 0x80 /* Register reset */
70 #define COM7_FMT_MASK 0x38
71 #define COM7_FMT_VGA 0x00
72 #define COM7_FMT_CIF 0x20 /* CIF format */
73 #define COM7_FMT_QVGA 0x10 /* QVGA format */
74 #define COM7_FMT_QCIF 0x08 /* QCIF format */
75 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
76 #define COM7_YUV 0x00 /* YUV */
77 #define COM7_BAYER 0x01 /* Bayer format */
78 #define COM7_PBAYER 0x05 /* "Processed bayer" */
79 #define REG_COM8 0x13 /* Control 8 */
80 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
81 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
82 #define COM8_BFILT 0x20 /* Band filter enable */
83 #define COM8_AGC 0x04 /* Auto gain enable */
84 #define COM8_AWB 0x02 /* White balance enable */
85 #define COM8_AEC 0x01 /* Auto exposure enable */
86 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
87 #define REG_COM10 0x15 /* Control 10 */
88 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
89 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
90 #define COM10_HREF_REV 0x08 /* Reverse HREF */
91 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
92 #define COM10_VS_NEG 0x02 /* VSYNC negative */
93 #define COM10_HS_NEG 0x01 /* HSYNC negative */
94 #define REG_HSTART 0x17 /* Horiz start high bits */
95 #define REG_HSTOP 0x18 /* Horiz stop high bits */
96 #define REG_VSTART 0x19 /* Vert start high bits */
97 #define REG_VSTOP 0x1a /* Vert stop high bits */
98 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
99 #define REG_MIDH 0x1c /* Manuf. ID high */
100 #define REG_MIDL 0x1d /* Manuf. ID low */
101 #define REG_MVFP 0x1e /* Mirror / vflip */
102 #define MVFP_MIRROR 0x20 /* Mirror image */
103 #define MVFP_FLIP 0x10 /* Vertical flip */
104
105 #define REG_AEW 0x24 /* AGC upper limit */
106 #define REG_AEB 0x25 /* AGC lower limit */
107 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
108 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
109 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
110 #define REG_HREF 0x32 /* HREF pieces */
111 #define REG_TSLB 0x3a /* lots of stuff */
112 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
113 #define REG_COM11 0x3b /* Control 11 */
114 #define COM11_NIGHT 0x80 /* NIght mode enable */
115 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
116 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
117 #define COM11_50HZ 0x08 /* Manual 50Hz select */
118 #define COM11_EXP 0x02
119 #define REG_COM12 0x3c /* Control 12 */
120 #define COM12_HREF 0x80 /* HREF always */
121 #define REG_COM13 0x3d /* Control 13 */
122 #define COM13_GAMMA 0x80 /* Gamma enable */
123 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
124 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
125 #define REG_COM14 0x3e /* Control 14 */
126 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
127 #define REG_EDGE 0x3f /* Edge enhancement factor */
128 #define REG_COM15 0x40 /* Control 15 */
129 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
130 #define COM15_R01FE 0x80 /* 01 to FE */
131 #define COM15_R00FF 0xc0 /* 00 to FF */
132 #define COM15_RGB565 0x10 /* RGB565 output */
133 #define COM15_RGB555 0x30 /* RGB555 output */
134 #define REG_COM16 0x41 /* Control 16 */
135 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
136 #define REG_COM17 0x42 /* Control 17 */
137 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
138 #define COM17_CBAR 0x08 /* DSP Color bar */
139
140 /*
141 * This matrix defines how the colors are generated, must be
142 * tweaked to adjust hue and saturation.
143 *
144 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
145 *
146 * They are nine-bit signed quantities, with the sign bit
147 * stored in 0x58. Sign for v-red is bit 0, and up from there.
148 */
149 #define REG_CMATRIX_BASE 0x4f
150 #define CMATRIX_LEN 6
151 #define REG_CMATRIX_SIGN 0x58
152
153
154 #define REG_BRIGHT 0x55 /* Brightness */
155 #define REG_CONTRAS 0x56 /* Contrast control */
156
157 #define REG_GFIX 0x69 /* Fix gain control */
158
159 #define REG_DBLV 0x6b /* PLL control an debugging */
160 #define DBLV_BYPASS 0x0a /* Bypass PLL */
161 #define DBLV_X4 0x4a /* clock x4 */
162 #define DBLV_X6 0x8a /* clock x6 */
163 #define DBLV_X8 0xca /* clock x8 */
164
165 #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */
166 #define TEST_PATTTERN_0 0x80
167 #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */
168 #define TEST_PATTTERN_1 0x80
169
170 #define REG_REG76 0x76 /* OV's name */
171 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
172 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
173
174 #define REG_RGB444 0x8c /* RGB 444 control */
175 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
176 #define R444_RGBX 0x01 /* Empty nibble at end */
177
178 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
179 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
180
181 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
182 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
183 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
184 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
185 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
186 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
187 #define REG_BD60MAX 0xab /* 60hz banding step limit */
188
189 struct ov7670_win_size {
190 int width;
191 int height;
192 unsigned char com7_bit;
193 int hstart; /* Start/stop values for the camera. Note */
194 int hstop; /* that they do not always make complete */
195 int vstart; /* sense to humans, but evidently the sensor */
196 int vstop; /* will do the right thing... */
197 struct regval_list *regs; /* Regs to tweak */
198 };
199
200 struct ov7670_devtype {
201 /* formats supported for each model */
202 struct ov7670_win_size *win_sizes;
203 unsigned int n_win_sizes;
204 /* callbacks for frame rate control */
205 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
206 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
207 };
208
209 /*
210 * Information we maintain about a known sensor.
211 */
212 struct ov7670_format_struct; /* coming later */
213 struct ov7670_info {
214 struct v4l2_subdev sd;
215 struct media_pad pad;
216 struct v4l2_ctrl_handler hdl;
217 struct {
218 /* gain cluster */
219 struct v4l2_ctrl *auto_gain;
220 struct v4l2_ctrl *gain;
221 };
222 struct {
223 /* exposure cluster */
224 struct v4l2_ctrl *auto_exposure;
225 struct v4l2_ctrl *exposure;
226 };
227 struct {
228 /* saturation/hue cluster */
229 struct v4l2_ctrl *saturation;
230 struct v4l2_ctrl *hue;
231 };
232 struct v4l2_mbus_framefmt format;
233 struct ov7670_format_struct *fmt; /* Current format */
234 struct ov7670_win_size *wsize;
235 struct clk *clk;
236 int on;
237 struct gpio_desc *resetb_gpio;
238 struct gpio_desc *pwdn_gpio;
239 unsigned int mbus_config; /* Media bus configuration flags */
240 int min_width; /* Filter out smaller sizes */
241 int min_height; /* Filter out smaller sizes */
242 int clock_speed; /* External clock speed (MHz) */
243 u8 clkrc; /* Clock divider value */
244 bool use_smbus; /* Use smbus I/O instead of I2C */
245 bool pll_bypass;
246 bool pclk_hb_disable;
247 const struct ov7670_devtype *devtype; /* Device specifics */
248 };
249
to_state(struct v4l2_subdev * sd)250 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
251 {
252 return container_of(sd, struct ov7670_info, sd);
253 }
254
to_sd(struct v4l2_ctrl * ctrl)255 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
256 {
257 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
258 }
259
260
261
262 /*
263 * The default register settings, as obtained from OmniVision. There
264 * is really no making sense of most of these - lots of "reserved" values
265 * and such.
266 *
267 * These settings give VGA YUYV.
268 */
269
270 struct regval_list {
271 unsigned char reg_num;
272 unsigned char value;
273 };
274
275 static struct regval_list ov7670_default_regs[] = {
276 { REG_COM7, COM7_RESET },
277 /*
278 * Clock scale: 3 = 15fps
279 * 2 = 20fps
280 * 1 = 30fps
281 */
282 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
283 { REG_TSLB, 0x04 }, /* OV */
284 { REG_COM7, 0 }, /* VGA */
285 /*
286 * Set the hardware window. These values from OV don't entirely
287 * make sense - hstop is less than hstart. But they work...
288 */
289 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
290 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
291 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
292
293 { REG_COM3, 0 }, { REG_COM14, 0 },
294 /* Mystery scaling numbers */
295 { REG_SCALING_XSC, 0x3a },
296 { REG_SCALING_YSC, 0x35 },
297 { 0x72, 0x11 }, { 0x73, 0xf0 },
298 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
299
300 /* Gamma curve values */
301 { 0x7a, 0x20 }, { 0x7b, 0x10 },
302 { 0x7c, 0x1e }, { 0x7d, 0x35 },
303 { 0x7e, 0x5a }, { 0x7f, 0x69 },
304 { 0x80, 0x76 }, { 0x81, 0x80 },
305 { 0x82, 0x88 }, { 0x83, 0x8f },
306 { 0x84, 0x96 }, { 0x85, 0xa3 },
307 { 0x86, 0xaf }, { 0x87, 0xc4 },
308 { 0x88, 0xd7 }, { 0x89, 0xe8 },
309
310 /* AGC and AEC parameters. Note we start by disabling those features,
311 then turn them only after tweaking the values. */
312 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
313 { REG_GAIN, 0 }, { REG_AECH, 0 },
314 { REG_COM4, 0x40 }, /* magic reserved bit */
315 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
316 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
317 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
318 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
319 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
320 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
321 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
322 { REG_HAECC7, 0x94 },
323 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
324
325 /* Almost all of these are magic "reserved" values. */
326 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
327 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
328 { 0x21, 0x02 }, { 0x22, 0x91 },
329 { 0x29, 0x07 }, { 0x33, 0x0b },
330 { 0x35, 0x0b }, { 0x37, 0x1d },
331 { 0x38, 0x71 }, { 0x39, 0x2a },
332 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
333 { 0x4e, 0x20 }, { REG_GFIX, 0 },
334 { 0x6b, 0x4a }, { 0x74, 0x10 },
335 { 0x8d, 0x4f }, { 0x8e, 0 },
336 { 0x8f, 0 }, { 0x90, 0 },
337 { 0x91, 0 }, { 0x96, 0 },
338 { 0x9a, 0 }, { 0xb0, 0x84 },
339 { 0xb1, 0x0c }, { 0xb2, 0x0e },
340 { 0xb3, 0x82 }, { 0xb8, 0x0a },
341
342 /* More reserved magic, some of which tweaks white balance */
343 { 0x43, 0x0a }, { 0x44, 0xf0 },
344 { 0x45, 0x34 }, { 0x46, 0x58 },
345 { 0x47, 0x28 }, { 0x48, 0x3a },
346 { 0x59, 0x88 }, { 0x5a, 0x88 },
347 { 0x5b, 0x44 }, { 0x5c, 0x67 },
348 { 0x5d, 0x49 }, { 0x5e, 0x0e },
349 { 0x6c, 0x0a }, { 0x6d, 0x55 },
350 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
351 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
352 { REG_RED, 0x60 },
353 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
354
355 /* Matrix coefficients */
356 { 0x4f, 0x80 }, { 0x50, 0x80 },
357 { 0x51, 0 }, { 0x52, 0x22 },
358 { 0x53, 0x5e }, { 0x54, 0x80 },
359 { 0x58, 0x9e },
360
361 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
362 { 0x75, 0x05 }, { 0x76, 0xe1 },
363 { 0x4c, 0 }, { 0x77, 0x01 },
364 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
365 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
366 { 0x56, 0x40 },
367
368 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
369 { 0xa4, 0x88 }, { 0x96, 0 },
370 { 0x97, 0x30 }, { 0x98, 0x20 },
371 { 0x99, 0x30 }, { 0x9a, 0x84 },
372 { 0x9b, 0x29 }, { 0x9c, 0x03 },
373 { 0x9d, 0x4c }, { 0x9e, 0x3f },
374 { 0x78, 0x04 },
375
376 /* Extra-weird stuff. Some sort of multiplexor register */
377 { 0x79, 0x01 }, { 0xc8, 0xf0 },
378 { 0x79, 0x0f }, { 0xc8, 0x00 },
379 { 0x79, 0x10 }, { 0xc8, 0x7e },
380 { 0x79, 0x0a }, { 0xc8, 0x80 },
381 { 0x79, 0x0b }, { 0xc8, 0x01 },
382 { 0x79, 0x0c }, { 0xc8, 0x0f },
383 { 0x79, 0x0d }, { 0xc8, 0x20 },
384 { 0x79, 0x09 }, { 0xc8, 0x80 },
385 { 0x79, 0x02 }, { 0xc8, 0xc0 },
386 { 0x79, 0x03 }, { 0xc8, 0x40 },
387 { 0x79, 0x05 }, { 0xc8, 0x30 },
388 { 0x79, 0x26 },
389
390 { 0xff, 0xff }, /* END MARKER */
391 };
392
393
394 /*
395 * Here we'll try to encapsulate the changes for just the output
396 * video format.
397 *
398 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
399 *
400 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
401 */
402
403
404 static struct regval_list ov7670_fmt_yuv422[] = {
405 { REG_COM7, 0x0 }, /* Selects YUV mode */
406 { REG_RGB444, 0 }, /* No RGB444 please */
407 { REG_COM1, 0 }, /* CCIR601 */
408 { REG_COM15, COM15_R00FF },
409 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
410 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
411 { 0x50, 0x80 }, /* "matrix coefficient 2" */
412 { 0x51, 0 }, /* vb */
413 { 0x52, 0x22 }, /* "matrix coefficient 4" */
414 { 0x53, 0x5e }, /* "matrix coefficient 5" */
415 { 0x54, 0x80 }, /* "matrix coefficient 6" */
416 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
417 { 0xff, 0xff },
418 };
419
420 static struct regval_list ov7670_fmt_rgb565[] = {
421 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
422 { REG_RGB444, 0 }, /* No RGB444 please */
423 { REG_COM1, 0x0 }, /* CCIR601 */
424 { REG_COM15, COM15_RGB565 },
425 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
426 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
427 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
428 { 0x51, 0 }, /* vb */
429 { 0x52, 0x3d }, /* "matrix coefficient 4" */
430 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
431 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
432 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
433 { 0xff, 0xff },
434 };
435
436 static struct regval_list ov7670_fmt_rgb444[] = {
437 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
438 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
439 { REG_COM1, 0x0 }, /* CCIR601 */
440 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
441 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
442 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
443 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
444 { 0x51, 0 }, /* vb */
445 { 0x52, 0x3d }, /* "matrix coefficient 4" */
446 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
447 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
448 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
449 { 0xff, 0xff },
450 };
451
452 static struct regval_list ov7670_fmt_raw[] = {
453 { REG_COM7, COM7_BAYER },
454 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
455 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
456 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
457 { 0xff, 0xff },
458 };
459
460
461
462 /*
463 * Low-level register I/O.
464 *
465 * Note that there are two versions of these. On the XO 1, the
466 * i2c controller only does SMBUS, so that's what we use. The
467 * ov7670 is not really an SMBUS device, though, so the communication
468 * is not always entirely reliable.
469 */
ov7670_read_smbus(struct v4l2_subdev * sd,unsigned char reg,unsigned char * value)470 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
471 unsigned char *value)
472 {
473 struct i2c_client *client = v4l2_get_subdevdata(sd);
474 int ret;
475
476 ret = i2c_smbus_read_byte_data(client, reg);
477 if (ret >= 0) {
478 *value = (unsigned char)ret;
479 ret = 0;
480 }
481 return ret;
482 }
483
484
ov7670_write_smbus(struct v4l2_subdev * sd,unsigned char reg,unsigned char value)485 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
486 unsigned char value)
487 {
488 struct i2c_client *client = v4l2_get_subdevdata(sd);
489 int ret = i2c_smbus_write_byte_data(client, reg, value);
490
491 if (reg == REG_COM7 && (value & COM7_RESET))
492 msleep(5); /* Wait for reset to run */
493 return ret;
494 }
495
496 /*
497 * On most platforms, we'd rather do straight i2c I/O.
498 */
ov7670_read_i2c(struct v4l2_subdev * sd,unsigned char reg,unsigned char * value)499 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
500 unsigned char *value)
501 {
502 struct i2c_client *client = v4l2_get_subdevdata(sd);
503 u8 data = reg;
504 struct i2c_msg msg;
505 int ret;
506
507 /*
508 * Send out the register address...
509 */
510 msg.addr = client->addr;
511 msg.flags = 0;
512 msg.len = 1;
513 msg.buf = &data;
514 ret = i2c_transfer(client->adapter, &msg, 1);
515 if (ret < 0) {
516 printk(KERN_ERR "Error %d on register write\n", ret);
517 return ret;
518 }
519 /*
520 * ...then read back the result.
521 */
522 msg.flags = I2C_M_RD;
523 ret = i2c_transfer(client->adapter, &msg, 1);
524 if (ret >= 0) {
525 *value = data;
526 ret = 0;
527 }
528 return ret;
529 }
530
531
ov7670_write_i2c(struct v4l2_subdev * sd,unsigned char reg,unsigned char value)532 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
533 unsigned char value)
534 {
535 struct i2c_client *client = v4l2_get_subdevdata(sd);
536 struct i2c_msg msg;
537 unsigned char data[2] = { reg, value };
538 int ret;
539
540 msg.addr = client->addr;
541 msg.flags = 0;
542 msg.len = 2;
543 msg.buf = data;
544 ret = i2c_transfer(client->adapter, &msg, 1);
545 if (ret > 0)
546 ret = 0;
547 if (reg == REG_COM7 && (value & COM7_RESET))
548 msleep(5); /* Wait for reset to run */
549 return ret;
550 }
551
ov7670_read(struct v4l2_subdev * sd,unsigned char reg,unsigned char * value)552 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
553 unsigned char *value)
554 {
555 struct ov7670_info *info = to_state(sd);
556
557 if (info->use_smbus)
558 return ov7670_read_smbus(sd, reg, value);
559 else
560 return ov7670_read_i2c(sd, reg, value);
561 }
562
ov7670_write(struct v4l2_subdev * sd,unsigned char reg,unsigned char value)563 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
564 unsigned char value)
565 {
566 struct ov7670_info *info = to_state(sd);
567
568 if (info->use_smbus)
569 return ov7670_write_smbus(sd, reg, value);
570 else
571 return ov7670_write_i2c(sd, reg, value);
572 }
573
ov7670_update_bits(struct v4l2_subdev * sd,unsigned char reg,unsigned char mask,unsigned char value)574 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg,
575 unsigned char mask, unsigned char value)
576 {
577 unsigned char orig;
578 int ret;
579
580 ret = ov7670_read(sd, reg, &orig);
581 if (ret)
582 return ret;
583
584 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask));
585 }
586
587 /*
588 * Write a list of register settings; ff/ff stops the process.
589 */
ov7670_write_array(struct v4l2_subdev * sd,struct regval_list * vals)590 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
591 {
592 while (vals->reg_num != 0xff || vals->value != 0xff) {
593 int ret = ov7670_write(sd, vals->reg_num, vals->value);
594
595 if (ret < 0)
596 return ret;
597 vals++;
598 }
599 return 0;
600 }
601
602
603 /*
604 * Stuff that knows about the sensor.
605 */
ov7670_reset(struct v4l2_subdev * sd,u32 val)606 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
607 {
608 ov7670_write(sd, REG_COM7, COM7_RESET);
609 msleep(1);
610 return 0;
611 }
612
613
ov7670_init(struct v4l2_subdev * sd,u32 val)614 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
615 {
616 return ov7670_write_array(sd, ov7670_default_regs);
617 }
618
ov7670_detect(struct v4l2_subdev * sd)619 static int ov7670_detect(struct v4l2_subdev *sd)
620 {
621 unsigned char v;
622 int ret;
623
624 ret = ov7670_init(sd, 0);
625 if (ret < 0)
626 return ret;
627 ret = ov7670_read(sd, REG_MIDH, &v);
628 if (ret < 0)
629 return ret;
630 if (v != 0x7f) /* OV manuf. id. */
631 return -ENODEV;
632 ret = ov7670_read(sd, REG_MIDL, &v);
633 if (ret < 0)
634 return ret;
635 if (v != 0xa2)
636 return -ENODEV;
637 /*
638 * OK, we know we have an OmniVision chip...but which one?
639 */
640 ret = ov7670_read(sd, REG_PID, &v);
641 if (ret < 0)
642 return ret;
643 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
644 return -ENODEV;
645 ret = ov7670_read(sd, REG_VER, &v);
646 if (ret < 0)
647 return ret;
648 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
649 return -ENODEV;
650 return 0;
651 }
652
653
654 /*
655 * Store information about the video data format. The color matrix
656 * is deeply tied into the format, so keep the relevant values here.
657 * The magic matrix numbers come from OmniVision.
658 */
659 static struct ov7670_format_struct {
660 u32 mbus_code;
661 enum v4l2_colorspace colorspace;
662 struct regval_list *regs;
663 int cmatrix[CMATRIX_LEN];
664 } ov7670_formats[] = {
665 {
666 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
667 .colorspace = V4L2_COLORSPACE_SRGB,
668 .regs = ov7670_fmt_yuv422,
669 .cmatrix = { 128, -128, 0, -34, -94, 128 },
670 },
671 {
672 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
673 .colorspace = V4L2_COLORSPACE_SRGB,
674 .regs = ov7670_fmt_rgb444,
675 .cmatrix = { 179, -179, 0, -61, -176, 228 },
676 },
677 {
678 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
679 .colorspace = V4L2_COLORSPACE_SRGB,
680 .regs = ov7670_fmt_rgb565,
681 .cmatrix = { 179, -179, 0, -61, -176, 228 },
682 },
683 {
684 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
685 .colorspace = V4L2_COLORSPACE_SRGB,
686 .regs = ov7670_fmt_raw,
687 .cmatrix = { 0, 0, 0, 0, 0, 0 },
688 },
689 };
690 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
691
692
693 /*
694 * Then there is the issue of window sizes. Try to capture the info here.
695 */
696
697 /*
698 * QCIF mode is done (by OV) in a very strange way - it actually looks like
699 * VGA with weird scaling options - they do *not* use the canned QCIF mode
700 * which is allegedly provided by the sensor. So here's the weird register
701 * settings.
702 */
703 static struct regval_list ov7670_qcif_regs[] = {
704 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
705 { REG_COM3, COM3_DCWEN },
706 { REG_COM14, COM14_DCWEN | 0x01},
707 { 0x73, 0xf1 },
708 { 0xa2, 0x52 },
709 { 0x7b, 0x1c },
710 { 0x7c, 0x28 },
711 { 0x7d, 0x3c },
712 { 0x7f, 0x69 },
713 { REG_COM9, 0x38 },
714 { 0xa1, 0x0b },
715 { 0x74, 0x19 },
716 { 0x9a, 0x80 },
717 { 0x43, 0x14 },
718 { REG_COM13, 0xc0 },
719 { 0xff, 0xff },
720 };
721
722 static struct ov7670_win_size ov7670_win_sizes[] = {
723 /* VGA */
724 {
725 .width = VGA_WIDTH,
726 .height = VGA_HEIGHT,
727 .com7_bit = COM7_FMT_VGA,
728 .hstart = 158, /* These values from */
729 .hstop = 14, /* Omnivision */
730 .vstart = 10,
731 .vstop = 490,
732 .regs = NULL,
733 },
734 /* CIF */
735 {
736 .width = CIF_WIDTH,
737 .height = CIF_HEIGHT,
738 .com7_bit = COM7_FMT_CIF,
739 .hstart = 170, /* Empirically determined */
740 .hstop = 90,
741 .vstart = 14,
742 .vstop = 494,
743 .regs = NULL,
744 },
745 /* QVGA */
746 {
747 .width = QVGA_WIDTH,
748 .height = QVGA_HEIGHT,
749 .com7_bit = COM7_FMT_QVGA,
750 .hstart = 168, /* Empirically determined */
751 .hstop = 24,
752 .vstart = 12,
753 .vstop = 492,
754 .regs = NULL,
755 },
756 /* QCIF */
757 {
758 .width = QCIF_WIDTH,
759 .height = QCIF_HEIGHT,
760 .com7_bit = COM7_FMT_VGA, /* see comment above */
761 .hstart = 456, /* Empirically determined */
762 .hstop = 24,
763 .vstart = 14,
764 .vstop = 494,
765 .regs = ov7670_qcif_regs,
766 }
767 };
768
769 static struct ov7670_win_size ov7675_win_sizes[] = {
770 /*
771 * Currently, only VGA is supported. Theoretically it could be possible
772 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
773 * base and tweak them empirically could be required.
774 */
775 {
776 .width = VGA_WIDTH,
777 .height = VGA_HEIGHT,
778 .com7_bit = COM7_FMT_VGA,
779 .hstart = 158, /* These values from */
780 .hstop = 14, /* Omnivision */
781 .vstart = 14, /* Empirically determined */
782 .vstop = 494,
783 .regs = NULL,
784 }
785 };
786
ov7675_get_framerate(struct v4l2_subdev * sd,struct v4l2_fract * tpf)787 static void ov7675_get_framerate(struct v4l2_subdev *sd,
788 struct v4l2_fract *tpf)
789 {
790 struct ov7670_info *info = to_state(sd);
791 u32 clkrc = info->clkrc;
792 int pll_factor;
793
794 if (info->pll_bypass)
795 pll_factor = 1;
796 else
797 pll_factor = PLL_FACTOR;
798
799 clkrc++;
800 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
801 clkrc = (clkrc >> 1);
802
803 tpf->numerator = 1;
804 tpf->denominator = (5 * pll_factor * info->clock_speed) /
805 (4 * clkrc);
806 }
807
ov7675_apply_framerate(struct v4l2_subdev * sd)808 static int ov7675_apply_framerate(struct v4l2_subdev *sd)
809 {
810 struct ov7670_info *info = to_state(sd);
811 int ret;
812
813 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
814 if (ret < 0)
815 return ret;
816
817 return ov7670_write(sd, REG_DBLV,
818 info->pll_bypass ? DBLV_BYPASS : DBLV_X4);
819 }
820
ov7675_set_framerate(struct v4l2_subdev * sd,struct v4l2_fract * tpf)821 static int ov7675_set_framerate(struct v4l2_subdev *sd,
822 struct v4l2_fract *tpf)
823 {
824 struct ov7670_info *info = to_state(sd);
825 u32 clkrc;
826 int pll_factor;
827
828 /*
829 * The formula is fps = 5/4*pixclk for YUV/RGB and
830 * fps = 5/2*pixclk for RAW.
831 *
832 * pixclk = clock_speed / (clkrc + 1) * PLLfactor
833 *
834 */
835 if (tpf->numerator == 0 || tpf->denominator == 0) {
836 clkrc = 0;
837 } else {
838 pll_factor = info->pll_bypass ? 1 : PLL_FACTOR;
839 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
840 (4 * tpf->denominator);
841 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
842 clkrc = (clkrc << 1);
843 clkrc--;
844 }
845
846 /*
847 * The datasheet claims that clkrc = 0 will divide the input clock by 1
848 * but we've checked with an oscilloscope that it divides by 2 instead.
849 * So, if clkrc = 0 just bypass the divider.
850 */
851 if (clkrc <= 0)
852 clkrc = CLK_EXT;
853 else if (clkrc > CLK_SCALE)
854 clkrc = CLK_SCALE;
855 info->clkrc = clkrc;
856
857 /* Recalculate frame rate */
858 ov7675_get_framerate(sd, tpf);
859
860 /*
861 * If the device is not powered up by the host driver do
862 * not apply any changes to H/W at this time. Instead
863 * the framerate will be restored right after power-up.
864 */
865 if (info->on)
866 return ov7675_apply_framerate(sd);
867
868 return 0;
869 }
870
ov7670_get_framerate_legacy(struct v4l2_subdev * sd,struct v4l2_fract * tpf)871 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
872 struct v4l2_fract *tpf)
873 {
874 struct ov7670_info *info = to_state(sd);
875
876 tpf->numerator = 1;
877 tpf->denominator = info->clock_speed;
878 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
879 tpf->denominator /= (info->clkrc & CLK_SCALE);
880 }
881
ov7670_set_framerate_legacy(struct v4l2_subdev * sd,struct v4l2_fract * tpf)882 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
883 struct v4l2_fract *tpf)
884 {
885 struct ov7670_info *info = to_state(sd);
886 int div;
887
888 if (tpf->numerator == 0 || tpf->denominator == 0)
889 div = 1; /* Reset to full rate */
890 else
891 div = (tpf->numerator * info->clock_speed) / tpf->denominator;
892 if (div == 0)
893 div = 1;
894 else if (div > CLK_SCALE)
895 div = CLK_SCALE;
896 info->clkrc = (info->clkrc & 0x80) | div;
897 tpf->numerator = 1;
898 tpf->denominator = info->clock_speed / div;
899
900 /*
901 * If the device is not powered up by the host driver do
902 * not apply any changes to H/W at this time. Instead
903 * the framerate will be restored right after power-up.
904 */
905 if (info->on)
906 return ov7670_write(sd, REG_CLKRC, info->clkrc);
907
908 return 0;
909 }
910
911 /*
912 * Store a set of start/stop values into the camera.
913 */
ov7670_set_hw(struct v4l2_subdev * sd,int hstart,int hstop,int vstart,int vstop)914 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
915 int vstart, int vstop)
916 {
917 int ret;
918 unsigned char v;
919 /*
920 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
921 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
922 * a mystery "edge offset" value in the top two bits of href.
923 */
924 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
925 if (ret)
926 return ret;
927 ret = ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
928 if (ret)
929 return ret;
930 ret = ov7670_read(sd, REG_HREF, &v);
931 if (ret)
932 return ret;
933 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
934 msleep(10);
935 ret = ov7670_write(sd, REG_HREF, v);
936 if (ret)
937 return ret;
938 /* Vertical: similar arrangement, but only 10 bits. */
939 ret = ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
940 if (ret)
941 return ret;
942 ret = ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
943 if (ret)
944 return ret;
945 ret = ov7670_read(sd, REG_VREF, &v);
946 if (ret)
947 return ret;
948 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
949 msleep(10);
950 return ov7670_write(sd, REG_VREF, v);
951 }
952
953
ov7670_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)954 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
955 struct v4l2_subdev_state *sd_state,
956 struct v4l2_subdev_mbus_code_enum *code)
957 {
958 if (code->pad || code->index >= N_OV7670_FMTS)
959 return -EINVAL;
960
961 code->code = ov7670_formats[code->index].mbus_code;
962 return 0;
963 }
964
ov7670_try_fmt_internal(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt,struct ov7670_format_struct ** ret_fmt,struct ov7670_win_size ** ret_wsize)965 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
966 struct v4l2_mbus_framefmt *fmt,
967 struct ov7670_format_struct **ret_fmt,
968 struct ov7670_win_size **ret_wsize)
969 {
970 int index, i;
971 struct ov7670_win_size *wsize;
972 struct ov7670_info *info = to_state(sd);
973 unsigned int n_win_sizes = info->devtype->n_win_sizes;
974 unsigned int win_sizes_limit = n_win_sizes;
975
976 for (index = 0; index < N_OV7670_FMTS; index++)
977 if (ov7670_formats[index].mbus_code == fmt->code)
978 break;
979 if (index >= N_OV7670_FMTS) {
980 /* default to first format */
981 index = 0;
982 fmt->code = ov7670_formats[0].mbus_code;
983 }
984 if (ret_fmt != NULL)
985 *ret_fmt = ov7670_formats + index;
986 /*
987 * Fields: the OV devices claim to be progressive.
988 */
989 fmt->field = V4L2_FIELD_NONE;
990
991 /*
992 * Don't consider values that don't match min_height and min_width
993 * constraints.
994 */
995 if (info->min_width || info->min_height)
996 for (i = 0; i < n_win_sizes; i++) {
997 wsize = info->devtype->win_sizes + i;
998
999 if (wsize->width < info->min_width ||
1000 wsize->height < info->min_height) {
1001 win_sizes_limit = i;
1002 break;
1003 }
1004 }
1005 /*
1006 * Round requested image size down to the nearest
1007 * we support, but not below the smallest.
1008 */
1009 for (wsize = info->devtype->win_sizes;
1010 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
1011 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
1012 break;
1013 if (wsize >= info->devtype->win_sizes + win_sizes_limit)
1014 wsize--; /* Take the smallest one */
1015 if (ret_wsize != NULL)
1016 *ret_wsize = wsize;
1017 /*
1018 * Note the size we'll actually handle.
1019 */
1020 fmt->width = wsize->width;
1021 fmt->height = wsize->height;
1022 fmt->colorspace = ov7670_formats[index].colorspace;
1023
1024 info->format = *fmt;
1025
1026 return 0;
1027 }
1028
ov7670_apply_fmt(struct v4l2_subdev * sd)1029 static int ov7670_apply_fmt(struct v4l2_subdev *sd)
1030 {
1031 struct ov7670_info *info = to_state(sd);
1032 struct ov7670_win_size *wsize = info->wsize;
1033 unsigned char com7, com10 = 0;
1034 int ret;
1035
1036 /*
1037 * COM7 is a pain in the ass, it doesn't like to be read then
1038 * quickly written afterward. But we have everything we need
1039 * to set it absolutely here, as long as the format-specific
1040 * register sets list it first.
1041 */
1042 com7 = info->fmt->regs[0].value;
1043 com7 |= wsize->com7_bit;
1044 ret = ov7670_write(sd, REG_COM7, com7);
1045 if (ret)
1046 return ret;
1047
1048 /*
1049 * Configure the media bus through COM10 register
1050 */
1051 if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1052 com10 |= COM10_VS_NEG;
1053 if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1054 com10 |= COM10_HREF_REV;
1055 if (info->pclk_hb_disable)
1056 com10 |= COM10_PCLK_HB;
1057 ret = ov7670_write(sd, REG_COM10, com10);
1058 if (ret)
1059 return ret;
1060
1061 /*
1062 * Now write the rest of the array. Also store start/stops
1063 */
1064 ret = ov7670_write_array(sd, info->fmt->regs + 1);
1065 if (ret)
1066 return ret;
1067
1068 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1069 wsize->vstop);
1070 if (ret)
1071 return ret;
1072
1073 if (wsize->regs) {
1074 ret = ov7670_write_array(sd, wsize->regs);
1075 if (ret)
1076 return ret;
1077 }
1078
1079 /*
1080 * If we're running RGB565, we must rewrite clkrc after setting
1081 * the other parameters or the image looks poor. If we're *not*
1082 * doing RGB565, we must not rewrite clkrc or the image looks
1083 * *really* poor.
1084 *
1085 * (Update) Now that we retain clkrc state, we should be able
1086 * to write it unconditionally, and that will make the frame
1087 * rate persistent too.
1088 */
1089 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1090 if (ret)
1091 return ret;
1092
1093 return 0;
1094 }
1095
1096 /*
1097 * Set a format.
1098 */
ov7670_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1099 static int ov7670_set_fmt(struct v4l2_subdev *sd,
1100 struct v4l2_subdev_state *sd_state,
1101 struct v4l2_subdev_format *format)
1102 {
1103 struct ov7670_info *info = to_state(sd);
1104 struct v4l2_mbus_framefmt *mbus_fmt;
1105 int ret;
1106
1107 if (format->pad)
1108 return -EINVAL;
1109
1110 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1111 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
1112 if (ret)
1113 return ret;
1114 mbus_fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1115 *mbus_fmt = format->format;
1116 return 0;
1117 }
1118
1119 ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize);
1120 if (ret)
1121 return ret;
1122
1123 /*
1124 * If the device is not powered up by the host driver do
1125 * not apply any changes to H/W at this time. Instead
1126 * the frame format will be restored right after power-up.
1127 */
1128 if (info->on)
1129 return ov7670_apply_fmt(sd);
1130
1131 return 0;
1132 }
1133
ov7670_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1134 static int ov7670_get_fmt(struct v4l2_subdev *sd,
1135 struct v4l2_subdev_state *sd_state,
1136 struct v4l2_subdev_format *format)
1137 {
1138 struct ov7670_info *info = to_state(sd);
1139 struct v4l2_mbus_framefmt *mbus_fmt;
1140
1141 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1142 mbus_fmt = v4l2_subdev_state_get_format(sd_state, 0);
1143 format->format = *mbus_fmt;
1144 return 0;
1145 } else {
1146 format->format = info->format;
1147 }
1148
1149 return 0;
1150 }
1151
1152 /*
1153 * Implement G/S_PARM. There is a "high quality" mode we could try
1154 * to do someday; for now, we just do the frame rate tweak.
1155 */
ov7670_get_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * ival)1156 static int ov7670_get_frame_interval(struct v4l2_subdev *sd,
1157 struct v4l2_subdev_state *sd_state,
1158 struct v4l2_subdev_frame_interval *ival)
1159 {
1160 struct ov7670_info *info = to_state(sd);
1161
1162 /*
1163 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1164 * subdev active state API.
1165 */
1166 if (ival->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1167 return -EINVAL;
1168
1169 info->devtype->get_framerate(sd, &ival->interval);
1170
1171 return 0;
1172 }
1173
ov7670_set_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * ival)1174 static int ov7670_set_frame_interval(struct v4l2_subdev *sd,
1175 struct v4l2_subdev_state *sd_state,
1176 struct v4l2_subdev_frame_interval *ival)
1177 {
1178 struct v4l2_fract *tpf = &ival->interval;
1179 struct ov7670_info *info = to_state(sd);
1180
1181 /*
1182 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1183 * subdev active state API.
1184 */
1185 if (ival->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1186 return -EINVAL;
1187
1188 return info->devtype->set_framerate(sd, tpf);
1189 }
1190
1191
1192 /*
1193 * Frame intervals. Since frame rates are controlled with the clock
1194 * divider, we can only do 30/n for integer n values. So no continuous
1195 * or stepwise options. Here we just pick a handful of logical values.
1196 */
1197
1198 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
1199
ov7670_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval_enum * fie)1200 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
1201 struct v4l2_subdev_state *sd_state,
1202 struct v4l2_subdev_frame_interval_enum *fie)
1203 {
1204 struct ov7670_info *info = to_state(sd);
1205 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1206 int i;
1207
1208 if (fie->pad)
1209 return -EINVAL;
1210 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1211 return -EINVAL;
1212
1213 /*
1214 * Check if the width/height is valid.
1215 *
1216 * If a minimum width/height was requested, filter out the capture
1217 * windows that fall outside that.
1218 */
1219 for (i = 0; i < n_win_sizes; i++) {
1220 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1221
1222 if (info->min_width && win->width < info->min_width)
1223 continue;
1224 if (info->min_height && win->height < info->min_height)
1225 continue;
1226 if (fie->width == win->width && fie->height == win->height)
1227 break;
1228 }
1229 if (i == n_win_sizes)
1230 return -EINVAL;
1231 fie->interval.numerator = 1;
1232 fie->interval.denominator = ov7670_frame_rates[fie->index];
1233 return 0;
1234 }
1235
1236 /*
1237 * Frame size enumeration
1238 */
ov7670_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1239 static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
1240 struct v4l2_subdev_state *sd_state,
1241 struct v4l2_subdev_frame_size_enum *fse)
1242 {
1243 struct ov7670_info *info = to_state(sd);
1244 int i;
1245 int num_valid = -1;
1246 __u32 index = fse->index;
1247 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1248
1249 if (fse->pad)
1250 return -EINVAL;
1251
1252 /*
1253 * If a minimum width/height was requested, filter out the capture
1254 * windows that fall outside that.
1255 */
1256 for (i = 0; i < n_win_sizes; i++) {
1257 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1258
1259 if (info->min_width && win->width < info->min_width)
1260 continue;
1261 if (info->min_height && win->height < info->min_height)
1262 continue;
1263 if (index == ++num_valid) {
1264 fse->min_width = fse->max_width = win->width;
1265 fse->min_height = fse->max_height = win->height;
1266 return 0;
1267 }
1268 }
1269
1270 return -EINVAL;
1271 }
1272
1273 /*
1274 * Code for dealing with controls.
1275 */
1276
ov7670_store_cmatrix(struct v4l2_subdev * sd,int matrix[CMATRIX_LEN])1277 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
1278 int matrix[CMATRIX_LEN])
1279 {
1280 int i, ret;
1281 unsigned char signbits = 0;
1282
1283 /*
1284 * Weird crap seems to exist in the upper part of
1285 * the sign bits register, so let's preserve it.
1286 */
1287 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
1288 signbits &= 0xc0;
1289
1290 for (i = 0; i < CMATRIX_LEN; i++) {
1291 unsigned char raw;
1292
1293 if (matrix[i] < 0) {
1294 signbits |= (1 << i);
1295 if (matrix[i] < -255)
1296 raw = 0xff;
1297 else
1298 raw = (-1 * matrix[i]) & 0xff;
1299 } else {
1300 if (matrix[i] > 255)
1301 raw = 0xff;
1302 else
1303 raw = matrix[i] & 0xff;
1304 }
1305 ret = ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1306 if (ret)
1307 return ret;
1308 }
1309 return ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
1310 }
1311
1312
1313 /*
1314 * Hue also requires messing with the color matrix. It also requires
1315 * trig functions, which tend not to be well supported in the kernel.
1316 * So here is a simple table of sine values, 0-90 degrees, in steps
1317 * of five degrees. Values are multiplied by 1000.
1318 *
1319 * The following naive approximate trig functions require an argument
1320 * carefully limited to -180 <= theta <= 180.
1321 */
1322 #define SIN_STEP 5
1323 static const int ov7670_sin_table[] = {
1324 0, 87, 173, 258, 342, 422,
1325 499, 573, 642, 707, 766, 819,
1326 866, 906, 939, 965, 984, 996,
1327 1000
1328 };
1329
ov7670_sine(int theta)1330 static int ov7670_sine(int theta)
1331 {
1332 int chs = 1;
1333 int sine;
1334
1335 if (theta < 0) {
1336 theta = -theta;
1337 chs = -1;
1338 }
1339 if (theta <= 90)
1340 sine = ov7670_sin_table[theta/SIN_STEP];
1341 else {
1342 theta -= 90;
1343 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1344 }
1345 return sine*chs;
1346 }
1347
ov7670_cosine(int theta)1348 static int ov7670_cosine(int theta)
1349 {
1350 theta = 90 - theta;
1351 if (theta > 180)
1352 theta -= 360;
1353 else if (theta < -180)
1354 theta += 360;
1355 return ov7670_sine(theta);
1356 }
1357
1358
1359
1360
ov7670_calc_cmatrix(struct ov7670_info * info,int matrix[CMATRIX_LEN],int sat,int hue)1361 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1362 int matrix[CMATRIX_LEN], int sat, int hue)
1363 {
1364 int i;
1365 /*
1366 * Apply the current saturation setting first.
1367 */
1368 for (i = 0; i < CMATRIX_LEN; i++)
1369 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
1370 /*
1371 * Then, if need be, rotate the hue value.
1372 */
1373 if (hue != 0) {
1374 int sinth, costh, tmpmatrix[CMATRIX_LEN];
1375
1376 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1377 sinth = ov7670_sine(hue);
1378 costh = ov7670_cosine(hue);
1379
1380 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1381 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1382 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1383 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1384 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1385 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1386 }
1387 }
1388
1389
1390
ov7670_s_sat_hue(struct v4l2_subdev * sd,int sat,int hue)1391 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
1392 {
1393 struct ov7670_info *info = to_state(sd);
1394 int matrix[CMATRIX_LEN];
1395
1396 ov7670_calc_cmatrix(info, matrix, sat, hue);
1397 return ov7670_store_cmatrix(sd, matrix);
1398 }
1399
1400
1401 /*
1402 * Some weird registers seem to store values in a sign/magnitude format!
1403 */
1404
ov7670_abs_to_sm(unsigned char v)1405 static unsigned char ov7670_abs_to_sm(unsigned char v)
1406 {
1407 if (v > 127)
1408 return v & 0x7f;
1409 return (128 - v) | 0x80;
1410 }
1411
ov7670_s_brightness(struct v4l2_subdev * sd,int value)1412 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1413 {
1414 unsigned char com8 = 0, v;
1415
1416 ov7670_read(sd, REG_COM8, &com8);
1417 com8 &= ~COM8_AEC;
1418 ov7670_write(sd, REG_COM8, com8);
1419 v = ov7670_abs_to_sm(value);
1420 return ov7670_write(sd, REG_BRIGHT, v);
1421 }
1422
ov7670_s_contrast(struct v4l2_subdev * sd,int value)1423 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1424 {
1425 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1426 }
1427
ov7670_s_hflip(struct v4l2_subdev * sd,int value)1428 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1429 {
1430 unsigned char v = 0;
1431 int ret;
1432
1433 ret = ov7670_read(sd, REG_MVFP, &v);
1434 if (ret)
1435 return ret;
1436 if (value)
1437 v |= MVFP_MIRROR;
1438 else
1439 v &= ~MVFP_MIRROR;
1440 msleep(10); /* FIXME */
1441 return ov7670_write(sd, REG_MVFP, v);
1442 }
1443
ov7670_s_vflip(struct v4l2_subdev * sd,int value)1444 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1445 {
1446 unsigned char v = 0;
1447 int ret;
1448
1449 ret = ov7670_read(sd, REG_MVFP, &v);
1450 if (ret)
1451 return ret;
1452 if (value)
1453 v |= MVFP_FLIP;
1454 else
1455 v &= ~MVFP_FLIP;
1456 msleep(10); /* FIXME */
1457 return ov7670_write(sd, REG_MVFP, v);
1458 }
1459
1460 /*
1461 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1462 * the data sheet, the VREF parts should be the most significant, but
1463 * experience shows otherwise. There seems to be little value in
1464 * messing with the VREF bits, so we leave them alone.
1465 */
ov7670_g_gain(struct v4l2_subdev * sd,__s32 * value)1466 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1467 {
1468 int ret;
1469 unsigned char gain;
1470
1471 ret = ov7670_read(sd, REG_GAIN, &gain);
1472 if (ret)
1473 return ret;
1474 *value = gain;
1475 return 0;
1476 }
1477
ov7670_s_gain(struct v4l2_subdev * sd,int value)1478 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1479 {
1480 int ret;
1481 unsigned char com8;
1482
1483 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1484 if (ret)
1485 return ret;
1486 /* Have to turn off AGC as well */
1487 ret = ov7670_read(sd, REG_COM8, &com8);
1488 if (ret)
1489 return ret;
1490 return ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1491 }
1492
1493 /*
1494 * Tweak autogain.
1495 */
ov7670_s_autogain(struct v4l2_subdev * sd,int value)1496 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1497 {
1498 int ret;
1499 unsigned char com8;
1500
1501 ret = ov7670_read(sd, REG_COM8, &com8);
1502 if (ret == 0) {
1503 if (value)
1504 com8 |= COM8_AGC;
1505 else
1506 com8 &= ~COM8_AGC;
1507 ret = ov7670_write(sd, REG_COM8, com8);
1508 }
1509 return ret;
1510 }
1511
ov7670_s_exp(struct v4l2_subdev * sd,int value)1512 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1513 {
1514 int ret;
1515 unsigned char com1, com8, aech, aechh;
1516
1517 ret = ov7670_read(sd, REG_COM1, &com1) +
1518 ov7670_read(sd, REG_COM8, &com8) +
1519 ov7670_read(sd, REG_AECHH, &aechh);
1520 if (ret)
1521 return ret;
1522
1523 com1 = (com1 & 0xfc) | (value & 0x03);
1524 aech = (value >> 2) & 0xff;
1525 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1526 ret = ov7670_write(sd, REG_COM1, com1) +
1527 ov7670_write(sd, REG_AECH, aech) +
1528 ov7670_write(sd, REG_AECHH, aechh);
1529 /* Have to turn off AEC as well */
1530 if (ret == 0)
1531 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1532 return ret;
1533 }
1534
1535 /*
1536 * Tweak autoexposure.
1537 */
ov7670_s_autoexp(struct v4l2_subdev * sd,enum v4l2_exposure_auto_type value)1538 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1539 enum v4l2_exposure_auto_type value)
1540 {
1541 int ret;
1542 unsigned char com8;
1543
1544 ret = ov7670_read(sd, REG_COM8, &com8);
1545 if (ret == 0) {
1546 if (value == V4L2_EXPOSURE_AUTO)
1547 com8 |= COM8_AEC;
1548 else
1549 com8 &= ~COM8_AEC;
1550 ret = ov7670_write(sd, REG_COM8, com8);
1551 }
1552 return ret;
1553 }
1554
1555 static const char * const ov7670_test_pattern_menu[] = {
1556 "No test output",
1557 "Shifting \"1\"",
1558 "8-bar color bar",
1559 "Fade to gray color bar",
1560 };
1561
ov7670_s_test_pattern(struct v4l2_subdev * sd,int value)1562 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value)
1563 {
1564 int ret;
1565
1566 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0,
1567 value & BIT(0) ? TEST_PATTTERN_0 : 0);
1568 if (ret)
1569 return ret;
1570
1571 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1,
1572 value & BIT(1) ? TEST_PATTTERN_1 : 0);
1573 }
1574
ov7670_g_volatile_ctrl(struct v4l2_ctrl * ctrl)1575 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1576 {
1577 struct v4l2_subdev *sd = to_sd(ctrl);
1578 struct ov7670_info *info = to_state(sd);
1579
1580 switch (ctrl->id) {
1581 case V4L2_CID_AUTOGAIN:
1582 return ov7670_g_gain(sd, &info->gain->val);
1583 }
1584 return -EINVAL;
1585 }
1586
ov7670_s_ctrl(struct v4l2_ctrl * ctrl)1587 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
1588 {
1589 struct v4l2_subdev *sd = to_sd(ctrl);
1590 struct ov7670_info *info = to_state(sd);
1591
1592 switch (ctrl->id) {
1593 case V4L2_CID_BRIGHTNESS:
1594 return ov7670_s_brightness(sd, ctrl->val);
1595 case V4L2_CID_CONTRAST:
1596 return ov7670_s_contrast(sd, ctrl->val);
1597 case V4L2_CID_SATURATION:
1598 return ov7670_s_sat_hue(sd,
1599 info->saturation->val, info->hue->val);
1600 case V4L2_CID_VFLIP:
1601 return ov7670_s_vflip(sd, ctrl->val);
1602 case V4L2_CID_HFLIP:
1603 return ov7670_s_hflip(sd, ctrl->val);
1604 case V4L2_CID_AUTOGAIN:
1605 /* Only set manual gain if auto gain is not explicitly
1606 turned on. */
1607 if (!ctrl->val) {
1608 /* ov7670_s_gain turns off auto gain */
1609 return ov7670_s_gain(sd, info->gain->val);
1610 }
1611 return ov7670_s_autogain(sd, ctrl->val);
1612 case V4L2_CID_EXPOSURE_AUTO:
1613 /* Only set manual exposure if auto exposure is not explicitly
1614 turned on. */
1615 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1616 /* ov7670_s_exp turns off auto exposure */
1617 return ov7670_s_exp(sd, info->exposure->val);
1618 }
1619 return ov7670_s_autoexp(sd, ctrl->val);
1620 case V4L2_CID_TEST_PATTERN:
1621 return ov7670_s_test_pattern(sd, ctrl->val);
1622 }
1623 return -EINVAL;
1624 }
1625
1626 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1627 .s_ctrl = ov7670_s_ctrl,
1628 .g_volatile_ctrl = ov7670_g_volatile_ctrl,
1629 };
1630
1631 #ifdef CONFIG_VIDEO_ADV_DEBUG
ov7670_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)1632 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1633 {
1634 unsigned char val = 0;
1635 int ret;
1636
1637 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1638 reg->val = val;
1639 reg->size = 1;
1640 return ret;
1641 }
1642
ov7670_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)1643 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1644 {
1645 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1646 return 0;
1647 }
1648 #endif
1649
ov7670_power_on(struct v4l2_subdev * sd)1650 static void ov7670_power_on(struct v4l2_subdev *sd)
1651 {
1652 struct ov7670_info *info = to_state(sd);
1653
1654 if (info->on)
1655 return;
1656
1657 clk_prepare_enable(info->clk);
1658
1659 if (info->pwdn_gpio)
1660 gpiod_set_value(info->pwdn_gpio, 0);
1661 if (info->resetb_gpio) {
1662 gpiod_set_value(info->resetb_gpio, 1);
1663 usleep_range(500, 1000);
1664 gpiod_set_value(info->resetb_gpio, 0);
1665 }
1666 if (info->pwdn_gpio || info->resetb_gpio || info->clk)
1667 usleep_range(3000, 5000);
1668
1669 info->on = true;
1670 }
1671
ov7670_power_off(struct v4l2_subdev * sd)1672 static void ov7670_power_off(struct v4l2_subdev *sd)
1673 {
1674 struct ov7670_info *info = to_state(sd);
1675
1676 if (!info->on)
1677 return;
1678
1679 clk_disable_unprepare(info->clk);
1680
1681 if (info->pwdn_gpio)
1682 gpiod_set_value(info->pwdn_gpio, 1);
1683
1684 info->on = false;
1685 }
1686
ov7670_s_power(struct v4l2_subdev * sd,int on)1687 static int ov7670_s_power(struct v4l2_subdev *sd, int on)
1688 {
1689 struct ov7670_info *info = to_state(sd);
1690
1691 if (info->on == on)
1692 return 0;
1693
1694 if (on) {
1695 ov7670_power_on(sd);
1696 ov7670_init(sd, 0);
1697 ov7670_apply_fmt(sd);
1698 ov7675_apply_framerate(sd);
1699 v4l2_ctrl_handler_setup(&info->hdl);
1700 } else {
1701 ov7670_power_off(sd);
1702 }
1703
1704 return 0;
1705 }
1706
ov7670_get_default_format(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * format)1707 static void ov7670_get_default_format(struct v4l2_subdev *sd,
1708 struct v4l2_mbus_framefmt *format)
1709 {
1710 struct ov7670_info *info = to_state(sd);
1711
1712 format->width = info->devtype->win_sizes[0].width;
1713 format->height = info->devtype->win_sizes[0].height;
1714 format->colorspace = info->fmt->colorspace;
1715 format->code = info->fmt->mbus_code;
1716 format->field = V4L2_FIELD_NONE;
1717 }
1718
ov7670_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1719 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1720 {
1721 struct v4l2_mbus_framefmt *format =
1722 v4l2_subdev_state_get_format(fh->state, 0);
1723
1724 ov7670_get_default_format(sd, format);
1725
1726 return 0;
1727 }
1728
1729 /* ----------------------------------------------------------------------- */
1730
1731 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1732 .reset = ov7670_reset,
1733 .init = ov7670_init,
1734 .s_power = ov7670_s_power,
1735 .log_status = v4l2_ctrl_subdev_log_status,
1736 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1737 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1738 #ifdef CONFIG_VIDEO_ADV_DEBUG
1739 .g_register = ov7670_g_register,
1740 .s_register = ov7670_s_register,
1741 #endif
1742 };
1743
1744 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1745 .enum_frame_interval = ov7670_enum_frame_interval,
1746 .enum_frame_size = ov7670_enum_frame_size,
1747 .enum_mbus_code = ov7670_enum_mbus_code,
1748 .get_fmt = ov7670_get_fmt,
1749 .set_fmt = ov7670_set_fmt,
1750 .get_frame_interval = ov7670_get_frame_interval,
1751 .set_frame_interval = ov7670_set_frame_interval,
1752 };
1753
1754 static const struct v4l2_subdev_ops ov7670_ops = {
1755 .core = &ov7670_core_ops,
1756 .pad = &ov7670_pad_ops,
1757 };
1758
1759 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = {
1760 .open = ov7670_open,
1761 };
1762
1763 /* ----------------------------------------------------------------------- */
1764
ov7670_init_gpio(struct i2c_client * client,struct ov7670_info * info)1765 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
1766 {
1767 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1768 GPIOD_OUT_LOW);
1769 if (IS_ERR(info->pwdn_gpio)) {
1770 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
1771 return PTR_ERR(info->pwdn_gpio);
1772 }
1773
1774 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1775 GPIOD_OUT_LOW);
1776 if (IS_ERR(info->resetb_gpio)) {
1777 dev_info(&client->dev, "can't get %s GPIO\n", "reset");
1778 return PTR_ERR(info->resetb_gpio);
1779 }
1780
1781 usleep_range(3000, 5000);
1782
1783 return 0;
1784 }
1785
1786 /*
1787 * ov7670_parse_dt() - Parse device tree to collect mbus configuration
1788 * properties
1789 */
ov7670_parse_dt(struct device * dev,struct ov7670_info * info)1790 static int ov7670_parse_dt(struct device *dev,
1791 struct ov7670_info *info)
1792 {
1793 struct fwnode_handle *fwnode = dev_fwnode(dev);
1794 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
1795 struct fwnode_handle *ep;
1796 int ret;
1797
1798 if (!fwnode)
1799 return -EINVAL;
1800
1801 info->pclk_hb_disable = false;
1802 if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable"))
1803 info->pclk_hb_disable = true;
1804
1805 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1806 if (!ep)
1807 return -EINVAL;
1808
1809 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
1810 fwnode_handle_put(ep);
1811 if (ret)
1812 return ret;
1813
1814 if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) {
1815 dev_err(dev, "Unsupported media bus type\n");
1816 return -EINVAL;
1817 }
1818 info->mbus_config = bus_cfg.bus.parallel.flags;
1819
1820 return 0;
1821 }
1822
ov7670_probe(struct i2c_client * client)1823 static int ov7670_probe(struct i2c_client *client)
1824 {
1825 struct v4l2_fract tpf;
1826 struct v4l2_subdev *sd;
1827 struct ov7670_info *info;
1828 int ret;
1829
1830 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
1831 if (info == NULL)
1832 return -ENOMEM;
1833 sd = &info->sd;
1834 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1835
1836 sd->internal_ops = &ov7670_subdev_internal_ops;
1837 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1838
1839 info->clock_speed = 30; /* default: a guess */
1840
1841 if (dev_fwnode(&client->dev)) {
1842 ret = ov7670_parse_dt(&client->dev, info);
1843 if (ret)
1844 return ret;
1845
1846 } else if (client->dev.platform_data) {
1847 struct ov7670_config *config = client->dev.platform_data;
1848
1849 /*
1850 * Must apply configuration before initializing device, because it
1851 * selects I/O method.
1852 */
1853 info->min_width = config->min_width;
1854 info->min_height = config->min_height;
1855 info->use_smbus = config->use_smbus;
1856
1857 if (config->clock_speed)
1858 info->clock_speed = config->clock_speed;
1859
1860 if (config->pll_bypass)
1861 info->pll_bypass = true;
1862
1863 if (config->pclk_hb_disable)
1864 info->pclk_hb_disable = true;
1865 }
1866
1867 info->clk = devm_clk_get_optional(&client->dev, "xclk");
1868 if (IS_ERR(info->clk))
1869 return PTR_ERR(info->clk);
1870
1871 ret = ov7670_init_gpio(client, info);
1872 if (ret)
1873 return ret;
1874
1875 ov7670_power_on(sd);
1876
1877 if (info->clk) {
1878 info->clock_speed = clk_get_rate(info->clk) / 1000000;
1879 if (info->clock_speed < 10 || info->clock_speed > 48) {
1880 ret = -EINVAL;
1881 goto power_off;
1882 }
1883 }
1884
1885 /* Make sure it's an ov7670 */
1886 ret = ov7670_detect(sd);
1887 if (ret) {
1888 v4l_dbg(1, debug, client,
1889 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1890 client->addr << 1, client->adapter->name);
1891 goto power_off;
1892 }
1893 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1894 client->addr << 1, client->adapter->name);
1895
1896 info->devtype = i2c_get_match_data(client);
1897 info->fmt = &ov7670_formats[0];
1898 info->wsize = &info->devtype->win_sizes[0];
1899
1900 ov7670_get_default_format(sd, &info->format);
1901
1902 info->clkrc = 0;
1903
1904 /* Set default frame rate to 30 fps */
1905 tpf.numerator = 1;
1906 tpf.denominator = 30;
1907 info->devtype->set_framerate(sd, &tpf);
1908
1909 v4l2_ctrl_handler_init(&info->hdl, 10);
1910 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1911 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1912 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1913 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1914 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1915 V4L2_CID_VFLIP, 0, 1, 1, 0);
1916 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1917 V4L2_CID_HFLIP, 0, 1, 1, 0);
1918 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1919 V4L2_CID_SATURATION, 0, 256, 1, 128);
1920 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1921 V4L2_CID_HUE, -180, 180, 5, 0);
1922 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1923 V4L2_CID_GAIN, 0, 255, 1, 128);
1924 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1925 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1926 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1927 V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1928 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1929 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1930 V4L2_EXPOSURE_AUTO);
1931 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops,
1932 V4L2_CID_TEST_PATTERN,
1933 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0,
1934 ov7670_test_pattern_menu);
1935 sd->ctrl_handler = &info->hdl;
1936 if (info->hdl.error) {
1937 ret = info->hdl.error;
1938
1939 goto hdl_free;
1940 }
1941 /*
1942 * We have checked empirically that hw allows to read back the gain
1943 * value chosen by auto gain but that's not the case for auto exposure.
1944 */
1945 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1946 v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1947 V4L2_EXPOSURE_MANUAL, false);
1948 v4l2_ctrl_cluster(2, &info->saturation);
1949
1950 info->pad.flags = MEDIA_PAD_FL_SOURCE;
1951 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1952 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
1953 if (ret < 0)
1954 goto hdl_free;
1955
1956 v4l2_ctrl_handler_setup(&info->hdl);
1957
1958 ret = v4l2_async_register_subdev(&info->sd);
1959 if (ret < 0)
1960 goto entity_cleanup;
1961
1962 ov7670_power_off(sd);
1963 return 0;
1964
1965 entity_cleanup:
1966 media_entity_cleanup(&info->sd.entity);
1967 hdl_free:
1968 v4l2_ctrl_handler_free(&info->hdl);
1969 power_off:
1970 ov7670_power_off(sd);
1971 return ret;
1972 }
1973
ov7670_remove(struct i2c_client * client)1974 static void ov7670_remove(struct i2c_client *client)
1975 {
1976 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1977 struct ov7670_info *info = to_state(sd);
1978
1979 v4l2_async_unregister_subdev(sd);
1980 v4l2_ctrl_handler_free(&info->hdl);
1981 media_entity_cleanup(&info->sd.entity);
1982 }
1983
1984 static const struct ov7670_devtype ov7670_devdata = {
1985 .win_sizes = ov7670_win_sizes,
1986 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
1987 .set_framerate = ov7670_set_framerate_legacy,
1988 .get_framerate = ov7670_get_framerate_legacy,
1989 };
1990
1991 static const struct ov7670_devtype ov7675_devdata = {
1992 .win_sizes = ov7675_win_sizes,
1993 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
1994 .set_framerate = ov7675_set_framerate,
1995 .get_framerate = ov7675_get_framerate,
1996 };
1997
1998 static const struct i2c_device_id ov7670_id[] = {
1999 { .name = "ov7670", .driver_data = (kernel_ulong_t)&ov7670_devdata },
2000 { .name = "ov7675", .driver_data = (kernel_ulong_t)&ov7675_devdata },
2001 { /* sentinel */ }
2002 };
2003 MODULE_DEVICE_TABLE(i2c, ov7670_id);
2004
2005 static const struct of_device_id ov7670_of_match[] = {
2006 { .compatible = "ovti,ov7670", &ov7670_devdata },
2007 { /* sentinel */ }
2008 };
2009 MODULE_DEVICE_TABLE(of, ov7670_of_match);
2010
2011 static struct i2c_driver ov7670_driver = {
2012 .driver = {
2013 .name = "ov7670",
2014 .of_match_table = ov7670_of_match,
2015 },
2016 .probe = ov7670_probe,
2017 .remove = ov7670_remove,
2018 .id_table = ov7670_id,
2019 };
2020
2021 module_i2c_driver(ov7670_driver);
2022