xref: /linux/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) VF Ethernet Driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 #ifndef _OCTEP_VF_REGS_CN9K_H_
8 #define _OCTEP_VF_REGS_CN9K_H_
9 
10 /*############################ RST #########################*/
11 #define     CN93_VF_CONFIG_XPANSION_BAR         0x38
12 #define     CN93_VF_CONFIG_PCIE_CAP             0x70
13 #define     CN93_VF_CONFIG_PCIE_DEVCAP          0x74
14 #define     CN93_VF_CONFIG_PCIE_DEVCTL          0x78
15 #define     CN93_VF_CONFIG_PCIE_LINKCAP         0x7C
16 #define     CN93_VF_CONFIG_PCIE_LINKCTL         0x80
17 #define     CN93_VF_CONFIG_PCIE_SLOTCAP         0x84
18 #define     CN93_VF_CONFIG_PCIE_SLOTCTL         0x88
19 
20 #define     CN93_VF_RING_OFFSET                    BIT_ULL(17)
21 
22 /*###################### RING IN REGISTERS #########################*/
23 #define    CN93_VF_SDP_R_IN_CONTROL_START          0x10000
24 #define    CN93_VF_SDP_R_IN_ENABLE_START           0x10010
25 #define    CN93_VF_SDP_R_IN_INSTR_BADDR_START      0x10020
26 #define    CN93_VF_SDP_R_IN_INSTR_RSIZE_START      0x10030
27 #define    CN93_VF_SDP_R_IN_INSTR_DBELL_START      0x10040
28 #define    CN93_VF_SDP_R_IN_CNTS_START             0x10050
29 #define    CN93_VF_SDP_R_IN_INT_LEVELS_START       0x10060
30 #define    CN93_VF_SDP_R_IN_PKT_CNT_START          0x10080
31 #define    CN93_VF_SDP_R_IN_BYTE_CNT_START         0x10090
32 
33 #define    CN93_VF_SDP_R_IN_CONTROL(ring)          \
34 	(CN93_VF_SDP_R_IN_CONTROL_START + ((ring) * CN93_VF_RING_OFFSET))
35 
36 #define    CN93_VF_SDP_R_IN_ENABLE(ring)          \
37 	(CN93_VF_SDP_R_IN_ENABLE_START + ((ring) * CN93_VF_RING_OFFSET))
38 
39 #define    CN93_VF_SDP_R_IN_INSTR_BADDR(ring)          \
40 	(CN93_VF_SDP_R_IN_INSTR_BADDR_START + ((ring) * CN93_VF_RING_OFFSET))
41 
42 #define    CN93_VF_SDP_R_IN_INSTR_RSIZE(ring)          \
43 	(CN93_VF_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CN93_VF_RING_OFFSET))
44 
45 #define    CN93_VF_SDP_R_IN_INSTR_DBELL(ring)          \
46 	(CN93_VF_SDP_R_IN_INSTR_DBELL_START + ((ring) * CN93_VF_RING_OFFSET))
47 
48 #define    CN93_VF_SDP_R_IN_CNTS(ring)          \
49 	(CN93_VF_SDP_R_IN_CNTS_START + ((ring) * CN93_VF_RING_OFFSET))
50 
51 #define    CN93_VF_SDP_R_IN_INT_LEVELS(ring)          \
52 	(CN93_VF_SDP_R_IN_INT_LEVELS_START + ((ring) * CN93_VF_RING_OFFSET))
53 
54 #define    CN93_VF_SDP_R_IN_PKT_CNT(ring)          \
55 	(CN93_VF_SDP_R_IN_PKT_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
56 
57 #define    CN93_VF_SDP_R_IN_BYTE_CNT(ring)          \
58 	(CN93_VF_SDP_R_IN_BYTE_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
59 
60 /*------------------ R_IN Masks ----------------*/
61 
62 /** Rings per Virtual Function **/
63 #define    CN93_VF_R_IN_CTL_RPVF_MASK    (0xF)
64 #define	   CN93_VF_R_IN_CTL_RPVF_POS     (48)
65 
66 /* Number of instructions to be read in one MAC read request.
67  * setting to Max value(4)
68  **/
69 #define    CN93_VF_R_IN_CTL_IDLE                  BIT_ULL(28)
70 #define    CN93_VF_R_IN_CTL_RDSIZE                (0x3ULL << 25)
71 #define    CN93_VF_R_IN_CTL_IS_64B                BIT_ULL(24)
72 #define    CN93_VF_R_IN_CTL_D_NSR                 BIT_ULL(8)
73 #define    CN93_VF_R_IN_CTL_D_ESR                 BIT_ULL(6)
74 #define    CN93_VF_R_IN_CTL_D_ROR                 BIT_ULL(5)
75 #define    CN93_VF_R_IN_CTL_NSR                   BIT_ULL(3)
76 #define    CN93_VF_R_IN_CTL_ESR                   BIT_ULL(1)
77 #define    CN93_VF_R_IN_CTL_ROR                   BIT_ULL(0)
78 
79 #define    CN93_VF_R_IN_CTL_MASK     (CN93_VF_R_IN_CTL_RDSIZE | CN93_VF_R_IN_CTL_IS_64B)
80 
81 /*###################### RING OUT REGISTERS #########################*/
82 #define    CN93_VF_SDP_R_OUT_CNTS_START            0x10100
83 #define    CN93_VF_SDP_R_OUT_INT_LEVELS_START      0x10110
84 #define    CN93_VF_SDP_R_OUT_SLIST_BADDR_START     0x10120
85 #define    CN93_VF_SDP_R_OUT_SLIST_RSIZE_START     0x10130
86 #define    CN93_VF_SDP_R_OUT_SLIST_DBELL_START     0x10140
87 #define    CN93_VF_SDP_R_OUT_CONTROL_START         0x10150
88 #define    CN93_VF_SDP_R_OUT_ENABLE_START          0x10160
89 #define    CN93_VF_SDP_R_OUT_PKT_CNT_START         0x10180
90 #define    CN93_VF_SDP_R_OUT_BYTE_CNT_START        0x10190
91 
92 #define    CN93_VF_SDP_R_OUT_CONTROL(ring)          \
93 	(CN93_VF_SDP_R_OUT_CONTROL_START + ((ring) * CN93_VF_RING_OFFSET))
94 
95 #define    CN93_VF_SDP_R_OUT_ENABLE(ring)          \
96 	(CN93_VF_SDP_R_OUT_ENABLE_START + ((ring) * CN93_VF_RING_OFFSET))
97 
98 #define    CN93_VF_SDP_R_OUT_SLIST_BADDR(ring)          \
99 	(CN93_VF_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CN93_VF_RING_OFFSET))
100 
101 #define    CN93_VF_SDP_R_OUT_SLIST_RSIZE(ring)          \
102 	(CN93_VF_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CN93_VF_RING_OFFSET))
103 
104 #define    CN93_VF_SDP_R_OUT_SLIST_DBELL(ring)          \
105 	(CN93_VF_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CN93_VF_RING_OFFSET))
106 
107 #define    CN93_VF_SDP_R_OUT_CNTS(ring)          \
108 	(CN93_VF_SDP_R_OUT_CNTS_START + ((ring) * CN93_VF_RING_OFFSET))
109 
110 #define    CN93_VF_SDP_R_OUT_INT_LEVELS(ring)          \
111 	(CN93_VF_SDP_R_OUT_INT_LEVELS_START + ((ring) * CN93_VF_RING_OFFSET))
112 
113 #define    CN93_VF_SDP_R_OUT_PKT_CNT(ring)          \
114 	(CN93_VF_SDP_R_OUT_PKT_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
115 
116 #define    CN93_VF_SDP_R_OUT_BYTE_CNT(ring)          \
117 	(CN93_VF_SDP_R_OUT_BYTE_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
118 
119 /*------------------ R_OUT Masks ----------------*/
120 #define    CN93_VF_R_OUT_INT_LEVELS_BMODE            BIT_ULL(63)
121 #define    CN93_VF_R_OUT_INT_LEVELS_TIMET            (32)
122 
123 #define    CN93_VF_R_OUT_CTL_IDLE                    BIT_ULL(40)
124 #define    CN93_VF_R_OUT_CTL_ES_I                    BIT_ULL(34)
125 #define    CN93_VF_R_OUT_CTL_NSR_I                   BIT_ULL(33)
126 #define    CN93_VF_R_OUT_CTL_ROR_I                   BIT_ULL(32)
127 #define    CN93_VF_R_OUT_CTL_ES_D                    BIT_ULL(30)
128 #define    CN93_VF_R_OUT_CTL_NSR_D                   BIT_ULL(29)
129 #define    CN93_VF_R_OUT_CTL_ROR_D                   BIT_ULL(28)
130 #define    CN93_VF_R_OUT_CTL_ES_P                    BIT_ULL(26)
131 #define    CN93_VF_R_OUT_CTL_NSR_P                   BIT_ULL(25)
132 #define    CN93_VF_R_OUT_CTL_ROR_P                   BIT_ULL(24)
133 #define    CN93_VF_R_OUT_CTL_IMODE                   BIT_ULL(23)
134 
135 /* ##################### Mail Box Registers ########################## */
136 /* SDP PF to VF Mailbox Data Register */
137 #define    CN93_VF_SDP_R_MBOX_PF_VF_DATA_START    0x10210
138 /* SDP Packet PF to VF Mailbox Interrupt Register */
139 #define    CN93_VF_SDP_R_MBOX_PF_VF_INT_START     0x10220
140 /* SDP VF to PF Mailbox Data Register */
141 #define    CN93_VF_SDP_R_MBOX_VF_PF_DATA_START    0x10230
142 
143 #define    CN93_VF_SDP_R_MBOX_PF_VF_INT_ENAB         BIT_ULL(1)
144 #define    CN93_VF_SDP_R_MBOX_PF_VF_INT_STATUS       BIT_ULL(0)
145 
146 #define    CN93_VF_SDP_R_MBOX_PF_VF_DATA(ring)          \
147 	(CN93_VF_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CN93_VF_RING_OFFSET))
148 
149 #define    CN93_VF_SDP_R_MBOX_PF_VF_INT(ring)          \
150 	(CN93_VF_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CN93_VF_RING_OFFSET))
151 
152 #define    CN93_VF_SDP_R_MBOX_VF_PF_DATA(ring)          \
153 	(CN93_VF_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CN93_VF_RING_OFFSET))
154 #endif /* _OCTEP_VF_REGS_CN9K_H_ */
155