1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /*************************************************************************** 4 * Header for ines GPIB boards 5 * copyright : (C) 2002 by Frank Mori Hess 6 ***************************************************************************/ 7 8 #ifndef _INES_GPIB_H 9 #define _INES_GPIB_H 10 11 #include "nec7210.h" 12 #include "gpibP.h" 13 #include "plx9050.h" 14 #include "amcc5920.h" 15 #include "quancom_pci.h" 16 #include <linux/interrupt.h> 17 18 enum ines_pci_chip { 19 PCI_CHIP_NONE, 20 PCI_CHIP_PLX9050, 21 PCI_CHIP_AMCC5920, 22 PCI_CHIP_QUANCOM, 23 PCI_CHIP_QUICKLOGIC5030, 24 }; 25 26 struct ines_priv { 27 struct nec7210_priv nec7210_priv; 28 struct pci_dev *pci_device; 29 // base address for plx9052 pci chip 30 unsigned long plx_iobase; 31 // base address for amcc5920 pci chip 32 unsigned long amcc_iobase; 33 unsigned int irq; 34 enum ines_pci_chip pci_chip_type; 35 u8 extend_mode_bits; 36 }; 37 38 // interface functions 39 int ines_read(gpib_board_t *board, uint8_t *buffer, size_t length, int *end, size_t *bytes_read); 40 int ines_write(gpib_board_t *board, uint8_t *buffer, size_t length, 41 int send_eoi, size_t *bytes_written); 42 int ines_accel_read(gpib_board_t *board, uint8_t *buffer, size_t length, 43 int *end, size_t *bytes_read); 44 int ines_accel_write(gpib_board_t *board, uint8_t *buffer, size_t length, 45 int send_eoi, size_t *bytes_written); 46 int ines_command(gpib_board_t *board, uint8_t *buffer, size_t length, size_t *bytes_written); 47 int ines_take_control(gpib_board_t *board, int synchronous); 48 int ines_go_to_standby(gpib_board_t *board); 49 void ines_request_system_control(gpib_board_t *board, int request_control); 50 void ines_interface_clear(gpib_board_t *board, int assert); 51 void ines_remote_enable(gpib_board_t *board, int enable); 52 int ines_enable_eos(gpib_board_t *board, uint8_t eos_byte, int compare_8_bits); 53 void ines_disable_eos(gpib_board_t *board); 54 unsigned int ines_update_status(gpib_board_t *board, unsigned int clear_mask); 55 int ines_primary_address(gpib_board_t *board, unsigned int address); 56 int ines_secondary_address(gpib_board_t *board, unsigned int address, int enable); 57 int ines_parallel_poll(gpib_board_t *board, uint8_t *result); 58 void ines_parallel_poll_configure(gpib_board_t *board, uint8_t config); 59 void ines_parallel_poll_response(gpib_board_t *board, int ist); 60 void ines_serial_poll_response(gpib_board_t *board, uint8_t status); 61 uint8_t ines_serial_poll_status(gpib_board_t *board); 62 int ines_line_status(const gpib_board_t *board); 63 unsigned int ines_t1_delay(gpib_board_t *board, unsigned int nano_sec); 64 void ines_return_to_local(gpib_board_t *board); 65 66 // interrupt service routines 67 irqreturn_t ines_pci_interrupt(int irq, void *arg); 68 irqreturn_t ines_interrupt(gpib_board_t *board); 69 70 // utility functions 71 void ines_free_private(gpib_board_t *board); 72 int ines_generic_attach(gpib_board_t *board); 73 void ines_online(struct ines_priv *priv, const gpib_board_t *board, int use_accel); 74 void ines_set_xfer_counter(struct ines_priv *priv, unsigned int count); 75 76 /* inb/outb wrappers */ 77 static inline unsigned int ines_inb(struct ines_priv *priv, unsigned int register_number) 78 { 79 return inb(priv->nec7210_priv.iobase + 80 register_number * priv->nec7210_priv.offset); 81 } 82 83 static inline void ines_outb(struct ines_priv *priv, unsigned int value, 84 unsigned int register_number) 85 { 86 outb(value, priv->nec7210_priv.iobase + 87 register_number * priv->nec7210_priv.offset); 88 } 89 90 // pcmcia init/cleanup 91 92 int ines_pcmcia_init_module(void); 93 void ines_pcmcia_cleanup_module(void); 94 95 enum ines_regs { 96 // read 97 FIFO_STATUS = 0x8, 98 ISR3 = 0x9, 99 ISR4 = 0xa, 100 IN_FIFO_COUNT = 0x10, 101 OUT_FIFO_COUNT = 0x11, 102 EXTEND_STATUS = 0xf, 103 104 // write 105 XDMA_CONTROL = 0x8, 106 IMR3 = ISR3, 107 IMR4 = ISR4, 108 IN_FIFO_WATERMARK = IN_FIFO_COUNT, 109 OUT_FIFO_WATERMARK = OUT_FIFO_COUNT, 110 EXTEND_MODE = 0xf, 111 112 // read-write 113 XFER_COUNT_LOWER = 0xb, 114 XFER_COUNT_UPPER = 0xc, 115 BUS_CONTROL_MONITOR = 0x13, 116 }; 117 118 enum isr3_imr3_bits { 119 HW_TIMEOUT_BIT = 0x1, 120 XFER_COUNT_BIT = 0x2, 121 CMD_RECEIVED_BIT = 0x4, 122 TCT_RECEIVED_BIT = 0x8, 123 IFC_ACTIVE_BIT = 0x10, 124 ATN_ACTIVE_BIT = 0x20, 125 FIFO_ERROR_BIT = 0x40, 126 }; 127 128 enum isr4_imr4_bits { 129 IN_FIFO_WATERMARK_BIT = 0x1, 130 OUT_FIFO_WATERMARK_BIT = 0x2, 131 IN_FIFO_FULL_BIT = 0x4, 132 OUT_FIFO_EMPTY_BIT = 0x8, 133 IN_FIFO_READY_BIT = 0x10, 134 OUT_FIFO_READY_BIT = 0x20, 135 IN_FIFO_EXIT_WATERMARK_BIT = 0x40, 136 OUT_FIFO_EXIT_WATERMARK_BIT = 0x80, 137 }; 138 139 enum extend_mode_bits { 140 TR3_TRIG_ENABLE_BIT = 0x1, // enable generation of trigger pulse T/R3 pin 141 // clear message available status bit when chip writes byte with EOI true 142 MAV_ENABLE_BIT = 0x2, 143 EOS1_ENABLE_BIT = 0x4, // enable eos register 1 144 EOS2_ENABLE_BIT = 0x8, // enable eos register 2 145 EOIDIS_BIT = 0x10, // disable EOI interrupt when doing rfd holdoff on end? 146 XFER_COUNTER_ENABLE_BIT = 0x20, 147 XFER_COUNTER_OUTPUT_BIT = 0x40, // use counter for output, clear for input 148 // when xfer counter hits 0, assert EOI on write or RFD holdoff on read 149 LAST_BYTE_HANDLING_BIT = 0x80, 150 }; 151 152 enum extend_status_bits { 153 OUTPUT_MESSAGE_IN_PROGRESS_BIT = 0x1, 154 SCSEL_BIT = 0x2, // statue of SCSEL pin 155 LISTEN_DISABLED = 0x4, 156 IN_FIFO_EMPTY_BIT = 0x8, 157 OUT_FIFO_FULL_BIT = 0x10, 158 }; 159 160 // ines adds fifo enable bits to address mode register 161 enum ines_admr_bits { 162 IN_FIFO_ENABLE_BIT = 0x8, 163 OUT_FIFO_ENABLE_BIT = 0x4, 164 }; 165 166 enum xdma_control_bits { 167 DMA_OUTPUT_BIT = 0x1, // use dma for output, clear for input 168 ENABLE_SYNC_DMA_BIT = 0x2, 169 DMA_ACCESS_EVERY_CYCLE = 0x4,// dma accesses fifo every cycle, clear for every other cycle 170 DMA_16BIT = 0x8, // clear for 8 bit transfers 171 }; 172 173 enum bus_control_monitor_bits { 174 BCM_DAV_BIT = 0x1, 175 BCM_NRFD_BIT = 0x2, 176 BCM_NDAC_BIT = 0x4, 177 BCM_IFC_BIT = 0x8, 178 BCM_ATN_BIT = 0x10, 179 BCM_SRQ_BIT = 0x20, 180 BCM_REN_BIT = 0x40, 181 BCM_EOI_BIT = 0x80, 182 }; 183 184 enum ines_aux_reg_bits { 185 INES_AUXD = 0x40, 186 }; 187 188 enum ines_aux_cmds { 189 INES_RFD_HLD_IMMEDIATE = 0x4, 190 INES_AUX_CLR_OUT_FIFO = 0x5, 191 INES_AUX_CLR_IN_FIFO = 0x6, 192 INES_AUX_XMODE = 0xa, 193 }; 194 195 enum ines_auxd_bits { 196 INES_FOLLOWING_T1_MASK = 0x3, 197 INES_FOLLOWING_T1_500ns = 0x0, 198 INES_FOLLOWING_T1_350ns = 0x1, 199 INES_FOLLOWING_T1_250ns = 0x2, 200 INES_INITIAL_TI_MASK = 0xc, 201 INES_INITIAL_T1_2000ns = 0x0, 202 INES_INITIAL_T1_1100ns = 0x4, 203 INES_INITIAL_T1_700ns = 0x8, 204 INES_T6_2us = 0x0, 205 INES_T6_50us = 0x10, 206 }; 207 208 #endif // _INES_GPIB_H 209