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Searched refs:CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8195-vdo1.c78 GATE_VDO1_0(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 14),
H A Dclk-mt8188-vdo1.c82 GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 2),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h677 #define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 macro
H A Dmt8195-clk.h826 #define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 macro