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Searched refs:CLK_TOP_UNIVPLL_D5_D4 (Results 1 – 15 of 15) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt6779-clk.h81 #define CLK_TOP_UNIVPLL_D5_D4 71 macro
H A Dmt8183-clk.h106 #define CLK_TOP_UNIVPLL_D5_D4 70 macro
H A Dmt8186-clk.h111 #define CLK_TOP_UNIVPLL_D5_D4 92 macro
H A Dmt8192-clk.h105 #define CLK_TOP_UNIVPLL_D5_D4 93 macro
H A Dmediatek,mt8196-clock.h117 #define CLK_TOP_UNIVPLL_D5_D4 104 macro
H A Dmt8195-clk.h162 #define CLK_TOP_UNIVPLL_D5_D4 150 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c46 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
H A Dclk-mt8183.c62 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
H A Dclk-mt8188-topckgen.c53 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
H A Dclk-mt8192.c51 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
H A Dclk-mt8195-topckgen.c64 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
H A Dclk-mt6779.c55 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
H A Dclk-mt8196-topckgen.c221 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll", 1, 20),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi1380 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1381 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1481 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1482 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1504 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1520 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1536 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1552 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
H A Dmt8192.dtsi957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
958 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;