/linux/include/dt-bindings/clock/ |
H A D | mt8135-clk.h | 51 #define CLK_TOP_UNIVPLL2_D8 40 macro
|
H A D | mt7629-clk.h | 56 #define CLK_TOP_UNIVPLL2_D8 46 macro
|
H A D | mt7622-clk.h | 50 #define CLK_TOP_UNIVPLL2_D8 38 macro
|
H A D | mt6797-clk.h | 74 #define CLK_TOP_UNIVPLL2_D8 64 macro
|
H A D | mediatek,mt6795-clk.h | 77 #define CLK_TOP_UNIVPLL2_D8 66 macro
|
H A D | mt8173-clk.h | 79 #define CLK_TOP_UNIVPLL2_D8 69 macro
|
H A D | mt6765-clk.h | 63 #define CLK_TOP_UNIVPLL2_D8 28 macro
|
H A D | mediatek,mt8365-clk.h | 38 #define CLK_TOP_UNIVPLL2_D8 28 macro
|
H A D | mt2712-clk.h | 63 #define CLK_TOP_UNIVPLL2_D8 32 macro
|
H A D | mt2701-clk.h | 41 #define CLK_TOP_UNIVPLL2_D8 31 macro
|
/linux/drivers/clk/mediatek/ |
H A D | clk-mt6795-topckgen.c | 433 FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
|
H A D | clk-mt8173-topckgen.c | 512 FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
|
H A D | clk-mt8135.c | 72 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
|
H A D | clk-mt7622.c | 292 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
|
H A D | clk-mt7629.c | 399 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
|
H A D | clk-mt6797.c | 54 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
|
H A D | clk-mt2712.c | 71 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
|
H A D | clk-mt8365.c | 57 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
|
H A D | clk-mt6765.c | 113 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
|
H A D | clk-mt2701.c | 89 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
|