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Searched refs:CLK_TOP_SYSPLL_D5 (Results 1 – 24 of 24) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h14 #define CLK_TOP_SYSPLL_D5 7 macro
H A Dmt8135-clk.h41 #define CLK_TOP_SYSPLL_D5 30 macro
H A Dmt7629-clk.h42 #define CLK_TOP_SYSPLL_D5 32 macro
H A Dmt7622-clk.h36 #define CLK_TOP_SYSPLL_D5 24 macro
H A Dmt6797-clk.h56 #define CLK_TOP_SYSPLL_D5 46 macro
H A Dmediatek,mt6795-clk.h59 #define CLK_TOP_SYSPLL_D5 48 macro
H A Dmt8173-clk.h61 #define CLK_TOP_SYSPLL_D5 51 macro
H A Dmt6765-clk.h45 #define CLK_TOP_SYSPLL_D5 10 macro
H A Dmediatek,mt8365-clk.h25 #define CLK_TOP_SYSPLL_D5 15 macro
H A Dmt8183-clk.h81 #define CLK_TOP_SYSPLL_D5 45 macro
H A Dmt2712-clk.h44 #define CLK_TOP_SYSPLL_D5 13 macro
H A Dmt2701-clk.h14 #define CLK_TOP_SYSPLL_D5 4 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c74 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
H A Dclk-mt6795-topckgen.c413 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
H A Dclk-mt8173-topckgen.c492 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
H A Dclk-mt8135.c59 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
H A Dclk-mt7622.c278 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
H A Dclk-mt7629.c385 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
H A Dclk-mt6797.c36 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
H A Dclk-mt2712.c52 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5),
H A Dclk-mt8183.c45 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0),
H A Dclk-mt8365.c44 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
H A Dclk-mt6765.c93 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
H A Dclk-mt2701.c60 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),